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2006-10-27Fix the CHIP_NAME() entries of all mainboards to have the same formatUwe Hermann
and (hopefully) the correct canonical name of the vendor and board. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2476 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-24Change all occurences of NSC to nsc in the code. The next commitUwe Hermann
will then rename the src/superio/NSC directory to src/superio/nsc. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2472 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-24fix leftover typoStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2470 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-24fix typo during rename. Subversion would not let Yinghai Lu
me fix this before committing first. Signed-off-by: Yinghai Lu <yinghailu@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2469 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-24fix naming convention, turn X.Yinghai Lu
another commit is following Signed-off-by: Yinghai Lu <yinghailu@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2468 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-24rename Iwill to iwill to keep naming scheme consistentStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2467 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-24remove DK8HTX, it's an old duplicate version of dk8_htxStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2466 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-18add the CAFE IRQ supportRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2461 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-18add the btest mainboardRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2459 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-13change things that make no sense on ultra40. serial output now works!Ronald G. Minnich
Signed-off-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2453 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-12DK8 HTX with CAR and acpi, and easy support for HTXYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2452 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-06MEMCLK to DDRXXXYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2446 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-05K8_4RANK to QRANKYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2445 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-04get_bus_cong using sysconf insteadYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2442 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-04add missed asl for ht chainYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2441 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-04CONFIG_USE_PRINTK_IN_CAR and ht chain id for HTX support inYinghai Lu
serengeti_cheeatah git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2439 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-04AMD Rev F supportYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-21add irq for keyboard and mouse Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2432 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-20Lots of lx fixes. CLeanup mainly. THings now buildRonald G. Minnich
Signed-off-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2430 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-20This driver is a mistake, removing it.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2429 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-19commit moire changesRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2428 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-19add the msm800srv ; put the usb in the right place. Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2426 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-19add an OLPC target for qemuRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2422 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-18fix old bug in the src/devices/pci_device.c Ronald G. Minnich
add devices for the lx and artecgroup/dbe61 point artecgroup at cs5536_lx as it is so different. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2420 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-15fix variable name for ts5300Ronald G. Minnich
Signed-off-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2416 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-14additions and mods for lzma. Carl-Daniel Hailfinger
Signed-off-by: Carl-Daniel Hailfinger Signed-off-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2413 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-13new presents from artec group :-)Indrek Kruusa
Signed-off-by: Indrek Kruusa git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2411 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-13Add DCON support.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2409 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-13- fix irq routing for epia-mii cardbus slot. (signed off by Nick Barker)Stefan Reinauer
- some minor cleanups git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2407 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-13Fix the irq_tables ronald g. minnich
signed-off-by: ronald g. minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2403 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-13mods for qemu, these buildronald g. minnich
signed-off-by: ronald g. minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2402 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-07remove dangerous call to normal image; no backup on OLPCRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2399 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-25- Added suport for enabling USB P4 on the olpcRichard Smith
USB P4 is disabled by default and we need to setup the mux bits proper to make it work. This is the frame work for that. All thats needed is the right address values git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2387 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-17add smsc part. Mod sun board to use smsc part for nowRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2380 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-10change from AMD for the IRQ10 problem.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2370 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-09mods for the ultra40 bringup. This now builds.Ronald G. Minnich
amd gx2 north -- don't set anything in the north, it conflicts with vsa settings. So we have our own pci_set_resources that is essentially a no-op -- just calls the kids. olpc rev_a config -- DISABLE the compressed rom stream. This SHOULD NOT have been set -- it is untested and caused real trouble. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2369 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-08fix up the links for the ultra 40 -- i/o on ht 1 on each cpuRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2368 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-08fix up config space.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2367 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-07initial work on sunw ultra40. It's wrong :-)Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2366 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-04p2b uses i82371eb as well.Stefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2364 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-04final rename orgy. sorry for the inconvenience. This should fix it againStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2363 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-04rename southbridge i440bx to its actual name i8371ebStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2361 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-03Changelog:Indrek Kruusa
* src/cpu/amd/model_lx/model_lx_init.c L2 cache initialization removed (moved to northbridge.c) * src/include/cpu/amd/lxdef.h more checked values * src/northbridge/amd/lx/northbridge.c L2 cache initialization added cpubug() commented out * src/northbridge/amd/lx/raminit.c empty function sdram_set_registers() is in use, don't remove * src/mainboard/artecgroup/dbe61/Config.lb irqmap changes * src/mainboard/artecgroup/dbe61/irq_tables.c tentative changes to irq table (currently not in use) * src/mainboard/artecgroup/dbe61/mainboard.c irq assigned manually to NIC * src/mainboard/artecgroup/dbe61/Options.lb gcc 4.0 is OK * targets/artecgroup/dbe61/Config.lb 64K for VSA is OK at moment Signed-off-by: Indrek Kruusa <indrek.kruusa@artecdesign.ee> Signed-off-by: Andrei Birjukov <andrei.birjukov@artecdesign.ee> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-03slightly changed C.D. Hailfinger's precompressed rom stream patchStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2359 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-02Allow setting of serial port speed in EPIA-M config file.Jonathan McDowell
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2357 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-30- Fix some copy bugs and thinkos in the i440bx SMbusRichard Smith
read code. SBbus reads to RAM now work. Yah! - Rename the register constants to something I can look at more easily. - Make the logic flow match the flow from V1 assembly - #if 0 out other SMbus functions that are still broken. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2353 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-29- fixup Bitworks/IMS to use private copy of SMbus debug routinesRichard Smith
Re-enable the SPD dump routine in this Bitworks/IMS code and make it work like the Asus/p2b. This avoids having to hack the sdram/generic_dump_spd.c for a single mem controller. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2352 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-29- Add support _framework_ for the Asus p2b. Richard Smith
- New superIO winbond/w83977tf - Add single memory controller SBbus debug routine into a file private to the i440bx This adds support the start of support for an Asus p2b mainboard. Current limitations are the same as for the Bitworks IMS board. Reads from the SMbus don't work. Moving dump_spd_registers() into its own private copy solves the problem of having to go hack on the version that included in src/sdram to only do one memory controller. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2351 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-28This patch adds support for the AMD LX cpu. Ron Minnich
There is one global change to pci_ids.h. The rest are changes for LX. I ran abuild and it is ok. Not all artec design changes are included as some of them would adversely affect other mainboards. Indrek will need to test. Signed-off-by: Ron Minnich Signed-off-by: Indrek Kruusa, indrek.kruusa@artecdesign.ee, artec design. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-24add framework for i440bx chipsetRichard Smith
add support for NSC pc87351 SuperIO add Bitworks/IMS manboard config This is a very basic framework for the i440bx chipset and the Bitworks IMS board that uses it. Most things are structure only. Known issues: - SMbus reads to the RAM SPD come back all zero. - dump_spd_registers() is commented out since it breaks with the default setting of generic_dump_spd.c where it wants 2 memory controllers. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2347 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-21These changes incorporate steve goodrich'es fixes, and one bug that isRonald G. Minnich
disabled. cs5536: add new entires for SB control etc. cs5536.c: chip_enabled function moved to chip_init, so it only gets run once. IRQ setup improved gx2def.h: new defines added vr.h: new file, with new def's for virtual register control. mainboard config.lb: new entries added for nb and sb control. chipsetinit.c: new controls added -- I forget all the details :-) grphinit.c: new function added northbridge.c: new IRQ control added. FlashChipSetup added, controlled by chip info setupflash struct member. Currently, if enabled, this hangs OLPC in linux PCI scan. chip.h: new struct members added for unwanted device enable, flash setup git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2345 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-19closing issue 44: rename ram clocks in cmos.layoutStefan Reinauer
https://openbios.org/roundup/linuxbios/issue44 git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2340 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-18fixing aruma build as suggested by mail ;-)Stefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2339 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-18sorry for the inconvenience. this is a test commit.Stefan Reinauer
breaking a build is intentional. It will be fixed in a bit. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2338 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-06-27fix interrupt for f5 (ehci)Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2335 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-06-24fix typo on duplicate line.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2331 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-06-23fix compilation of s2892.Stefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2330 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-06-22set up interrupt values for the southbridge, and add a function toRonald G. Minnich
manage them. Make pci_level_irq global. Add value settings for OLPC rev_a board. Comment out no-longer-needed code in olpc mainboard.c -- it is replaced by the settings in Config.lb, and the support in cs5536.c git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2328 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-06-18delete two empty filesStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2326 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-06-18fix idiiot typo I did not catch.Ronald G. Minnich
add support for conditional enable of uarta interrupt. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2324 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-06-18add irq mapper support for OLPC and other boards that need this mappingRonald G. Minnich
done for the gx2 north. tested on OLPC. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2323 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-06-10changes from AMD for making OLPC video work.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2316 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-06-08further development of OLPC. Set vsm size to 35k. add PCI IRQ for USB. Ronald G. Minnich
Set linuxbios size to 28k. Drop debug level to 8. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2315 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-26fix two mainboards that have been broken by someone who does not use abuild.shStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2313 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-25add DK8HTX support. Ronald G. Minnich
VSAs now required to be nrv2 compressed git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2312 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-18co processor support with s2891Yinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2310 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-18cleanup some of the compressed rom stream ugliness -- more to do!Ronald G. Minnich
olpc and rumba can now boot linux out of flash. vsa was resized to 64K. olpc and rumba now used compressed payload -- thanks stefan! git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2307 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-16Commit for IDE NAND FLASHRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2306 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-12correct it, finally.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2304 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-12memory size in cf07Ronald G. Minnich
goodrich pll code disable havedmi git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2303 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-05reorder early startup so that it might work.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2298 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-04don't wait core0 started twiceYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2295 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-03more changes; rumba enet works fine now.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2290 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-02enable compressed payload per defaultStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2289 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-02Fall back to pre-broken settings and setup for GX2. Ronald G. Minnich
We lost a few things, but this is still worth it. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2287 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-27we don't need msr_initRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2281 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-26some todo and comment for ron.Li-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2280 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-25set irq options.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2278 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-25fix the msr.lo for olpc 0x20000019Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2275 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-23Adds a CONFIG_MAX_PCI_BUSES to pci_locate_device()Richard Smith
Default is 255. This allows mainboard configs for working across various groups of boards that differ a device that may not loaded. If you search for a device that is not loaded and max buses is 255 then there can be up to a 8 second delay to search the entire PCI space. Board configs that know thier max bus can limit this search space. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2273 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-23fix so that olpc uarts come up enabled.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-20change to 5536Li-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2268 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-20change to 5536Li-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2267 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-20boot to kernelLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2264 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-19resolve conflictLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2260 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-18add back in missing lineRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2258 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-18set up timingRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2257 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-18add ram resourcesRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2256 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-18added the olpc target and supportRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2255 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-13add SystemPreInit() and supportRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2254 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-10add cpureginit to romcc code.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-08drop unsupported momentum apache board. Check Stefan Reinauer
http://snapshots.linuxbios.org/stats/abuild-LinuxBIOSv2-2247.log git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2247 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-06pseudo fix xe7501devkitStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2243 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-06break the tree really quick due to svn restrictions, next commit fill fix itStefan Reinauer
again. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2240 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-06more fix for vsm, not working yetLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2237 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-03did I commit the last change?Li-Ta Lo
try to fix 0x10000026 git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2235 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-03comment out reset from MB ConfigYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2234 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-03comment out reset in MB ConfigYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2233 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-03new cache_as_ram support Yinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-01- Adds support for the Advantech eval board. Configuration was producedRichard Smith
on a SOM-DB2301 baseboard with a SOM-2354 cpu module. - Also does a slight tweak to the ram test code to make it more obvious when it fails. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2231 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 16:51:14 +0000