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Enable/disable LTE function based on LTE field of FW_CONFIG.
1. GPIO control
2. USB port setting
BUG=b:213582491
BRANCH=dedede
TEST=FW_NAME=beadrix emerge-dedede coreboot
Change-Id: Icea44992e2e3195d1fd9a888f5ce4650f82280bb
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62801
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This CL adds the delay time into the RTD3 sequence, which will turn
off the eMMC controller (a true D3cold state) during the RTD3 sequence.We checked power on sequence requires enable pin prior to reset pin, added delay to meet the sequence and test passed on various eMMC SKUs.Base on BH799BB_Preliminary_DS_R079_20201124.pdf in chapter 7.2.
BUG=b:224648680
TEST=USE="project_primus" emerge-brya coreboot chromeos-bootimage
test suspend stress 2500 cycles passed on primus
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I1ab4fdf0ee73b819b3c203e995ac9d5ae0d24bd0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Commit 5a0ad1186 missed one chip config member that got converted to
snake case in commit 215a97ee1.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie92106f0fee0bb18863b7063c07673e0f7995c74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63005
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Martin L Roth <martinroth@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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init overridetree.cb based on the schematic adl_rfq_mb_20220310.pdf
BUG=b:220814038
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I8829d4b39d48ae574eeccbfc62e79b671211ae2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Set the GPIO configuration of crota by bernadino 14 adl-p 20220112.pdf
BUG=b:219891328
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I164bc7a8b682eb8682f02b06708bc7c72a5c449a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Kinox is designed to 8-layer PCB. In order to reduce the length of
memory singals, the DDR4 is designed from interleaved to
non-interleaved.
BUG=b:210094309
TEST=emerge-brask coreboot
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I03c6fcccf8b1646cec1a35cc1f9cbb1cfb942c4e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
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GL9763e doesn’t support L0s state, so disable L0s at the root port.
BUG=b:220079865
TEST=Build FW and run stress exceed 2500 cycles.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I6ed790c833d1c01a30aed0fd09cac260a3837ead
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
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The workaround causes the eMMC controller to not enter its L1
during the boot process
BUG=b:220079865
TEST=Build FW and run stress exceed 2500 cycles.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I142a816611e204e6c8577d15b3f0a0e08251f848
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
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The cpu device listed in MediaTek platforms' devicetree.cb doesn't
actually do anything, except causing an error during device
initialization:
CPU: 00 missing read_resources
Therefore, remove it from the devicetree.
BUG=b:224419346
TEST=emerge-corsola coreboot
TEST=Krabby booted up successfully
BRANCH=none
Change-Id: Ibf9f7cf65da6a0dd0a0e1f556d5772573ba3e930
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62805
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The APCB files that provide the firmware components running on the PSP
some mainboard-specific information like the DRAM interface
configuration. Those files aren't yet in the upstream 3rdparty/blobs
repository, so only add those files if they are present and print that
no APCB was added and the image won't boot if they aren't present.
TEST=Both cases behave as expected.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1e8621901741b8b0531fe134273b47e85911e19f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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To have enough space in the A/B RW sections, increase those sizes to 4
MByte and decrease the RO section size to 6 MByte to free up the space
needed for that.
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib107fd05cfb0ef7de95425abcce6c82b88a9835d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Add WiFi SAR table
BUG=b:225285426
TEST=emerge-brya chromeos-config chromeos-config-bsp-private
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage
and checked SAR table can load by WiFi driver.
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I8fa833409bd69e080fda735c89015b9548252190
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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ALC5682-VD/ALC5682I-VS load different kernel driver by different hid
name. Update hid name and machine_dev depending on the AUDIO_CODEC_SOURCE
field of fw_config. Define FW_CONFIG bits 36 - 37 (SSFC bits 4 - 5)
for codec selection.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:211672259
BRANCH=firmware-zork-13434.B
TEST=ALC5682I-VS audio codec can work
Change-Id: Icd4321ec0a284e35511dd4b860a16506f54cf663
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-hsuan Hsu <yuhsuan@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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ALC5682-VD/ALC5682I-VS load different kernel driver by different hid
name. Update hid name and machine_dev depending on the AUDIO_CODEC_SOURCE
field of fw_config. Define FW_CONFIG bits 36 - 37 (SSFC bits 4 - 5)
for codec selection.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:215292608
BRANCH=firmware-zork-13434.B
TEST=ALC5682I-VS audio codec can work
Change-Id: I0b0231a3ee9c0dad289ffd50607b3ae6201f56a0
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-hsuan Hsu <yuhsuan@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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This was to merge PCIe ACPI code to WWAN device. Also, RTD3 devices are
add to overridetree.cb where WWAN is present for vell.
BUG=none
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Change-Id: If27abcf31ed948899bfaecbe8ef494fe8a80609b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The patch deselects ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR Kconfig which
updates PMC settings in the IFD for Alder Lake A0 silicon.
As Alder Lake A0 is intermediate stepping, and the IFD is locked in the
production systems, so the Kconfig is deselected.
BUG=b:190588098
BRANCH=firmware-brya-14505.B
TEST=Build the coreboot for Gimble
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I81fe7c792dd82d9d547d318ebda55ee4a0f3ac96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Although the panel initializes fine and the fw recovery screen is
displayed without issues, the current power-on sequence of the
PS8640 violates the spec of the PS8640, which can be confirmed by
measuring it with an oscilloscope.
The sequence is:
- set VDD12 to be 1.2V
- set VDD33 to be 3.3V
- pull hign PD#
- pull down RST#
- delay 2ms
- pull high RST#
- delay more than 50ms (55ms for margin)
- pull down RST#
- delay more than 50ms (55ms for margin)
- pull high RST#
This flow will increase 110ms if firmware display is enabled in
krabby. For normal booting flow, the firmware will not be enabled,
so it will meet boot time requirements of Chrome OS. (Less than 1s.)
Datasheet name: PS8640_DS_V1.4_20200210.docx.
Chapter: 14.
BUG=b:222650141
TEST=show fw display normally in krabby.
TEST=result of waveform meets the spec.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I7706c56dc7fc13ac84c0d52a6e534bc0988e8fd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Right now, the PSPP policy that controls if the PCIe lanes can be
dynamically downgraded to a lower speed to save some power needs to be
disabled in order for the link training to be successful. Once this
feature is working, PSPP will be reenabled.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6ea602596acb8e5ea92076386e80102c3bc757af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
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Right now, the PSPP policy that controls if the PCIe lanes can be
dynamically downgraded to a lower speed to save some power needs to be
disabled in order for the link training to be successful. Once this
feature is working, the PSPP policy will be switched to balanced again.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I85a06f322c4ddff25c3a858e2b79c84b36c48932
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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The touchscreen slave address for landrid is 0x10 same as lantis, so we use SSFC to switch touchscreen controller.
BUG=b:222976965
TEST=emerge-dedede coreboot
Change-Id: I23d3de5e45aa2876c1590a1e09679d652a3f2906
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Use GEN3 from enum dxio_link_speed_cap instead of the number 3.
TEST=Timeless build results in identical firmware image for guybrush
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0dddc57e05ec2395ca980bb63320bb9ee5242c29
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Commit 215a97ee1c4cd87b266d63e32bf0b379e18fe849 (soc/intel/adl/chip.h:
Convert all camel case variables to snake case) converted the camel case
used in the parameter name to snake case, but
commit bd529e2e200a8fbfd455dd62be0494a2b727b9a5 (mb/google/nissa/var/
nivviks: Add TcssAuxori for nivviks) still used the old names which
breaks the upstream build. his patch is intended to be merged via
fast-path before the 24h are over to fix the tree.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2b9049553889c77bd8c59a2c4564d36d836a4eea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62927
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable SBU orientation handling by SoC for both USBC port0 and USBC
port1. Nivviks USBC port0 do not have retimer, USBC port1 has redriver,
but that do not flip the data lines. Hence we need to set bits for both
the USBC ports.
BRANCH:None
TEST=emerge-nissa coreboot chromeos-bootimage. Flash the image on
nivviks board and verified USBC display is working on both the ports in
normal and inverted connections.
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I219de6092ac9a9c773adbaa99f5a7d6196a2c937
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62731
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Based on the latest schematic, replace amp max98357 with max98360.
BUG=b:224692387, b:216110896
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Id265a4276c3f8b5553a0e5d7ed824b1d9a520d44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62887
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add wifi sar for galnat/galnat360
Use SKU ID to load wifi table.
Each Project and SKU ID correspond as below
galtic (sku id:0x120000)
galith (sku id:0x130000)
galnat (sku id:0x140000)*
gallop (sku id:0x150000)
galtic360 (sku id:0x260000)
galith360 (sku id:0x270000)
galnat360 (sku id:0x2B0000)*
BUG=b:222008376
TEST=emerge-dedede coreboot chromeos-bootimage \
coreboot-private-files-baseboard-dedede
verify the SAR table is correct in each project
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I868a7416a002732736cabea48ce80548ea75e517
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Volmar does not support Thunderbolt, therefore disable all of the TBT
devices in the devicetree. The volmar fit image had been disabled already, cf. chrome-internal:4459289.
BUG=b:2233193
TEST=Build and run on DUT.
Change-Id: Ic1bba80707b1d4a97c486e22f79feccf6241865e
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Configure GPIOs according to updated schematics.
- GPP_A21 from NC to TCP_DP1_CTRLCLK.
- GPP_A22 from NC to TCP_DP1_CTRLDATA.
- GPP_E22 from DDIA_DP_CTRLCLK to NC.
- GPP_E23 from DDIA_DP_CTRLDATA to NC.
BUG=b:214025396
TEST=emerge-brask coreboot
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I9d2d73820fbb191b682713e4e351c6375927ddf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This sets EPP value to be 45% for all Adl RVP variants.
Historically, EPP Ratio has always been 50% (128) on Chrome platforms.
But on Intel Alderlake EPP ratio of 45% is recommended for optimal
power and performance on Chrome platforms.
TEST=
Use 'iotools rdmsr [cpu id] 0x774' command and check field 32:24 = 0x73.
Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: If83a2148d596efccd2e50cc82f1afcbfb9ebb935
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
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1.Change I2S GPP_Sx (S0-S3) Native PAD Configuration from NF2 to NF4
2.Select CS35l53 AMP driver for Vell variant.
Change-Id: I96d49bd1a2ba061c4fd52b450b31d0885f49552c
Signed-off-by: Shon.Wang <shon.wang@quanta.corp-partner.google.com>
Signed-off-by: Vitaly Rodionov <vitaly.rodionov@cirrus.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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BUG=b:224618411
TEST=util/abuild/abuild -t GOOGLE_SKYRIM with and without APCB
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I71b30a5716f2e0d60d07a0ec29f98609c1f2a8b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Needed so i2c communication works.
BUG=b:224618411
TEST=build skyrim
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8ec7c18cae509b5683cb73153fd6d3747cf9d753
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62874
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This will fix:
> [INFO ] Probing TPM I2C: tis_plat_irq_status() not implemented, wasting 20ms to wait on Cr50!
BUG=b:224618411
TEST=Compile skyrim
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5add694506ad089adcc8961f101bf507bc39a522
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62873
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use C code to generate MS0X entry and provide variant hook.
BUG=b:207144468
TEST=check SSDT table has the same entry.
Scope (\_SB)
{
Method (MS0X, 1, Serialized)
{
If ((Arg0 == One))
{
\_SB.PCI0.CTXS (0x148)
}
Else
{
\_SB.PCI0.STXS (0x148)
}
}
}
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ic36543e5cbaf8aaa7d933dcf54badc5f40e8ef02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This was to merge PCIe ACPI code to WWAN device. But, now use recent
_DSD generation changes in FM driver instead. PCie generic driver is
not used for WWAN at this time.
Also, RTD3 devices are moved to overridetree.cb where WWAN is
present.
BUG=b:221250331
BRANCH=firmware-brya-14505.B
TEST=
Check that _DSD is added to WWAN device in SSDT for the variants.
Check that RTD3 is added to WWAN device in SSDT for the variants.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ia343c7545cf30bdbcd1de19e5eb84049dbb2977f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Follow thermal team design to update thermal table.
BUG=b:223492897
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I5da776e7ae3368ce00cd29ec0ccdb5b7a725ff88
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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For galnat platform, support 2nd ELAN touchscreen via SSFC.
Define FW_CONFIG bits 39 - 40 (SSFC bits 7-8)
for touchscreen controller switch.
BUG=b:221002826
TEST=touch screen is functional.
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Id3501205b147c9dc3c96ce8381a3e7492ae8258e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
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Modify 15W SOC default power settings for kinox.
- PL2 39W
- PL4 100W
- Psys_PL2 65W
- Psys_imax_ma 5000ma
- bj_volts_mv 20000mv
BUG=b:213417026, b:222599762
TEST=emerge-brask coreboot
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I2956705f7d26929c7cf2dd4e852fc61b619a83e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62627
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1.Assert eMMC enable pin in bootblock
2.Deassert eMMC reset pin in bootblock
BUG=b:220821454
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I924fcdadaae8ed29b50369a55bad00983cf6ba19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Follow the latest schematic change, gpio will match the baseboard.
Return the current table as override.
BUG=b:223677877
TEST=audio is functional on board_0.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I91dc2c9c8811d403c60a4b4f3a7c5ed8de4e527e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
Move selects from Kconfig.name to Kconfig so that the configuration is
in one place and not distributed over two files.
Change-Id: I500f6422c1f8975de8b0bcc8b95cba2bcd4ebe27
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
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Enable PCIe-eMMC bridge for Kinox.
BUG=b:218786363, b:211176722
TEST=emerge-brask coreboot
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Iec34708e5879c47f5339c48fd996eb6d7ef0ee86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Follow the Thermal_paramters_list-0314.xlsx to modify DPTF/Fan parameters.
BUG=b:221180425, b:222020226, b:221182596
TEST=emerge-brask coreboot
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I5f44120430029130d38b89d0eab6bbf205aca929
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Rename `BOARD_HP_SNB_IVB_LAPTOPS` to `BOARD_HP_SNB_IVB_LAPTOPS_COMMON`
to indicate and to make it clear that this option serves as base for
others.
Built HP EliteBook Revolve 810 G1 with BUILD_TIMELESS=1 and also with
`INCLUDE_CONFIG_FILE` disabled. coreboot.rom remains identical.
Change-Id: Icadeb8a33ae0787d2cd5da460065a2ed15256d64
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Built HP EliteBook Revolve 810 G1 with BUILD_TIMELESS=1 and
coreboot.rom remains identical.
Change-Id: I54367c7c663ad288ccdcbd4e7289546489a68f30
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Based on the schematic carbine_adl-p_dvt_20211104.pdf, the GPP_D0 is
directly connected to FP module, Set GPP_D0 to GPO, DUT can flash FP
firmware successfully.
BUG=b:222188263, b:223906569
TEST=USE="project_gimble emerge-brya coreboot" and run the Fingerprint
Firmware Test.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I164ffff6bd3b4058d6e28247eb7c3ed46d3891b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
All TGL mainboards are setting DIMM_SPD_SIZE to 512. Thus, default to
512 in the SoC Kconfig and drop it from the mainboard Kconfigs.
Change-Id: I9fd947b61c984e10bd5fba20b73280b08623a008
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62766
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:219616787
BRANCH=guybrush
TEST=emerge-guybrush coreboot
update the thermal setting value by measurement and
pass the thermal performance test
Change-Id: I3ba3ab990d5362c6f02d2ee5a023f4c5cca7fa45
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
|
|
Using the GPP_F19 as privacy switch for camera in banshee.
BUG=b:223712143, b:216110896
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I67d65347ceac7152f1951018a633a2e93ee84e14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
C1-state auto demotion feature allows hardware to determine C1-state as
per platform policy. Since Brya sets performance policy to balanced from
hardware, auto demotion can be disabled without performance impact.
Also, disabling this feature results in 110 mW power savings during
video playback.
Note that C1state Autodemotion feature is not applicable for ADL-P SoC.
Hence recommendation is to keep it disabled.
BUG=b:221876248
BRANCH=firmware-brya-14505.B
TEST=Code compiles and correct value of c1-state auto demotion is passed
to FSP. Also power and performance impact has been measure by respective
teams.
Change-Id: I41eea916cdfe4a86e4d263e3191f5cb40fa33a90
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
|
|
coreboot chip.h files mainly contains variable which allows board to
fill platform configuration through devicetree.
Since many of this configuration involves FSP UPDs, variable names were
in camel case which aligned with UPD naming convention.
By default coreboot follow snake case variable naming, so cleaning up
file to align all variable names as per coreboot convention.
During renaming process, this patch also removes unused variables
listed below:
-> SataEnable // Checked in SoC code based on PCI dev enabled status
-> ITbtConnectTopologyTimeoutInMs // SoC always passes 0, so not used
Note: Since separating out changes into smaller CL might break the
compilation for the patch set, this is being pushed as a single big CL.
BUG=None
BRANCH=firmware-brya-14505.B
TEST=All boards using ADL SoC compiles with the CL.
Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Commit hash b8b40964 ( mb, soc: Add the SPD_CACHE_ENABLE) introduced
per mainboard logic to invalidate the mrc_cache.
This patch moves mrc_cache invalidating logic into IA common code and
cleans up the code to remove unused argument `dimms_changed` from SoC
and mainboard directory.
BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=Able to build and boot redrix without any visible failure/errors.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6f18e18adc6572571871dd6da1698186e4e3d671
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
|
|
This patch modifies `memcfg_init` and `variant_memory_init`functions
argument from FSP_M_CONFIG to FSPM_UPD.
This change in `memcfg_init()` argument will help to update the
architectural FSP-M UPDs from common code blocks rather than going
into SoC and/or mainboard implementation.
BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=Able to build and boot redrix without any visible failure/errors.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3002dd5c2f3703de41f38512976296f63e54d0c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
|
|
Hoglin and Herobrine (proto1) should share majority of GPIOs.
Conslidating the QUP initializations in mainboard. Also, putting
fingerprint init in a conditional as not all devices will have an FP
sensor.
BUG=b:182963902,b:223826899
BRANCH=None
TEST=booted BIOS on hoglin and check for i2c errors in dmesg
Change-Id: I48ce42760f2c75f04619b967a05909d2b3f28e2c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
New board introduced to trogdor family.
BUG=b:223101874
BRANCH=none
TEST=make
Signed-off-by: Mars Chen <chenxiangrui@huaqin.corp-partner.google.com>
Change-Id: Ie83df3c753d0863841430fe62805250ef8efeae9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Currently the BayHub eMMC enable pin is using the default
configuration from the baseboard, which leads to RTD3 not being able
to control the GPIO when exiting and entering suspend. To fix this,
program the GPIO in the ramstage GPIO table.
BUG=b:222436260
TEST=USE="project_primus" emerge-brya coreboot chromeos-bootimage
scope enable pin while performing suspend stress and enable pin
works as expected.
test suspend stress 1000 cycles passed on primus.
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I1b6f164cc326bd368addb1e143ad2cbd449bb08d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Pull GPP_D16 to low when suspending, otherwise it will remain active
and use power.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I2cbe7caf66e8d8c27414aca3b74416c2b8115ea1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
DDR4 SPD data needs to be 512 byte to comply with the spec.
Though there is no vital timing data used beyond 256 byte there are some
part information which will be used to show the part info in the
coreboot log. If the buffer is too small this log shows garbage.
This patch increases the SPD buffer size from 256 byte to 512 to avoid
side effects.
Change-Id: I5b88df7818cfd62b3579d69f9f5bb14880f49c8c
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
1. Update override devicetree based on schematics.
2. ALC5682I-VS is for audio codec.
BUG=b:218786363, b:214025396, b:212183045
TEST=emerge-brask coreboot
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I08a1c2f784175b208ccdc562668041f432618dfc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
The verstage.c file contains PSP verstage specific code. We don't need
it when using x86 verstage.
BUG=b:193050286
TEST=Build and boot guybrush with x86 verstage
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6dc928cdce0c922bb18f4479b993c89dff106070
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62740
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This sets EPP value to be 45% for all Brya variants.
Historically, EPP Ratio has always been 50% (128) on Chrome platforms.
But on Intel Alderlake EPP ratio of 45% is recommended for optimal
power and performance on Chrome platforms.
BUG=b:219785001
BRANCH=firmware-brya-14505.B
TEST=
Use 'iotools rdmsr [cpu id] 0x774' command and check field 32:24 = 0x73.
Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: I973cfec72a0be24c56c4cd3283d2fe6e18400d02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Update PL1, PL2, and temperature sensor values from thermal team,
as well as, we remove unused temperature sensors according to
baseboard/devicetree.cb and mainboard schematic. After we check
DTT setting, the thermal and performance test pass.
BRANCH=dedede
BUG=b:204229229
TEST=on beadrix, run following commands:
localhost /tmp # cat /sys/class/thermal/thermal_zone*/type
x86_pkg_temp
INT3400 Thermal
TSR0
TSR1
TCPU
localhost /tmp # cat /sys/class/thermal/thermal_zone*/temp
45000
20000
32800
32800
39000
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: Ibc59c4aa431f600158e744f5bbdc6d59a07a1ef3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62729
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The one USB2 port on the XHCI2 controller should have the port ID 2.0,
since it's the first USB2 port on that XHCI controller.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4a370132960939bccec4eb69a6590d0880b04137
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62713
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
GFX HDA is the audio controller that provides audio output via the
external display connection, ACP is the audio coporcessor for the on-
board audio codec and XHCI2 is the third XHCI controller that provides
one USB 2.0 port. All those devices are used, so enable them in the
board's devicetree.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I186797a832470eb17752e06aa2fcc0b5c9db0398
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62571
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Select GL9750 driver and add power sequence according to datasheet:
GL9750S-OIY04 rev1.22.
BUG=b:223304292
TEST=check GL9750 can get enumerated by kernel 5.15.
01:00.0 SD Host controller: Genesys Logic, Inc Device 9750 (rev 01)
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ib6d461a56f6aeba30994daafe8993c36df4b309d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
|
|
Enable pen garage. Pen detect is active low. And wake system when
eject.
BUG=b:223476974
TEST=evtest work as expected.
Input driver version is 1.0.1
Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100
Input device name: "PRP0001:00"
Supported events:
Event type 0 (EV_SYN)
Event type 5 (EV_SW)
Event code 15 (SW_PEN_INSERTED) state 0
Properties:
Testing ... (interrupt to exit)
Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1
Event: -------------- SYN_REPORT ------------
Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I2f676301c3372a4760853ce9c10b75f94e22bbcd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used
for WLAN. Mappping derived from Skyrim schematic.
BUG=b:214412172
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I16e35b443f741d366589fefb7fd21863369d1ec2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
GPIO 32 was not allocated correctly, updating to reflect the native
function use of the pin
BUG=b:214412172
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Idadd2a802b3244eba8ee83f80d8f10baebe4ca40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62717
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Initialize trackpad on Qualcomm reference boards
BUG=b:182963902,b:223826899
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: I93e866d92cf37887a98de88b4b2d768562515670
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62226
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In order to copy the PSP verstage logs into x86 cbmem, we need to enable
DEBUG_SMI. This will include the CBMEM console code in SMM. I only
enable DEBUG_SMI when UART is disabled because SMM doesn't currently
save/restore the UART registers. This will result in clearing the
interrupt enable bits and makes it so you can no longer use the TTY.
BUG=b:221231786, b:217968734
BRANCH=guybrush
TEST=Build serial and non serial firmware and verify DEBUG_SMI is set
correctly.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I85a7933e8eb49ff920d00e43a494aaeab555ef3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Sets GPIO 42 to high to turn off WWAN DPR
BUG=b:216735313
BRANCH=guybrush
TEST=emerge-guybrush coreboot
make sure GPIO42 is high
Change-Id: Id0fcf27f086f98b2d42b47c8a871252b52d204ba
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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GPIO_18 is used for LCD_PRIVACY_SCREEN feature starting board phase 2.
But it is programmed incorrectly in the concerned ACPI device. Pass the
correct GPIO.
BUG=b:204401306
TEST=Build and boot to OS in Nipperkin. Ensure that the ACPI object
contains the right GPIO. Ensure that the screen visibility gets updated
by pressing the privacy screen button.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I99d40b49f4e97063f1ec2e15ac3da21f700a93eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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The Brask DDR4 setting are interleave, due to Moli PCB layer limited and the routing need to smooth, we will use non-interleave for Moli DDR4.
BUG=b:219831754
Signed-off-by: zoey wu <zoey_wu@wistron.corp-partner.google.com>
Change-Id: Iab153f16a3b729e7fa9daaa3dbfbccc70e6d789d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Decrease PSysMax from 13.52 A to 11 A for Moli variant according to its power circuitry, implying Psys_Pmax = 11A * 19.5V = 214.5W
BUG=b:215258941
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I61f4813f3527123a590d80b4a6e49d76ebb71c99
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Don't return 0x00 when running MWAK as it is not needed.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ic62eab8ae5319aff37c61fc29d701d9a36ada919
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Remove the dependency on Arg0 so PTS always runs.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I96c44397d62848231039330a32de781f75bb56bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
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Some non-SoC code might want to know whether or not the CNVi DDR RFIM
feature is enabled. Also note that future SoCs may also support this
feature. To make the CnviDdrRfim property generic, move it from
soc/intel/alderlake to drivers/wifi/generic instead.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Idf9fba0a79d1f431269be5851b026ed966600160
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
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Based on testing results from the thermal team, they have decided
to update PL1, PL2 and PL4 for U28 SKUs.
BUG=b:221338290
TEST=Run with U28 and ensure the PL1/PL2/PL4 settings are correct
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ib82e2dbacd6cbc39390eb28f27ca9db48d6c215c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Fix stylus UI behavior bug.
1) it appears the kernel's gpio_key driver is not expecting
an IRQ descriptor for the `gpio` property, therefore change
to an active-low input.
2) The wakeup event was configured backwards.
Change list
- Configure GPP_A7 as "ACPI_GPIO_INPUT_ACTIVE_LOW".
- Change wakeup_event_action from ASSERTED to DEASSERTED.
BUG=b:220992812
TEST=emerge-brya coreboot chromeos-bootimage and verify pass
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I6f5e2992584d759eb1a559684d1cda08c7cbe3f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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BUG=b:214415048
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ia6bb3f717b3d30fe5f166dfc958024e931a070c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Config VR_DOMAIN_GT's slew rate to 1/8 as well.
BUG=b:204009588
TEST=build and verified by Power team.
Change-Id: I766b828ad83710913323cf1485e09c1e0fd5e4c2
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Disable unused TCSS Port1.
BUG=b:223082190
TEST=Build
Change-Id: I63f4b7d89a1e37a00c58201ecc88bb336d0932c9
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Enable Acoustic noise mitigation and set slew rate to 1/8
BUG=b:223082189
TEST=build and verified by power team
Change-Id: I256cc57fb54e5d62e22470a01e7efef359d57083
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Nissa boards are curretly using chromeos.fmd file of brya. The SPI flash
layout for brya is of 32MB size, and nissa is expected to have 16MB SPI
NOR flash. The current composition of AP firmware exceeds 16MB. To get
an estimate of the unutilized region in the current flash layout for
nissa, added RW_UNUSED regions. The idea is to reduce the AP firmware
size to under 16MB and to remove the RW_UNUSED regions from the final
fmd file.
Below table gives the size reduction from brya fmd to nissa fmd:
+----------------+-------------------+---------------+
| Region | Earlier size (KB) | New size (KB) |
+================+===================+===============+
| SI_ME | 5116 | 3772 |
+----------------+-------------------+---------------+
| RW_SECTION_A/B | 8192 | 4344 |
+----------------+-------------------+---------------+
| VBLOCK_A/B | 64 | 8 |
+----------------+-------------------+---------------+
| ME_RW_A/B* | 3008 | 1434 |
+----------------+-------------------+---------------+
| RW_LEGACY | 2048 | 1024 |
+----------------+-------------------+---------------+
| RW_ELOG | 16 | 4 |
+----------------+-------------------+---------------+
| SHARED_DATA | 8 | 4 |
+----------------+-------------------+---------------+
| VBLOCK_DEV | 8 | 0 |
+----------------+-------------------+---------------+
| RW_SPD_CACHE | 4 | 0 |
+----------------+-------------------+---------------+
| RW_NVRAM | 24 | 8 |
+----------------+-------------------+---------------+
| WP_RO | 8192 | 4096 |
+----------------+-------------------+---------------+
| GBB | 448 | 12 |
+----------------+-------------------+---------------+
*Based on LZMA compression on ME_RW_A/B regions. With LZMA compression,
this region can be 1434K. Without this, ~665K will be more in each of
these regions.
Patch: https://review.coreboot.org/c/coreboot/+/62358/
BUG=b:202783191
BRANCH=None
TEST=Build and boot Nivviks.
Cq-Depend: chrome-internal:4584911
Change-Id: I24b1c19cb71a54fc916a12668f72193f9689e755
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Change-Id: Ib27149c527015bd54f839994e047f815e8922dc4
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I0324747f936be27ee39e586124005530d5c424b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Discovered this chassis identification number on Dell Precision
T1650 which is much OptiPlex 9010 alike. Precision T1650 is a Mid
Tower (MT) chassis.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I2266fe39606b947a3d30a9462377fd56c39c2fa7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I3487b0ab94e565862ed727e9a91bd1efb364d43d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Guard Max Charge EC write in Kconfig so it's only used on
platforms that support it.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I7be39cd9543c8253d53070950edc6908a21e864a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This patch aims to make timestamps more consistent in naming,
to follow one pattern. Until now there were many naming patterns:
- TS_START_*/TS_END_*
- TS_BEFORE_*/TS_AFTER_*
- TS_*_START/TS_*_END
This change also aims to indicate, that these timestamps can be used
to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Tested using MrChromeBox's `uefipayload_202107` branch:
* Windows 10
* Ubuntu 20.04
* MX Linux 19.4
* Manjaro 21
No known issues.
https://starlabs.systems/pages/labtop-mk-iv-specification
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Idbaa907dc38dc521961806132f21b7a90324ec9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58428
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set the GPIO configuration of moli
BUG=b:220821454
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I7ec41cb843419c32337b66f3877eda5d730cea35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
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When using CNVi WLAN on ADL-N, the internal USB2 port 10 is used for
bluetooth. So update the nivviks overridetree to enable port 10 instead
of port 8, which is the external port used for bluetooth with PCIe WLAN.
BUG=b:222595137
TEST=Bluetooth works on nivviks
Change-Id: Ica2067023125c04fc753eabc944ae29ff59dc864
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
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Currently the BayHub eMMC controller is only going into its reset
state when the RTD3 sequence is initiated. This causes it to
still consume too much power in suspend states. This CL adds the
power enable GPIO into the RTD3 sequence as well, which will turn
off the eMMC controller (a true D3cold state) during the RTD3
sequence.
BUG=b:222436260
TEST=USE="project_primus" emerge-brya coreboot chromeos-bootimage
test suspend stress 100 cycles passed on primus.
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I2fec6a30707fb1a258cdcc73b0ce38252b6f77c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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cr50 firmware revisions starting at 0.5.5 and later are able to extend
their IRQ pulses to be a minimum of 100us long. This change will enable
cr50 long interrupt pulses when it detects the feature is supported by
the detected firmware version. If the capability was detected, then
GPIO PM will be enabled for the device, otherwise it will be disabled.
BUG=b:202246591
TEST=boot brya0, check console logs for the correct message, and
verify the GPIO PM registers.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iaf333dc0f177e17cd03b36ec7e487fc33bde2b93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61722
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Mainboards accessing the cr50 over an I2C bus may want to reuse some of
the same firmware version and BOARD_CFG logic, therefore refactor this
logic out into a bus-agnostic file, drivers/tpm/cr50.c. This file uses
the new tis_vendor_read/write() functions in order to access the cr50
regardless of the bus which is physically used. In order to leave SPI
devices intact, the tis_vendor_* functions are added to the SPI driver.
BUG=b:202246591
TEST=boot to OS on google/dratini, see the same FW version and board_cfg
console prints as before the change.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie68618cbe026a2b9221f93d0fe41d0b2054e8091
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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Add GL9750 SD card reader support.
BUG=b:222402409
TEST=Build FW and check device function normally.
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Ied36719914de214ae7d810f3d03a508e95fbf66a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Disable unused TCSS PCIe port1
BUG=b:217238553
TEST=FW_NAME=redrix emerge-brya coreboot chromeos-bootimage
Change-Id: I2bdfdb23d010a1e24c986ab52b5cef6eedcb674e
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Vell has a keyboard MCU connected to USB2 port 7. This patch enables
the port.
localhost# usb_updater2 -f
Found device.
found interface 0 endpoint 1, chunk_len 64
READY
-------
start
target running protocol version 6 (type 1)
maximum PDU size: 4096
Flash protection status: 0000
version: prism_v2.0.12137+c4ae1432f5
key_version: 1
min_rollback: 0
offset: writable at 0xc000
Current versions:
Writable prism_v2.0.12137+c4ae1432f5
BUG=b:203664745,b:211496726
TEST=Run 'usb_updater2 -f' on Vell.
Change-Id: Iad2140dbdf5e34332388f3f43b3ede3d22e73087
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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ChromeOS considers the WWAN devices to be untrusted, therefore enable
the new DmaProperty in the WWAN's _DSD to indicate to the OS that these
devices should have IOMMU restrictions applied to them.
BUG=b:215424986
BRANCH=brya
TEST=dump SSDT
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I9c9e73b7ea0575ab87cc980fb4786338047155de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Commit ebf14826
[mb/google/hatch/var/jinlon: Switch to using device pointers]
broke jinlon boards without an electronic privacy screen (EPS) by
disabling the parent device (iGPU) instead of the EPS when determined to
be not present via SKU ID.
Commit c5a3a4a6
[mb/google/hatch (baseboard): add ACPI backlight support]
broke EPS detection by adding a duplicate iGPU device to the devicetree,
resulting in the EPS entry being skipped.
Fix both of these issues by assigning the device alias to the EPS child
device, not the parent (iGPU). Rename the alias for clarity, and combine
the duplicate device definitions for the iGPU.
Test: build/boot google/jinlon SKU w/o EPS, observe GPU functional
in both firmware boot screens and Linux OS.
Change-Id: I0615ce361497abe6872085b0dec83292607e53dd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62593
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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