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Adapted from WIP (and now abandoned) patches CB:25334, 26308, 26309.
Update the nhlt_soc_add_*() methods for max98373, max98927, and rt5514
codecs to program the render and feedback slot numbers as appropriate.
TEST=boot Windows on google/eve, atlas, nocturne, and rammus. Verify
audio functional with both Google project campfire drivers as well as
coolstar's AVS audio drivers.
Change-Id: Ib8c6e24ba539e205bd5bbd856ecff43b2c016c2e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
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Remove the PSE TSN GbE device #0 as it's unused on the board and not
visible during the PCI enumeration.
Change-Id: I4a7d0e437c4f4a12d3a07564cddeafb7c697c6d3
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70700
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Contrary to mc_ehl2, which this variant is based on, this board
doesn't contain the TI XIO2001 PCIe-to-PCI bridge, which makes the
attempts to modify the bridge's registers unnecessary.
Change-Id: I6597ceb78e4c790c08a0dfa9535dece33a8f95b8
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70854
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Switch from using ACPI "probed" flag to "detect" flag for all i2c
touchscreens and digitizers. This removes non-present devices from the
SSDT and relieves the OS of the burden of probing.
Test: build/boot Windows/Linux on various octopus variants, verify
touchscreens/digitizers functional, dump ACPI tables and verify only i2c
devices actually present on the board have entries in the SSDT.
Change-Id: I67c5bbae42e96ae21d37309e382b635321e6ef01
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63214
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The GPIOs themselves are configured as level triggered, and the drivers
(both Linux and Windows) work better with LEVEL vs EDGE triggering.
TEST=tested with rest of patch train
Change-Id: I13bc6920a0dfaf769091b1764a7584902d1f85d6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63213
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For octopus variants with a touchscreen/digitizer, drive the enable and
reset GPIOs high in romstage, then disable the reset GPIOs in ramstage.
Where available, only set the GPIOs for SKUs which have a touchscreen.
This will allow coreboot to detect the presence of i2c touchscreens
during ACPI SSDT generation (implemented in a subsequent commit).
TEST=tested with rest of patch train
Change-Id: Ia725b4054069c0a4f60afd7e0bca6e2fd5fdcbba
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63212
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add method variant_romstage_gpio_table() with empty weak implementation
to allow variants to override as needed for touchscreen power
sequencing (to be implemented in a subsequent commit). Call method
in romstage to program any GPIOs the variant may need to set.
TEST=tested with rest of patch train
Change-Id: I4a8e11945ae64b000051989089e0ebae22896c6b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70905
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch enables building ChromeOS for mtlrvp.
Patch includes,
1. Add cros_gpios for mtlrvp
2. Add chrome OS configuration in Kconfig
3. Add Chromeos.c
BUG=b:224325352
TEST=Able to build with the patch and boot the mtlrvp platform with the
subsequent patches in the train (CB: 69886)
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: Ia428941bd8269714c3edca6c7b0c2a3fbf08bd75
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70724
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Power resource for Bluetooth device is not configured correctly in the
device tree. Fix Bluetooth devicetree configuration.
BUG=b:262785310
TEST=Build Skyrim BIOS image and boot to OS. Ensure that the DUT is able
to connect to a Bluetooth headset.
Change-Id: Id980424349537be35860dec04cc823d419cefe2f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71068
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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add dptc support for different power parameter on tablet/clamshell
mode.
BUG=b:257187831
BRANCH=none
TEST=validate the parameter change for each mode by AGT.
Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I96e04d113d18b42f3457056a5e4fa311ceccffb3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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1.Config setting for touchpad I2C
BUG=b:261159229
TEST=On frostflow, touchpad i2c spec from EE measure
Frequencies:
1.I2C0 (Touchpad): 385.7kHz
Change-Id: I4ca72ee7fabd4b641eb17451ed8d942c5df52dde
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I07be0aa2144b7718e28f1f675978b4b4b92752ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69492
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds files required for ramstage and SMM.
1. Add file required for ramstage (mainboard.c)
2. Add smihandler.c for SMM
BUG=b:224325352
TEST=Able to build with the patch and boot the mtlrvp platform with the
subsequent patches in the train
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I377c4ff954a900c7b5193d7cab5554c6c02573ee
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70723
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch will initialize EC for mtlrvp which includes,
1. Add configuration (& choice) for CHROME_EC and INTEL_EC (WINDOWS_EC)
2. Add respective ACPI configuration
3. Add ec.c required for ramstage
4. Program EC ranges as part of devicetree.cb
5. Enable VBOOT in Kconfig
BUG=b:224325352
TEST=Able to build with the patch and boot the mtlrvp platform with
CHROME_EC using subsequent patches in the train
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: I662d7f79050d35e152d97dc5c2118a4af56223bc
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66101
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace `XOr (a, b, c)` with `c = a ^ b`, respectively `c ^= b` where
possible.
Change-Id: Ic5f67684bbd4ea115c4dae8a4417d88bea0d6b77
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70843
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Add NHLT endpoints for octopus boards using CS42L42 codec.
Reuse method to add da7219 endpoint as the routing is identical.
TEST=boot Windows, verify audio working with coolstar's audio drivers.
Change-Id: Id68997073752f5d90b6fe21f666a6140e22d65eb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Remove flag in VBTs for 'Use fixed resolution at boot' to allow FSP/GOP
display init to use native panel resolution instead.
TEST=build/boot multiple google/octopus variants with edk2 payload,
verify boot logo not distorted/stretched.
Change-Id: Ia31ff28379282619dfa22a955bee1a768bb54bb8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Boot menus are too small at native 4K res on some panels, so
set fixed display resolution to 1920x1090p
TEST=build/boot KOHAKU with 4K display, verify boot menu text legible.
Change-Id: I82563c83de7ab302151f60d86b8a6824330d03ea
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Adjust I2C speed for codec, TPM, touchpad, touchscreen.
BUG=b:260565911
TEST=Built and verified adjusted I2C speed
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Idcec6e401992d30dff01940c50473cba48cffc19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
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Based upon hardware differences from mc_ehl2, disable RP7
and enable RP3 and RP5.
Change-Id: Iecaa3098c3e4c9ce15254bb8bd1fe6da86d6e706
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70689
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a new mc_ehl variant, which is based on mc_ehl2 implementation.
This patch uses a copy of mc_ehl2 with changes only in naming
as a starting point for the new mc_ehl3 variant.
Follow-up patches will introduce the functional changes against
mc_ehl3.
Change-Id: Ie8c18b4f16d88b175ce576c2ef4c2e6ee0b4c306
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Enable wifi sar function for yaviks.
Use the fw_config to separate SAR setting for different wifi card.
BUG=259199095
TEST=build, enabled iwlwifi debug, and check dmesg
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I3ced65368ee66e084e58d66cff8f75147f665d71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Update SX9324 RegProxCtrl0 register settings based on tunning value
from P-sensor vendor.
BUG=b:242662878
TEST=i2cdump -y -f 13 0x28 on Pujjo
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: If471a6fee5a3daeac1958709415b2d5e1329b81b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Tested using `edk2` from
`github.com/starlabsltd/edk2/tree/uefipayload_202209`:
* Windows 10
* Ubuntu 20.04
* MX Linux 19.4
* Manjaro 21
No known issues.
https://starlabs.systems/pages/starbook-specification
Signed-off-by: Ben-StarLabs <ben@starlabs.systems>
Change-Id: Idc0c265a88b19cf9e89cc8ab3e8db9abd8cf8409
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65785
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
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This will help to integrate RO SPL table in RO partitions such that it
is used before PSP verstage is loaded. After PSP verstage, SPL table in
RW partition gets used.
BUG=b:243470283
TEST=Build Skyrim BIOS image and boot to OS.
Change-Id: Ic2061f66381d7e9a8018e6f28aa0bc2ca6010f6f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70777
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To support an RPL SKU on lisbon, lisbon must use the FSP for RPL.
Select SOC_INTEL_RAPTORLAKE for lisbon so that it will use the RPL
FSP headers for lisbon.
BUG=b:246657849
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=lisbon emerge-brask intel-rplfsp
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage
flash and boot lisbon to kernel.
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: Ie60c357ef0a2af2fec90df4a54e56f51ceb927d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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BUG=b:260565911
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Id5a73126737a3abbe6f0ef37276ce20f687b47fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70236
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
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Disable unused PCIE8 for fix system can not enter S0ix completely.
BUG=b:261915226
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I06f8bd06e1fe92c03bd5625a41469830ce37a11c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70660
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Rename the MIPI PWM control GPIO to be consistent with the schematic.
BUG=b:244208960
TEST=test firmware display pass for eDP and MIPI panels on MT8188 EVB
Change-Id: I6a3368d438cb50b257992260d1388f0b7e0f5ace
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70822
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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There are two ways to control backlight in geralt:
1. MIPI/eDP panel => control backlight via the GPIOs.
(`backlight chip enable` and `PWM dimming control`)
2. eDP OLED panel => enable backlight via `backlight chip enable` and
control dimming over AUX.
For MIPI/eDP panels(#1), both "backlight enable" and "PWM control" GPIOs
will be passed from coreboot. For eDP OLED panel(#2), only the
"backlight enable" GPIO will be passed. If depthcharge successfully gets
the GPIOs, it will use them to control backlight.
BUG=b:244208960
TEST=test firmware display pass for eDP and MIPI panels on MT8188 EVB
Change-Id: I866fa219722241008e2b0d566b29edf2f6d9321f
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70744
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Correct touchscreen setting to make touchscreen function workable.
BUG=b:260565911
BRANCH=firmware-brya-14505.B
TEST=Built and verified touchscreen function
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ia98deae65ef0e2f501457331144b044e07431a3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This patch connects USB3_PCH_*_WWAN_* to USB32_2 as per Proto 1
schematics dated 12/14/2022.
TEST=Able to build Google/Rex.
Change-Id: Ie04c79ff5c231527e3d5f63a5cc553ec39c46914
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This patch updates the GPIO PIN name as per Proto 1 schematics dated
12/14/2022.
TEST=Not code change, just updated the comment section.
Change-Id: Ic076ab35689fd2afb7c18eff065a90b9464a6b1d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Update RAM ID table because H9JCNNNFA5MLYR-N6E is using spd-4.hex
instead of spd-9.hex.
Reserve RAM ID 3 for it, so the RAM ID table remains the same.
BUG=b:261530632
BRANCH=None
TEST=FW_NAME=frostflow emerge-skyrim coreboot chromeos-bootimage
Then boot devices successfully
Change-Id: I1b683168310f74a07d246af8618b977cce32287a
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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pujjo support FM101 WWAN, add delay of FCPO# to meet warm reset toff
minimum 500ms requirement.
BUG=b:260380268
TEST=Build and boot on pujjo
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I63e599e76bd8a15ca44717823411576fa4df1c26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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BUG=none
TEST=Build and boot to the OS on google/rex.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I2c5bac880e7dbc2ec14376c5cee3c13363bab377
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70444
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fast VMode nmakes the SoC throttle when the current exceeds the I_TRIP
threshold.
BUG=b:252966799
BRANCH=firmware-brya-14505.B
TEST=Verify that the feature is enabled by reading from fsp log
Change-Id: I175f7f39d6115d1f082575393c45734c7b02e346
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Add PCIe RTD3 support for Skyrim
BUG=b:245550573
TEST=Boot/Reboot cycles and Suspend_stress_test 10 times
Signed-off-by: JasonNien <finaljason@gmail.com>
Change-Id: I7f01827613eea2f254bc42c7f5aebeeb969b163a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70740
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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With 1ms delay, reset is de-asserted too soon, before power is fully
up, causing a glitch to the reset signal. The issue is resolved with
4ms delay.
TEST=tested on dratini device and observed the issue is resolved.
BUG=b:260253945
Change-Id: I5c3edbc6ac90d5042c2d3c5b01573d4bb1ea676d
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70666
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a hook to allow a variant finalize to be called at the end of
ramstage.
BUG=b:245954151
TEST=Builds successfully
Change-Id: I00c091051e3499ca94b286d7fbe0a7a8bd38e635
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70319
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace `Store (a, b)` with `b = a`.
Change-Id: I349d1e7d3027097c5db4da96e2376831fff61b04
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Replace `Store (a, b)` with `b = a`.
Change-Id: Ib75ccc10c8086086f5db4ced1163b74c9835364b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Replace `Store (a, b)` with `b = a`.
Change-Id: I950d776a712a104f2caed614886ce2527028ead7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Replace `Store (a, b)` with `b = a`.
Change-Id: Ib2ba6b5c14f6699dc6c0734724a6784e3400a467
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Replace `Store (a, b)` with `b = a`.
Change-Id: If6c37cc2ce51780e0bae007d884d8f77b20847fb
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Replace `Store (a, b)` with `b = a`.
Change-Id: I04f61df6b651058060b88e5f5679a0dd5270e66d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Replace `Store (a, b)` with `b = a`.
Change-Id: Ic0ae4903546446322c2c47cab00de4c3af6c9d98
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Enable GPP clk req disabling on morgana after reviewing against morgana
ppr #57396, rev 1.52
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Id2502137486df7a8b0ac6a4b3e061b25b23e2e51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70465
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Now that gpio.h will only include the defines in the IASL case, gpio.h
can be included instead of soc/gpio.h in the files that will be directly
or indirectly included in the DSDT.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifc8d8fe4e4148e5b5628f32778368d1fc7f44e5b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70510
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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On nissa, the ISH is running closed source firmware, so the ChromeOS
security requirements specify it must be behind an IOMMU. Add
DmaProperty to the ISH _DSD on nivviks and yaviks.
BUG=b:259716145
TEST=Kernel marks ISH (PCI device 12.0) as untrusted, and changes the
IOMMU group type to "DMA". Also, device still goes to S0i3.
Before:
$ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted
0
$ ls /sys/kernel/iommu_groups/5/devices
0000:00:12.0
0000:00:12.7
$ cat /sys/kernel/iommu_groups/5/type
DMA-FQ
After:
$ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted
1
$ ls /sys/kernel/iommu_groups/5/devices
0000:00:12.0
0000:00:12.7
$ cat /sys/kernel/iommu_groups/5/type
DMA
Change-Id: Iaddb24580bda77df0c70ff58eb098213f8b509ad
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Update pci int defs per preview of next ppr after rev 1.52, #57396
Update birman and mayan mainboards to remove deleted PIRQs.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I10e13784761f0b9245f0ca10e3cd07d396ec4224
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70379
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add wifi sar for lisbon.
BUG=b:260938760
BRANCH=firmware-brya-14505.B
TEST=emerge-brask coreboot-private-files-baseboard-brya coreboot
chromeos-bootimage
Change-Id: Ia347c4cf56bec971700bb53a5804e36e0bad82fb
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70483
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add wifi sar for gladios.
BUG=b:260950906
BRANCH=firmware-brya-14505.B
TEST=emerge-brask coreboot-private-files-baseboard-brya coreboot
chromeos-bootimage
Change-Id: I4cd015f17c4ddd28414f51a873ae4afc37863708
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70605
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Tranferring a bit to DC through Skuid to update the regulator
node in order to support pro and non-pro
BUG=b:248187555
TEST=Validate boards are detected correctly on PRO and NON_PRO SKUs
Signed-off-by: Sudheer Kumar Amrabadi <quic_samrabad@quicinc.com>
Change-Id: Iec392c03c2e2c79d20b1fcb79236ca9e048bfd07
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68385
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Correct touchpad setting to make touchpad function workable.
BUG=b:261393412
BRANCH=firmware-brya-14505.B
TEST=Built and verified touchpad function
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I3c816ce4293ae362f0e5c18171f296d42b4307c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70440
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Found using 'Wmissing-include-dirs' command option.
Change-Id: I178c849d07e61d7a237629f3be1b52d3b4abb513
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Replace `LLessEqual (a, b)` with `a <= b`.
Change-Id: I4af47fdf5bab57c6bbfe417f55de35b074753120
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70621
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace `LEqual (a, b)` with `a == b`.
Change-Id: Ic3a49828551b6da45999ff55539d5e3449d475e3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70598
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace `LEqual (a, b)` with `a == b`.
Change-Id: Ief985f8b7b14e8879a068140cb1f9b28c7336e94
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70597
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Replace `LEqual (a, b)` with `a == b`.
Change-Id: I9441988c0bf6d07641595a3b501c2af5230ba131
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70596
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace `LEqual (a, b)` with `a == b`.
Change-Id: I50c1831c909163b8eb9b91d6ceb267bd8cc41e11
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70595
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Replace `LEqual (a, b)` with `a == b`.
Change-Id: I74a6c949fa08a6eb712c053137369242e20e78fe
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70594
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Replace `LEqual (a, b)` with `a == b`.
Change-Id: I710d9c8c767a688f423d5a7e3e2708eb6aef11fc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70587
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Replace `LEqual (a, b)` with `a == b`.
Change-Id: I4fa3942216f1638abeafa0c562f4d6a2a499254b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70586
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace `LEqual (a, b)` with `a == b`.
Change-Id: I99f34d4c03b0687b8e0c2e4aee85f196679bcf52
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Change-Id: Ie26b623a3848b929b83aad5931b1ecd90b342d2c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
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Both eDP and MIPI interfaces are supported in geralt project, so we can
initialize the different displays according to the panel ID.
This patch also generalizes the display initialization. So
`configure_edp_panel_backlight` and `power_on_edp_panel` can be removed.
BUG=b:244208960
TEST=test firmware display pass for MIPI panel on MT8188 EVB.
Change-Id: I7ae9318f56c70446516e197635acaffb8197ab53
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70406
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Both eDP and MIPI interfaces are supported in geralt project. Therefore,
we put the eDP panel data in panel_geralt.c to have the consistent
interface `get_active_panel` function.
BUG=b:244208960
TEST=emerge-geralt coreboot
Change-Id: Ib35b3cab31bae4109b9715242201425580339536
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70405
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There are eDP and MIPI panels supported in geralt. We put the panels'
specified functions - `power_on()` and `configure_panel_backlight()` in
panel_geralt.c. Also provide the common interface `get_active_panel()`
in panel.c to generalize the display initialization. Since each board
may support a different set of MIPI panels, we put the MIPI data in a
separate file panel_geralt.c.
BUG=b:244208960
TEST=emerge-geralt coreboot
Change-Id: Ie928759e020a916f29f0364201a3cf202dc512c3
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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The EN_PP3300_SD gpio (GPP_H13) was configured as a no-connect, but
should be configured as an output.
This change configures GPP_H13 on brya0 and skolas to be an output.
BUG=b:261901759
BRANCH=firmware-brya-14505.B
TEST="emerge-brya coreboot chromeos-bootimage" and verify skolas boots.
Change-Id: Ia3f01e877a5fea3af9a6e746523ed395f3af3b8a
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70512
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The baudrate of the SOC console is always 57600 and on tiogapass the
0x2f8 COM port is also used by the SOL console.
Change-Id: Ia7bf9fbe10ec66f49c2c7b41938a1a33967c131a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70500
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
According to the schematic, we use the same backlight enabled GPIO
naming in eDP and MIPI panels.
BUG=b:244208960
TEST=emerge-geralt coreboot
Change-Id: If8d3ca7098c6b22af41861bba74b764d71d27e1b
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70403
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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According to ID table(go/geralt-id), we add panel_id() to read the
panel id from auxadc channel 5.
BUG=b:244208960
TEST=emerge-geralt coreboot
Change-Id: I2c0f4ee5a642c41dda9594fbaf2c63f2b2ebac6e
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70402
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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According to ID table(go/geralt-id), geralt only uses channel 4 for SKU
ID.
BUG=b:244208960
TEST=emerge-geralt coreboot
Change-Id: I0f7303b8809e6000e3e16228b00b525a77feee87
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70401
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add wifi sar table for pujjo intel wifi config.
Use fw_config to separate different project settings.
BUG=b:256042825,b:256042769
Test=emerge-nissa coreboot
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Ibdbe1c0a477e47af9cbbc9bf73ac583d06ad7a0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70480
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
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Disable unused I2C2/I2C4 bus for marasov.
BUG=b:260565911
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Id1c41bfdca9b752e3f027e6b071629d67aa06761
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70237
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
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Add new memory parts
- H58G56BK7BX068
- MT62F1G32D2DS-026 WT:B
- K3KL8L80CM-MGCT
BUG=b:261539879
TEST=run part_id_gen to generate SPD id
Change-Id: I74f35d1afad90c3b6a79679a8126904565695fbc
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70410
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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commit 52ccd293d7 ("mb/google/brya: Implement shutdown function for
dGPU") started unconditionally adding MPTS to the SSDT. On variants
with HAVE_WWAN_POWER_SEQUENCE selected, MPTS is already added to the
DSDT via wwan_power.asl. The duplicate definition results in a kernel
error:
ERR kernel: [ 0.109237] ACPI BIOS Error (bug): Failure creating named object [\_SB.MPTS], AE_ALREADY_EXISTS (20210730/dswload2-327)
ERR kernel: [ 0.109242] ACPI Error: AE_ALREADY_EXISTS, During name lookup/catalog (20210730/psobject-220)
Don't add MPTS to the SSDT if HAVE_WWAN_POWER_SEQUENCE is selected.
There are no variants which use both, so this should only result in
empty MPTS methods being removed.
BUG=b:260380268
TEST=On pujjo, the SSDT no longer contains an empty MPTS method, there's
no kernel error, and the WWAN power-off sequence is met.
Change-Id: I9f411aae81ea87aa9c8fc7754c3709e398771a32
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70146
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change override memory ID 3 to 1 to workaround the incorrect
memory straps in hardware.
We would use board_id 7 to identify the specific boards which need
to correct the memory ID.
BUG=b:259301885
BRANCH=Octopus
TEST=Verified on Phaser
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I2330b7e16a09f8cc76ed96e81a6165afa80a03a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70353
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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PP1800_GPU_X should dynamically move from GPP_E18 to GPP_F12
depending on board revision.
PP0950_GPU_X (PEX) should remain on GPP_E10 for all board
revisions.
BUG=b:242752623
TEST=dGPU is functional on both revisions of the board
Change-Id: I20994fcac4d7b98ee893d5eb98b096c037d31d6c
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70320
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change FSP board type to Type3.
BUG=b:260565911
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
check MRC log "Maximum requested frequency" is 4800
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I69365bc726b4faac4cedb94cc7b08baa06056c1d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70439
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable PCIe port 5 for WLAN device
BUG=b:261514079
BRANCH=firmware-brya-14505.B
TEST=Build and boot on marasov.
Ensure that the WLAN module is enumerated in the output of lspci.
localhost ~ # lspci
01:00.0 Network controller: MEDIATEK Corp. MT7921 802.11ax PCI Express Wireless Network Adapter
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I007501bb00e2b7b83de1292f3066874d07646cb7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70442
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Based on the SKU plan, add FW_CONFIG definition.
BUG=b:260473966
BRANCH=None
TEST=emerge-skyrim coreboot chromeos-bootimage
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I727f69e8fe340cfe624adb5a49bd080ba9544786
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70418
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch ensures to be able to drive SYS_SLP_S0IX_L `low` based
on the state of the system while `SLP_S0_L` signal is `low` (while
the system is in S0ix).
Implemented runtime ASL method (MS0X) being called by PEPD device
_DSM to configure `SLP_S0_GATE (GPP_H14)` PIN at S0ix entry/exit.
Scope (\_SB)
{
Method (MS0X, 1, Serialized)
{
If ((Arg0 == One))
{
\_SB.PCI0.CTXS (0x75)
}
Else
{
\_SB.PCI0.STXS (0x75)
}
}
BUG=b:256807255
TEST=Able to see SYS_SLP_S0IX_L goes low in S0ix.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie6b5e066f228ea5dc79ae14dd803fc283fd248ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70196
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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<device/mmio.h>` chain-include `<arch/mmio.h>:
https://doc.coreboot.org/contributing/coding_style.html#headers-and-includes
Also sort includes while on it.
Change-Id: Ie62e4295ce735a6ca74fbe2499b41aab2e76d506
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Replace the amdblocks/gpio.h and soc/gpio.h includes with the common
gpio.h which will include soc/gpio.h which will include amdblocks/gpio.h
in the AMD SoC case.
Since baseboard/ec.h and indirectly baseboard/gpio.h files will get
included in the DSDT, the soc/gpio.h includes in those aren't replaced
with a gpio.h include for now.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib982e338b5c6bc145ec1a8f6dd75175a42dfb426
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70436
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace the amdblocks/gpio.h and soc/gpio.h includes with the common
gpio.h which will include soc/gpio.h which will include amdblocks/gpio.h
in the AMD SoC case.
Since baseboard/ec.h and indirectly baseboard/gpio.h files will get
included in the DSDT, the soc/gpio.h includes in those aren't replaced
with a gpio.h include for now.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifa82c10d10e4438b0437b78ddd95b5e823805571
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70435
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I2e1978f20b085f609cbeb0907374383f2d11fbf0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70474
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This adds MTL-P board id definition. Change include,
1. Add board_id.c implementation
2. Add board_id.h implementation
3. Add board_id config in variants.h
4. Makefile changes
BUG=b:224325352
TEST=Able to build with the patch and boot the mtlrvp platform with the
subsequent patches in the train
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: I90b0543d5db208f696d2c2c2dc3d2581514a845b
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66102
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This patch adds the initial code for mtlrvp_p_ext_ec variant board
which includes
1. support for 2 mainboards (Chrome EC and Windows EC) by
adding overridetree.cb to corresponding directory
2. Move devicetree to baseboard/mtlrvp_p
3. Update mainboard name in Kconfig and Kconfig.name
4. Add config option to select corresponding overridetree.cb
Subsequent patches include patch train starting from (CB - 66102)
BUG=b:260654043
TEST=Able to build with the patch and boot the mtlrvp platform with the
subsequent patches
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I83948aa5e9fcaadee4745e313360773c48142f89
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Usha P <usha.p@intel.com>
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Found using 'Wmissing-include-dirs' command option.
Change-Id: Ie0e31fcdbeb219d3ecbe14a492d3e7824f6a51cc
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70397
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch enables V1p05 and Vnn external bypass VRs for Marasov.
BUG=b:260565911
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Id28305b02e86f5ac55382ac6d2bd5e0453aae9b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Adjust the bit fields in the FW_CONFIG for Proto Phase.
BUG=b:254404046
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=marasov emerge-brya coreboot
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ia71269918092655c11c2b37a26ec19123f759650
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
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This patch enables S0ix for Google/Rex platform.
BUG=b:256807255
TEST=Able to program FADT table Bit 21 (Low Power Idle S0)
Change-Id: I79546267d29622c65321f7dfa29d3aac2fa59438
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70430
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Drop the __weak qualifier as this function is not overridden.
BUG=b:260565911
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ica25b2bc4325ff9d27be672926b4e3b550c86e96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
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Found using 'Wmissing-include-dirs' command option.
Change-Id: Ie9ff43432215ebc89e6c1ea5f86b248e7fecd943
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70396
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace the amdblocks/gpio.h, amdblocks/gpio_defs.h and soc/gpio.h
includes with the common gpio.h which will include soc/gpio.h which will
include amdblocks/gpio.h which will include amdblocks/gpio_defs.h in the
AMD SoC case.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I37a33dd8821a00b7edfd1e5b593f71bea0e77630
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70434
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Replace the amdblocks/gpio.h, amdblocks/gpio_defs.h and soc/gpio.h
includes with the common gpio.h which will include soc/gpio.h which will
include amdblocks/gpio.h which will include amdblocks/gpio_defs.h in the
AMD SoC case.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I13bc33b91f6e6d52867da9043bb386f3befac5fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70433
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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option STORAGE_EMMC 0
option STORAGE_NVME 1
BUG=b:239513596
TEST=FW_NAME=gladios emerge-brask coreboot
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I27baa2ca8c2b334fb81aa87b22c3b7c028c38cd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Enable Dynamic DPTC support.
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I957511c44278a7cffb7cb5d7e099eb13232b6a1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
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