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2024-06-07mb/cwwk/adl: Select FSP_TYPE_IOTRonak Kanabar
Currently, the 3rdparty/fsp submodule contains only the IoT FSP for ADL-N. However, coreboot's Kconfig is incorrectly applying the IoT FSP for both Client and IoT configurations, despite the Client FSP requiring distinct headers. The CWWK CW-ADL-4L-V1.0 board relies on the FSP provided by the 3rdparty/fsp submodule, which means it has been using the IoT FSP by default. To ensure the board continues to use the correct FSP as we plan to introduce Client FSP headers into vendorcode, we are now explicitly select FSP_TYPE_IOT for the CWWK CW-ADL-4L-V1.0 board. Change-Id: Ie3844cb24740e4d95ee835a44e55b4d5cb6854e5 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82915 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Brandon Weeks <bweeks@google.com>
2024-06-07mb/aoostar/wtr_r1: Select FSP_TYPE_IOTRonak Kanabar
Currently, the 3rdparty/fsp submodule contains only the IoT FSP for ADL-N. However, coreboot's Kconfig is incorrectly applying the IoT FSP for both Client and IoT configurations, despite the Client FSP requiring distinct headers. The aoostar/wtr_r1 board relies on the FSP provided by the 3rdparty/fsp submodule, which means it has been using the IoT FSP by default. To ensure the board continues to use the correct FSP as we plan to introduce Client FSP headers into vendorcode, we are now explicitly select FSP_TYPE_IOT for the aoostar/wtr_r1 board. Change-Id: I68feeaaffd825013ae1012694047b067535e7341 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82914 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-06mb/siemens/chili: Remove superfluous device entries from dtFelix Singer
Remove the entries which have the same state as the ones from the chipset devicetree. Change-Id: I4981cd835ef28a673d480808dd486fed4d9b45e5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-06mb/google/brox/var/lotso: Add dq map settingJian Tong
Based on lotso EVT schematics add dq map settings. BUG=b:333494257 TEST=emerge-brox coreboot chromeos-bootimage and boot on Change-Id: I4f03e8a90522cbf2fe06f4160414202dcc4a2199 Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82600 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Dengwu Yu <yudengwu@huaqin.corp-partner.google.com>
2024-06-06mb/asrock: Add Z87E-ITX (Haswell)Nicholas Chin
This was done using Haswell autoport, with manual fixes to get the output to build against current main. I do not physically have this board; I was sent the output of autoport with some fixes on top of which I added additional changes. The VBT was copied from /sys/kernel/debug/dri/0/i915_vbt on version 2.70 of the vendor firmware. The flash chip is 8MiB in a socketed DIP8 package, making it easy to externally flash to recover from a brick. Working: - Haswell MRC.bin - S3 suspend and resume - Libgfxinit - HDMI - DVI-I (including passive DVI to VGA adapter) - DisplayPort - SATA ports - mSATA SSD - mPCIe WiFi slot - Rear USB ports - USB 3.0 header - Audio header - Ethernet - x16 PCIe slot - EHCI debug with the CH347 (top USB 2.0 port by the PS/2 connector) - edk2 (MrChromebox uefipayload_202309) Not Tested: - PS/2 keyboard/mouse - eSATA - USB 2.0 header Change-Id: I56c22d8f5505f9a4da25f8b4406b00978af1a586 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81022 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-06mb/intel/coffeelake_rvp: Prefer include <soc/gpio.h> via <gpio.h>Elyes Haouas
Change-Id: I98aa3f582963f76690f907b678ac322ed4cc99d1 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82846 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-06mb/starlabs/starbook: Prefer include <soc/gpio.h> via <gpio.h>Elyes Haouas
Change-Id: I972516443bc57e193aefd54516ca994087d92054 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2024-06-05mb/google/brox/var/lotso: Update gpio settingJian Tong
Based on lotso EVT schematics update gpio settings. BUG=b:333494257 TEST=emerge-brox coreboot chromeos-bootimage and boot on Change-Id: I13485cc7ccd8b15352f5e21ad9336aa2b3d35749 Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82573 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shelley Chen <shchen@google.com>
2024-06-05mb/ibm/sbp1: Update PCIe port slot number for NICNaresh Solanki
Based on schematic, update slot number for PCIe port used for NIC controller. Change-Id: I7a1ead8f7e4588db45303041e60dbfe27ee12ea7 Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-06-05Xeon-SP boards: Factor out OCP VPD `get_cxl_mode()` implAngel Pons
There's two copies of the `get_cxl_mode()` function to map the OCP VPD value to the values expected by platform code. As this is unnecessary, have a single copy of this function in the OCP VPD driver code. As the `get_cxl_mode()` function is Xeon-SP only, keep it in a separate file. This change simplifies things for boards using OCP VPD for CXL and has no impact for boards *not* using OCP VPD: - Boards not using OCP VPD can still define get_cxl_mode() in mainboard code as needed, just like they were able to do before. - Boards using OCP VPD but without CXL (`SOC_INTEL_HAS_CXL` is not enabled), this code won't get compiled in at all (see `Makefile.mk`). - Boards using OCP VPD and CXL will automatically make use of this `get_cxl_mode()` definition, which should be the same for all boards. It is possible that this may need to be expanded/adapted in the future, which is easy to handle in a follow-up commit when the need arises. TEST=Build and boot on intel/archercity CRB Change-Id: I935c4eb5b2392e2d0dc01b9f66d46c79b8141ea7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82224 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-06-05mb/google/trulo/var/orisa: Configure TPM IRQ for orisaAmanda Huang
Set GSC_SOC_INT_ODL to GPP_A17 instead of GPP_A13. BUG=b:333486830 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I065fdf2a66036c6df1e16dda3b2a684b5202cccc Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82717 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-04mb/starlabs/lite: Prefer include <soc/gpio.h> via <gpio.h>Elyes Haouas
Change-Id: Ib8f7ac7e586390a1d25cbe84d6d4c3ba31ff078f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2024-06-04mb/google/brya/var/xol: Enable FSP UPD LpDdrDqDqsReTrainingSeunghwan Kim
Set LpDdrDqDqsReTraining to 1 for xol. Value 0 will cause black screen issue. Reference: https://review.coreboot.org/c/coreboot/+/79527 > FSP default value for LpDdrDqDqsReTraining is 1. For boards > that didn't set LpDdrDqDqsReTraining to any value, 0 was being > assigned and it caused black screen issue. BUG=b:332980211 BRANCH=brya TEST=Built and verified there is no black screen issue during power on/off test for over 100 cycles. Change-Id: Ia346ce559b4509ea1a63abe28b12ad909f9b7b0d Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82778 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-06-04mb/google/brask/var/bujia: change ALC5650 to ALC5682I-VSShon Wang
Due to system spec change, change audio codec ALC5650 to ALC5682I-VS BUG=b:329787697 TEST= USE="-project_all project_bujia" emerge-brask coreboot Change-Id: I38e5c58b3ef3fbe709b98601975ae3821bb77213 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-03mb/razer/blade_stealth_kbl: Add H3Q variantReagan Bohan
The Razer Blade Stealth Kaby Lake has 2 variants. One is the H2U variant, as originally committed, with the SKU number RZ09-01962, also known as the 2016 model, and the H3Q model with SKU numbers RZ09-01963 and RZ09-01964, known as the Mid 2017 model. This commit adds support for the H3Q model. With respect to coreboot, there are few known differences: 1. Only the H2U has TPM. 2. The USB ports are different. 3. The screen size (and therefore VBIOS Table) is different. 4. The hda_verb is very slightly different. 5. The gpio is different. Change-Id: I493a651e52c2eb938daa67a05e9caaa784020fa4 Signed-off-by: Reagan Bohan <xbjfk.github@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-03mb/system76/rpl: Fix addw4 Kconfig nameTim Crawford
Change-Id: I1ed280c1e62e0f094fd40d2165892240f76de390 Fixes: 29f1b791270b ("mb/system76/rpl: Add Adder WS 4 as a variant") Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-06-03mb/system76/rpl: Hook up TAS5825M initTim Crawford
Ensure per-board smart amp init is configured. Fixes speaker output on oryp12. Change-Id: I40ff1889dd144bf83ef85979a55535493aa7abdd Fixes: 8b9716e2269d ("mb/system76/rpl: Add Oryx Pro 12 as a variant") Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2024-06-03mb/system76: Add SPDX ID to devicetree filesTim Crawford
Change-Id: I55f2730f7277a3c699b86ded5864e9690d92d518 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82700 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-31mainboard/google/rex: Enable Rex64 build configurationSubrata Banik
- Add Rex64 board to Kconfig menu - Enable building for Rex64 with x86_64 support Change-Id: I02e2c49b4aeb2cb98d9d0cb66717db18c3f96d45 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82625 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-31mb/google/brya/var/nova: Update USB ports settingKenneth Chan
Update used USB port[2][3](type-a) setting for nova. BUG=b:328711879 TEST=emerge-constitution coreboot chromeos-bootimage Change-Id: I63cf97b23627feac05743f2a6e514a33fcaf7dff Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82703 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2024-05-31mb/google/trulo: Support OCP fault on A0/1 portsPranava Y N
The devicetree entry and gpio.c updated as per the schematics of Trulo to map the OC fault signals from A0/A1 USB ports. BUG=b:335858378 TEST= Able to build google/trulo Change-Id: Ic17debc5eecebca8c000c43a660e1b52d2932f2a Signed-off-by: Pranava Y N <pranavayn@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82637 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-05-30tree: Remove duplicated <soc/gpio.h>Elyes Haouas
<gpio.h> is supposed to chain-include <soc/gpio.h>. Change-Id: Ib25581bd2c8dd38cdd0396561ce5f9a782365f14 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82691 Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-30mb/siemens/mc_ehl5: Remove DDI settings from devicetreeMario Scheithauer
Since this mainboard no longer uses the FSP GOP driver, the DDI port settings are no longer necessary. The GOP driver was used in the initial phase of development where we used Tianocore as payload for some test cases. Finally, this mainboard uses a self-made Linux payload, which does the graphic initialization. BUG=none TEST=Boot into Linux and check if graphic works correctly Change-Id: Ie9e135fbc2627546d6ef95d7d5ff3e9a9222b5d2 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82663 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-29mb/system76/rpl: Add Adder WS 4 as a variantTim Crawford
The Adder WS 4 (addw4) is a Raptor Lake-HX board. Tested with a custom edk2 UefiPayloadPkg. Working: - PS/2 keyboard - I2C HID touchpad - Both DIMM slots (with Crucial CT8G48C40S5) - M.2 NVMe SSDs - All USB ports - MicroSD card reader - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Backlight controls on Linux 6.8 - DisplayPort output over USB-C - Internal microphone - Internal speakers - Combined headset + mic 3.5mm audio - 3.5mm microphone input - S3 suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.8.0 - TPM 2.0 device Not working: - Discrete/Hybrid graphics - Detection of devices in TBT slot on boot Change-Id: I4a6819cbcf64f68237008adebdd7eb196336514c Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82595 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-29mb/system76/rpl: Add Oryx Pro 12 as a variantTim Crawford
The Oryx Pro 12 (oryp12) is a Raptor Lake-HX board. Tested with a custom edk2 UefiPayloadPkg. Working: - PS/2 keyboard - I2C HID touchpad - Both DIMM slots (with Crucial CT8G48C40S5) - M.2 NVMe SSDs - MicroSD card reader - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Backlight controls on Linux 6.8 - Internal microphone - Internal speakers - Combined headset + mic 3.5mm audio - 3.5mm microphone input - S3 suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.8.0 - TPM 2.0 device Not working: - Discrete/Hybrid graphics - Thunderbolt Change-Id: I11cf2dbd1512ebae44e0109bdb78e6eafa027444 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-29mb/system76/rpl: darp9: Add SSD RTD3 configsTim Crawford
Some drives block the CPU from reaching C10 during S0ix suspend without the RTD3 configs. Fixes suspend with the following drives: - Kingston KC3000 (SKC3000D/4096G) - Kingston HyperX (SHPM2280P2H/240G) - Solidigm P44 Pro (SSDPFKKW010X7) The following drives continue to work: - Samsung 970 Evo (MZVLB250HAHQ) - WD Black SN770 (WDS250G3X0E) - WD Green SN350 (WDS240G2G0C-00AJM0) - WD Blue SN570 (WDS100T3B0C) Change-Id: Ia369727d0f1aa5ff546cfb5700a63063730e8248 Signed-off-by: Tim Crawford <tcrawford@system76.com> Tested-by: Levi Portenier <levi@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2024-05-29mb/intel/mtlrvp: Enable EC MKBP deviceJay Patel
MKBP device is required for passing events from input sources to AP. Input sources include buttons (power, volume); switches (lid, tablet mode) and sysrq. BUG=b:342227155 TEST=Able to build coreboot for mtlrvp platform and switch tablet mode. Change-Id: I630421c83784bb4492486d72290b9e8cdada1d47 Signed-off-by: Jay Patel <jay2.patel@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82612 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2024-05-29mb/google/nissa/var/sundance: Add WWAN power off sequenceLeo Chou
Sundance support FM101 WWAN, use wwan_power.asl to handle the power off sequence BUG=b:343139385 TEST=Build and boot on sundance Change-Id: I82085172db370ab5a6c0f77afe6042c53b89e43e Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-29mb/google/nissa/var/pujjoga: Update touchscreen IC settingsRoger Wang
Modify the Goodix touchscreen from new vendor and remove 3 unused touchscreens. According to the information provided by the key-part team. BUG=b:340689681 TEST=Build and check Goodix touchscreen can work. Change-Id: I1e6349e80431aadf27cd72b8439b01f95348071d Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82427 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-29mb/google/nissa/var/sundance: Update eMMC DLL settingsRoger Wang
Currently Samsung eMMC (KLMBG2JETD-B041) can't power on to OS nomally. According to Intel provides eMMC DLL delay patch that tuning on each Sundance different eMMC system to modify some system can't boot to OS problem. BUG=b:342057438 TEST=Build and check each SKU eMMC can work. Change-Id: I29d4305bbe5f91d822d947cae942b654e80a8a57 Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82602 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-29tree: Remove unused <string.h>Elyes Haouas
Change-Id: I9ed1a82fcd3fc29124ddc406592bd45dc84d4628 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-05-29tree: Use <stdio.h> for snprintfElyes Haouas
<stdio.h> header is used for input/output operations (such as printf, scanf, fopen, etc.). Although some input/output functions can manipulate strings, they do not need to directly include <string.h> because they are declared independently. Change-Id: Ibe2a4ff6f68843a6d99cfdfe182cf2dd922802aa Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82665 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-29tree: Remove unused <stddef.h>Elyes Haouas
Change-Id: I7d7ad562eeff7247b7377b6570d489faee0aeda0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82669 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-05-28mb/system76/tgl: Update VBTs to version 250Tim Crawford
Commit 4c7e97b26a34 ("Update fsp submodule to upstream master branch") included an update to the VBT from 240 to 250, breaking parsing of existing VBTs. After that commit, the VBT was parsed as (from gaze16-3060-b): [DEBUG] PCI: 00:02.0 init [INFO ] GMA: Found VBT in CBFS [INFO ] GMA: Found valid VBT in CBFS [INFO ] framebuffer_info: bytes_per_line: 4096, bits_per_pixel: 32 [INFO ] x_res x y_res: 1024 x 768, size: 3145728 at 0xd0000000 [DEBUG] PCI: 00:02.0 init finished in 6 msecs When the expected output is: [DEBUG] PCI: 00:00:02.0 init [INFO ] GMA: Found VBT in CBFS [INFO ] GMA: Found valid VBT in CBFS [INFO ] framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32 [INFO ] x_res x y_res: 1920 x 1080, size: 8294400 at 0xd0000000 [DEBUG] PCI: 00:00:02.0 init finished in 6 msecs Generate blobs for the new version using Intel Display Configuration Tool (DisCon) v3.3, based on the existing 237 and 240 VBTs. (For our edk2 payload, the UEFI GOP driver was updated to 17.0.1077.) Tested on all affected systems: - darp7 - galp5 - gaze16-3050 - gaze16-3060 - gaze16-3060-b - lemp10 - oryp8 Tested: - Boot splash displays on screen again - Firmware setup menu is rendered, at correct resolution Change-Id: I918356d9f660b985ee4408ef77544fbd071ab35f Signed-off-by: Tim Crawford <tcrawford@system76.com> Tested-by: Daniel Sutton <daniel@system76.com> Tested-by: Jacob Kauffmann <jacob@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-28mb/google/brox: Add romstage early graphicsSowmya Aralguppe
Select MAINBOARD_USE_EARLY_LIBGFXINIT for brox to enable SOL image. This patch enables Sign of Life image during MRC training. BUG=b:335369811 TEST=Able to boot to ChromeOS with SOL image. CPU log: [SPEW ] bootmode is set to: 0 (boot with full config) [0.384818] DP PHY mode status not complete [0.388911] DP PHY mode status not complete [0.393197] DP PHY mode status not complete [0.397484] DP PHY mode status not complete [0.401771] DP PHY mode status not complete [0.406057] DP PHY mode status not complete [0.410345] DP PHY mode status not complete [0.414632] DP PHY mode status not complete [0.418916] DP PHY mode status not complete [0.423203] DP PHY mode status not complete [0.427491] DP PHY mode status not complete [0.431777] DP PHY mode status not complete [INFO ] Informing user on-display of memory training. [DEBUG] FMAP: area COREBOOT found @ 1877000 (7901184 bytes) [WARN ] CBFS: 'preram_locales' not found. [ERROR] ux_locales_get_text: preram_locales not found. [DEBUG] FMAP: area RW_ELOG found @ f20000 (16384 bytes) [INFO ] ELOG: NV offset 0xf20000 size 0x4000  elogtool list: 0 | 2024-05-10 02:26:07-0700 | Log area cleared | 4088 1 | 2024-05-10 02:26:07-0700 | Early Sign of Life | MRC Early SOL Screen Shown 2 | 2024-05-10 02:26:51-0700 | Memory Cache Update | Normal | Success 3 | 2024-05-10 02:27:09-0700 | System boot | 4 4 | 2024-05-10 02:27:09-0700 | Firmware Splash Screen | Enabled 5 | 2024-05-10 02:27:11-0700 | System Reset 6 | 2024-05-10 02:27:11-0700 | Firmware vboot info | boot_mode=Developer | fw_tried=A | fw_try_count=0 | fw_prev_tried=A | fw_prev_result=Unknown 7 | 2024-05-10 02:27:18-0700 | ACPI Enter | S5 8 | 2024-05-10 02:27:36-0700 | System boot | 5 9 | 2024-05-10 02:27:36-0700 | Firmware Splash Screen | Enabled 10 | 2024-05-10 02:27:37-0700 | System Reset 11 | 2024-05-10 02:27:37-0700 | Firmware vboot info | boot_mode=Developer | fw_tried=A | fw_try_count=0 | fw_prev_tried=A | fw_prev_result=Unknown Change-Id: I1d4795825960bc58f8f7ef494b01aa975f3bc346 Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
2024-05-28mb/google/trulo: Add initial devicetree.cbSubrata Banik
This patch adds initial PCI device entries into the baseboard devicetree.cb. TEST=Able to build google/trulo. Change-Id: I6ec25b98379cf7c8cbdb5be94d9f3ea43878620c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-28mb/google/trulo: Mark unused USB ports as emptySubrata Banik
This patch marks unused USB ports (USB2.0/TCSS) empty to avoid prompting wrong dmesg as below. ``` usb usb2-port3: Cannot enable. Maybe the USB cable is bad? ``` Trulo variants to override the USB ports as per the target board design. TEST=Able to build google/trulo. Change-Id: I6240e66ed3d1a7198c1a526fdca2483910157235 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-28mb/google/trulo: Program EC ranges (host cmd and memory map)Subrata Banik
This patch adds chip config entries for EC host cmd and memory map ranges. TEST=Able to build Google/Trulo. Change-Id: Id4b0f3bba934c8da56b6d7ca8579b46b6cccac28 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-27mb/aoostar: Add Alder Lake based AOOSTAR R1 (WTR_R1)Federico Amedeo Izzo
AOOSTAR R1 is a Chinese NAS based on Intel N100 (Alder Lake N), with two 3.5" HDD slots, an M.2 NVMe 2280 SSD slot and a single DDR4-3200 SODIMM slot up to 32GB. It also comes with 2x 2.5Gb Intel NICs, Intel AX200 WiFi + BT and USB-C Alt-DP Power Delivery. Working: - DDR4 RAM (tested with Crucial 16GB 3200MHz CL22) - Automatic FAN control (IT8613E Super I/O) - M.2 NVME slot - 2x SATA ports (Issue on 3.5" HDD, see below) - USB 2.0 ports - USB 3.0 ports - USB-C port with Alt-DP and PD - HDMI / DisplayPort ports - 2x 2.5Gb NICs - WiFi + BT - MicroSD card reader - ASPM (Unavailable on stock) - Linux (Arch Linux, kernel 6.8.7-arch1-1) UEFI booting with EDK2 - Windows 10 UEFI booting with EDK2 Broken: - Power button (OFF->ON broken, ON->OFF works) - 3.5" SATA HDDs (Detected only after reboot) Untested: - Internal audio - S3 My motivation for doing this port is enabling ASPM, as it makes a great difference on idle power consumption (from 8.4W to 5W measured from the wall). The last remaining annoyance of this port is the power button not working. I spent a few hours double checking the Super I/O registers but then I gave up. A workaround for this is to use the "ON after power loss" feature and reconnect the power cord to turn on the board. It's not a big problem for a NAS that will stay ON 24/7. Any hint on the power button or 3.5" HDD issue is welcome. VBT extracted from vendor UEFI firmware version 1AXFE 0.01 x64 (Build date and time 11/29/2023 10:57:44) Compiled with FSP GOP video initialization, using IFD descriptor and ME blob extracted from vendor UEFI firmware (see above). The board can be flashed externally using a 1.8V adapter, I used a CH341a modded for 3.3V I/O. Internal flashing works, as flash is not read/write protected. Patchset 5: Re-enabled dptf, added default options to Kconfig. Patchset 7: Configured USB port mapping and overcurrent, USB3.0 works Patchset 8: Fixed microSD card reader Patchset 13: Change Super I/O Fan configuration to reduce fan noise Change-Id: I9414eb742b6b90459e010b038c1994537e9801a5 Signed-off-by: Federico Amedeo Izzo <federico@izzo.pro> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82010 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-27mb/google/ovis/var/deku: Set PsysPL2 value to 178WTony Huang
Adjust setting as recommended by power team. Add ramstage.c in Makefile.inc to set psys_pl2_watts in variant_devtree_update(). Also copy CPU power limit values from ovis baseboard. BUG=b:320410462 BRANCH=firmware-rex-15709.B TEST=FSP debug emerge-ovis coreboot intelfsp check overrides setting [INFO] CPU PsysPL2 = 178 Watts [INFO] Overriding PsysPL2 (178) [INFO] Overriding power limits PL1 (mW) (19000,28000) PL2 (mW) (64000, 64000) PL4 (W) (120) Change-Id: I9ce3a8f843a87e81d404778aaf250b876b6801eb Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-05-27mb/google/ovis/var/deku: Increase TDP PL1 value from 28 W to 33 WTony Huang
Adjust settings as recommended by thermal team. Set PL1 max value tdp_pl1_override from 28W to 33W. PL2, PL4 remain the same as CPU default. BUG=b:308704811 BRANCH=firmware-rex-15709.B TEST=emerge-ovis coreboot chromeos-bootimage built bootleg and verified test result by thermal team Change-Id: Iad0bca913496dda666ba9bcfe5f6fce1a6396692 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82615 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-27mb/google/ovis/var/deku: Set TCC_offset to 5Tony Huang
Adjust settings as recommended by thermal team. Set tcc_offset value to 5 in devicetree. BUG=b:308704811 BRANCH=firmware-rex-15709.B TEST=emerge-ovis coreboot chromeos-bootimage built bootleg and verified test result by thermal team Change-Id: I30f54ae6017c54c91ff9b432bba0ebd5bfc65ab9 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82614 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-27mb/google/rex/var/deku: Update DPTF parametersTony Huang
Adjust settings as recommended by thermal team. Update DPTF parameters based on b:308704811#comment4. BUG=b:308704811 BRANCH=firmware-rex-15709.B TEST=emerge-ovis coreboot chromeos-bootimage built bootleg and verified test result by thermal team Change-Id: I710682771bd0679ae4b44dd43be68f60e8984b2e Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-24soc/intel/xeon_sp: Move get_cxl_mode out of soc/util.hShuo Liu
get_cxl_mode() is the interface for CXL mode config check used by SoC codes. It could be implemented by mechanisms outside of the SoC codes, e.g. board codes or OCP VPD driver. Move the interface declaration out of soc/util.h to a dedicated header, a.k.a., soc/config.h, so that the implementation codes do not need to include soc/util.h where there are lots of irrelevant definitions. Future SoC config check interfaces could be added to soc/config.h as well. The default weak implementation is moved out of util.c to config.c as well. TEST=Build and boot on intel/archercity CRB Change-Id: Ia0302b0d3fd93c49e1d6f64e8159f59d50f33e20 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82293 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-24mb/google/trulo: Refactor gpio pad configurationSubrata Banik
This patch tries to simplify the baseboard/variant GPIO programming for Google/Trulo. The idea is to let each variant maintain its own complete GPIO PAD configuration table instead of having a back-and-forth call between baseboard and variants. With this patch coreboot performing GPIO programming is now much simpler where the common code block calls into respective variants and gets the gpio table prior to the pad configuration. BUG=b:334826281 ([TWL] Decouple GPIO from baseboard to variant) TEST=Able to build google/orisa. Change-Id: I4ab88ac094a45c608cd894feb5eeec24b867527a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-24mb/google/nissa: Fix potential null pointer dereferenceSubrata Banik
* Introduce a null check before calling `gpio_padbased_override` in `variant_configure_pads`. * This prevents potential errors in cases where the `variant_gpio_override_table` function returns a null pointer, indicating that there are no override pads to configure. BUG=b:334826281 TEST=Able to avoid hang incase there is no GPIO override. Change-Id: I733210a08091b37eda6e6b0d6924aafd5e7e6280 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82628 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-23device: drop unnecessary CHECK_REV_IN_OPROM_NAME optionFelix Held
The CHECK_REV_IN_OPROM_NAME Kconfig option was introduced to solve the problem of the PCI VID/DID combination of the Picasso iGPU not being sufficient information to know which VGA BIOS file to run, so a new function that additionally checks the PCI revision of that device was introduced. Later it turned out that there might be a case where even that isn't sufficient, so the soc_is_raven2() function is used in the remap function to always use the correct VBIOS file. Picasso is the only SoC that selected the CHECK_REV_IN_OPROM_NAME Kconfig option, so all other SoCs are unaffected by this change. Now that we use the VBIOS images with only the PCI VID and DID in the CBFS file name for Picasso, SeaBIOS will find the VBIOS with the same ID as the iGPU in CBFS and we don't need the workaround to add a third VBIOS image via VGA_BIOS_DGPU_* that has the name that SeaBIOS expects. This will result in SeaBIOS now running the VBIOS that has the same PCI VID/DID as the hardware which will be the wrong one in the RV2 silicon showing the PCO silicon PCI VID/DID, but that was also the case with the VGA_BIOS_DGPU_* workaround where the board's Kconfig just selected one of the two possible images during build time and hoped that it was the correct one for that actual hardware. The only board where this patch might cause a regression compared to the old behavior is the AMD Cereme reference board with Pollock APU, but I'm not even sure if any coreboot developer still has one of those boards, so I'm willing to accept that. To properly solve the problem with SeaBIOS using the correct VBIOS file in all cases, we'd need to generate that info during coreboot runtime and somehow pass it to SeaBIOS, but that's out of scope for this patch. TEST=On Mandolin with PCO silicon, the display output in both SeaBIOS and Ubuntu still works. Booting Windows 10 via the pre-built EDK2 payload that I'm using also resulted in the display output working. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia6de533c536044698d85404427719b8f534870fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/82598 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-23mb/google/brox/var/brox: Remove mux references from typec portPrashant Malani
The Type-C kernel driver no longer programs the AP mux, as of https://review.coreboot.org/c/coreboot/+/82077. So remove device references to the TCSS Mux control device from the Type-C port driver. This eliminates the following kernel error which was observed as a result of the kernel trying to program muxes it no longer has control over: [ 4.618600] cros-ec-typec GOOG0014:00: Failed to get mux info for port: 0, err = -95 [ 4.618608] cros-ec-typec GOOG0014:00: Configure muxes failed, err = -95 BUG=b:341331428 TEST=Run system reboot; configure mux kernel errors no longer seen. Change-Id: I93e498b12b109c0e649a23a4a49868976a9ee06b Signed-off-by: Prashant Malani <pmalani@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82599 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-23mb/amd/birman/display_card_type.h: add missing includeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5208ceeec17051e7849263a4caa0838efd59c044 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-05-23mb/amd/birman/display_card_type.h: add missing include guardsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaf4478814e672fb8cfae5ffc4fa89c475f5bb0b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82607 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-23mb/google/brya: Add romstage early graphics for nissaRonak Kanabar
1) Add all changes needed for early graphics 2) select MAINBOARD_USE_EARLY_LIBGFXINIT for nissa The InnoLux (N156HCN-EBA C7) panel is used for the device tree. BUG=b:296433986 TEST=On-screen text message seen during MRC training on Craask Logs: [NOTE ] MRC: no data in 'RW_MRC_CACHE' [SPEW ] bootmode is set to: 0 [0.171409] DP PHY mode status not complete [0.175509] DP PHY mode status not complete [0.179799] DP PHY mode status not complete [0.184087] DP PHY mode status not complete [0.188376] DP PHY mode status not complete [0.192665] DP PHY mode status not complete [0.196954] DP PHY mode status not complete [0.201243] DP PHY mode status not complete [0.205532] DP PHY mode status not complete [0.209821] DP PHY mode status not complete [0.214110] DP PHY mode status not complete [0.218397] DP PHY mode status not complete [INFO ] Informing user on-display of memory training. Change-Id: I33cfc5d1f8c25c344e598befd21c50a78a65275a Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78932 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-23mb/cwwk: Add CWWK CW-ADL-4L-V1.0 boardBrandon Weeks
This board is the CWWK variant based upon Alder Lake with 4 2.5 GbE ports, similar boards are available in other port configurations. As a low cost, relatively high performance board with 4 NICs, it is well suited for networking or 'homelab' tasks. CPU: Intel N100 or N350 Memory: DDR5-4800 SODIMM (max 16 GB) NIC: 4x Intel I226-V 2.5 GbE Expansion: - M.2 2230 E key - M.2 2280 M key - USB 2.0 header - Fan header External ports: - DC power - 4x Ethernet - Display Port - HDMI - 4x USB 2.0 - Micro SD Working: - Boots Debian 12 with SeaBIOS and EDK II payloads - Serial port - External USB ports - DisplayPort / HDMI - 4x Intel I226 2.5 GbE NICs - M.2 ports - Micro SD slot - ACPI S3 Not working / not tested: - Fan (ITE IT8613E) - Audio - S0ix - Internal USB ports VBT extracted from vendor UEFI firmware version ADLN 0.01 x64 (04/04/2023 11:42:38). Change-Id: Ice9174d95c10afc6a22ddd15fb3be4fa38d329be Signed-off-by: Brandon Weeks <me@brandonweeks.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-23mb/google/nissa/var/orisa: Generate RAM ID for Micron MT62F512M32D2DR-031 WT:BAmanda Huang
Add Micron part MT62F512M32D2DR-031 WT:B only for Orisa. DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) BUG=b:337178014 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I559ed817250c40795e6c613794d4f65c636f5fc5 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82586 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-22Revert "mb/google/rex/var/deku: Configure GPIO"Tony Huang
This reverts commit 7088257b1ab715e93506619727e3bf589ea688fb. Reason for revert: Intel suggest is NC only. No need to change anything that isn't broken. Change-Id: I976a85b35c69b03f1bc0ccd2bc7df923e47be815 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82572 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-22mb/prodrive/hermes: Tidy up hda_verb.cAngel Pons
Use the `AZALIA_PIN_CFG_NC(0)` macro instead of `0x411111f0` and tidy up some comments (align them and be consistent with capitalisation). Tested with BUILD_TIMELESS=1, prodrive/hermes remains identical. Change-Id: I1ff1197b1309fc0e5b978d6d36867a3f1a68c67c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-05-22mb/amd/birman/devicetree_phoenix_opensil: add USB PHY configFelix Held
Now that we also have the devicetree registers for the USB PHY config in the openSIL case, add the USB PHY config setting from the Phoenix with FSP devicetree. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3a0acbf1b9d705dbf09f4480eb35e71e587ddd44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-05-22mb/amd/birman/update_devicetree_phoenix_opensil: update DDI1 configFelix Held
Use the now common get_ddi1_type function to update the connector type of the DDI1 port to match the display output extension card plugged into the reference board. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7c51eab0d32e0a1708da415f690689a8ec38dcd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82583 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-22mb/amd/birman: factor out get_ddi1_typeFelix Held
Both port descriptor files used in the FSP case contain an identical get_ddi1_type implementation, so factor it out into a separate file. This will also allow using the same function in the openSIL case in a following patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6f5b75b9bdbdc67901d157079785c8fa2915bf0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/82582 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-22mb/amd/birman/devicetree_phoenix_opensil: add static DDI configurationFelix Held
Add a static DDI port configuration to the devicetree used in the Phoenix with openSIL case. The configuration is taken from the birman_ddi_descriptors array in port_descriptor_phoenix.c. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7b85b04114591f3e9da183019c98ca2cb08e59da Reviewed-on: https://review.coreboot.org/c/coreboot/+/82581 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-22mb/amd/birman/devicetree_phoenix_opensil: remove unexpected '<'Felix Held
Remove the unexpected '<' char at the end of the comment about the PSPP policy config. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id821351ce3a7a2b7844d8e7478fa3de3227a7da9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82579 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-05-22mb/intel/archercity_crb: Fix build for specific configurationsPatrick Rudolph
Guard OCP functions calls to allow builds without OCP drivers. Change-Id: Ie9a82387366a8bb3387bcba3ec7a4c7f0100f78c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-22mb/intel/mtlrvp: Include fw_config.c fileAnil Kumar
Update Makefile to include fw_config file for mtlrvp board. Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: Id41cd8b015a796f7a959ceccf85106a48d15ae35 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82559 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-22Revert "mb/google/brox: Update verb table to fix headset detection"Terry Cheong
This reverts commit f867c9c5473156617691d78350c362cd993bfcdd. The new verb table breaks external mic detection on brox. Revert and use old verb tables instead. BUG=b:330433089 BRANCH=main TEST=Verified headset on Brox When connected to audiojack in power_save state of legacy hda driver, headset is detected and audio is resumed. Change-Id: I0d8c092de6166b2c62f5ecc3deaf4960128e6106 Signed-off-by: Terry Cheong <htcheong@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82273 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-21mb/google/brya/var/nova: Add SOLDERDOWN supportKenneth Chan
Nova will use SOLDERDOWN. Add memory.c to override baseboard. Update dram id table for correct platform parameter. BUG=b:328711879 Change-Id: I6fbce991ef5ab9f0e6216ad1a5af73fcc1996a2a Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82474 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-21mb/google/brox/var/greenbayupoc: Update verb table from ALC256 to ALC236Wu Garen
On GreenbayPOC, HDA Codec used is ALC236, different with Brox (ALC256) Update to Realtek provided verb table for ALC236 audio codec. BUG=b:336967284 TEST=Verified headset and audio workable on DUT with "rec" and "aplay" command. Change-Id: I9fbe57a0acab20387754f6b6cb5705e34c1c149b Signed-off-by: Wu Garen <wu.garen@inventec.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82413 Reviewed-by: Ivan Chen <yulunchen@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-21mb/google/brya/var/bujia: Add devicetree based on schematicsShon Wang
Add devicetree settings per the schematic. Differences to gladios: 1. remove SD reader 2. remove EMMC setting 3. modify USB port distribution FRONT ------------------------------------------------------- | A3 A1 | | C0 A2 A0 | ------------------------------------------------------- BACK ------------------------------------------------------- | --------------- | | | TX25A | | ------------------------------------------------------- BUG=b:327549688 TEST= USE="-project_all project_bujia" emerge-brask coreboot Change-Id: Ia010e99c21e8d6088f6bb873f79dc19cadc9e455 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81447 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-05-20mb/prodrive/hermes/hda_verb.c: Refactor port B Vref cfgAngel Pons
Refactor the `get_port_b_vref_cfg()` function to only return the variable bits of the value. The NID itself is not connected, and the `misc` field in the verb conveys the Vref value. Change-Id: I5108f5339c5b002403a4e5339da6d52046c8bcbe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82395 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-17mb/google/dedede/var/kracko: Disable un-used C1 port by daughterboardRobert Chen
Probe C1 port in devicetree and disable un-used C1/A1 port by FW_CONFG. BUG=b:339534479 BRANCH=firmware-dedede-13606.B TEST=emerge-dedede coreboot chromeos-bootimage flash and check boot log on DUT. Change-Id: I944ff6f2fa712e7579ed1c9879f75835adc3ac4c Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-05-17mb/google/brask/var/nova: Remove unused retimerKenneth Chan
Remove unused setting for retimer. BUG=b:328711879 Change-Id: I48d8680d43a07aa3408dfbf5b25b568c2b51b343 Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82475 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-16mb/intel/beechnutcity_crb: Add GNR/SRF-SP 2S server board Beechnut CityShuo Liu
Beechnut City CRB is the 2 socket reference board for 6th Gen Xeon-SP SP SoCs (Granite Rapids SP and Sierra Forest SP). This patch initially sets the code set up as a compilation target with GNR N-1 FSP, and with basic feature supports (Integrated IO Controller (IIO) configuration, BMC, UART, HPET). TEST=Build on intel/beechnutcity CRB Change-Id: I3f6a0fb97b62baadb438fb9f11fdd78fccb3f89a Signed-off-by: Shuo Liu <shuo.liu@intel.com> Co-authored-by: Gang Chen <gang.c.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-05-16mb/intel/avenuecity_crb: Add GNR/SRF-AP 2S server board Avenue CityGang Chen
Avenue City CRB is the 2 socket reference board for 6th Gen Xeon-SP AP SoCs (Granite Rapids AP and Sierra Forest AP). This patch initially sets the code set up as a compilation target with GNR N-1 FSP, and with basic feature supports (Integrated IO Controller (IIO) configuration, BMC, UART, HPET). TEST=Build on intel/avenuecity CRB Change-Id: I64fdd5388aadf7732f6d3daa600c1455d3672a46 Signed-off-by: Gang Chen <gang.c.chen@intel.com> Co-authored-by: Shuo Liu <shuo.liu@intel.com> Co-authored-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-05-16mb/amd/birman/update_devicetree_phoenix_opensil: use common header fileFelix Held
Instead of including stub/mpio/chip.h, include chip/mpio/chip.h that will include the correct implementation to be able to use the same file with both the openSIL stub and the actual openSIL implementation glue code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaae26a0dfe0ba96842e72582c06f1b0b3f29871c Reviewed-on: https://review.coreboot.org/c/coreboot/+/82472 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-16mb/google/rex: Remove redundant VPU enablement codeSubrata Banik
This patch removes VPU enablement code that is no longer needed because the VPU is already enabled by default in the baseboard devicetree. BUG=b:332488817 TEST=Able to see VPU PCI device in lspci list after booting google/screebo to OS Change-Id: I94de92e970be1548068ed4e19309a95129f041ff Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82423 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-16mb/google/rex: Enable VPU device for Rex/Ovis baseboardSubrata Banik
This patch enables the Versatile Processing Unit (VPU) by default for Rex/Ovis baseboard. VPU is a dedicated AI engine that is included in the 14th generation "Meteor Lake" Core processors. The VPU is designed to efficiently run AI models directly on the system on chip (SoC). There is no power regression observed while keeping the VPU default enabled to run AI models natively hence, this patch enables the VPU by default. BUG=b:332488817 TEST=Able to see VPU PCI device in lspci (0:11:0) list after booting google/screebo to OS. Change-Id: I8b3521c8ec613b002f971eaf9d346927fe8cd656 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-16mb/google/rex/var/baseboard/ovis: Support CPU power limits per variantTony Huang
There is no direct way to override CPU default power_limits for different SKUs. This CL add structure variant_get_soc_power_limit_config() for variants to define and configure the values of soc_power_limits_config for current CPU SKU. Variants can override these values i.e. pl1, pl2, psyspl2 in variant_devtree_update(). BUG=b:320410462 BRANCH=firmware-rex-15709.B TEST=FSP debug emerge-ovis coreboot intelfsp check overrides setting Change-Id: Ib60fa4e3fc502d0aeb0c94ad46ba5a55b4dd027c Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82199 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-16mb/google/brask/var/bujia: Update gpio tableShon Wang
Based on latest schematic to update the gpio table. BUG=b:327549688 TEST= USE="-project_all project_bujia" emerge-brask coreboot Change-Id: I3d01e3b9eaef72d9e143f5163ee49d8c8f455b5f Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82412 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-15mb/amd/birman: add function to update MPIO config in devicetreeFelix Held
Phoenix 2 has less PCIe lanes than Phoenix, so some of the lane end numbers need to be adjusted to take that into account. When the Kconfig options WLAN01 or WWAN01 are set, either the WLAN or the WWAN card uses both PICe lanes that are available for those two devices, so the MPIO descriptor information the devicetree needs to be updated accordingly and the bridge to the PCIe port that doesn't have any lane left needs to be disabled. Two other PCIe devices will be disabled when the corresponding Kconfig options ENABLE_EVAL_CARD and DISABLE_DT_M2 have the value that results in the device being disabled via some GPIO driven by the EC. Since the code is specific to the openSIL case, only include it in the build in the CONFIG_BOARD_AMD_BIRMAN_PHOENIX_OPENSIL case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I23c14cc03980ea1e39f7e5aec551b975c237e487 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-05-15mb/amd/birman/devicetree_phoenix_opensil: add stub MPIO chipsFelix Held
Add the stub MPIO chips that contain the PCIe engine configuration for the external PCIe interfaces to the devicetree. Birman's port_descriptors_phoenix.c was used as a reference. The static configuration in the devicetree assumes that the default WLAN0_WWAN0 is selected; for the other cases we'll still need to fix up things accordingly in the mutable devicetree. The WLAN01 and WWAN01 cases still need to be handled in a follow-up patch. Since openSIL currently doesn't use the info from the gpio_group struct element, but deasserts both PCIe reset pins GPIO 26 and 27, the gpio_group isn't specified in the chip configuration in the devicetree. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icabe60322d46c1195284dd77ec39f9d143e3d2cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/81101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-05-15mb/google/brya: Create orisa variantEricKY Cheng
Create the orisa variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:337178014 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_ORISA Change-Id: I0cd8d763ffd8864b455a7f8909e95f6aee8bb23e Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-14mb/google/nissa/var/glassway: Set VccIn Aux Imon IccMax to 25 AFrank Chu
Iccmax of VccIn_Aux is 25A with MBVR design. BUG=b:330117043 BRANCH=firmware-nissa-15217.B TEST=Local build successfully and boot to OOBE normally. Change-Id: I105dc9df53c624fd7fc697408a1097e023a3cd68 Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81445 Reviewed-by: Simon Yang <simon1.yang@intel.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-14mb/google/nissa/var/quandiso: Add stop pin for G2 touchscreenRobert Chen
Add stop pin control for G2 touchscreen refer to G7500_Datasheet_Ver.1.2. BUG=b:335803573 TEST=build and verified touchscreen works normally Change-Id: I4f085c67c0cdb8b9ca3ff03993fda69cca6319ef Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82254 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-14mb/google/brox/var/greenbayupoc: Add vbt from broxEren Peng
Copy the data.vbt from brox to greenbayupoc BUG=b:326413034 TEST=emerge-brox coreboot chromeos-bootimage, flash and boot on DUT Change-Id: I1e8101519ab2ecbb4654c20485fbe83c90656e4d Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82108 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-14mb/google/brox/var/greenbayupoc: Update devicetree and gpio settingsEren Peng
Based on latest schematics GREENBAY_0412.SCH update the gpio and devicetree settings. BUG=b:326413034 TEST=emerge-brox coreboot chromeos-bootimage, flash and boot on DUT Cq-Depend:chrome-internal:7218819 Change-Id: I59f25b8abb7dd8a2dff7ff567b231bddc9db8455 Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-05-14mb/google/nissa/var/sundance: Update HID offset to 0x01 for Focal touchpadLeo Chou
Currently the Focal touchpad does not work. Based on the Focal touchpad vendor, upadet the HID descriptor address from 0x20 to 0x01. BUG=b:339756281 TEST=Build and check Focal touchpad can work. Change-Id: I383ad907e6a23c34ab1bd0f6594a87564e21181d Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-14mb/google/dedede/var/pirika: Add SPD IDs for two new memory partsDaniel_Peng
Support Memory of Micron MT53E512M32D1NP-046 WT:B and Hynix H54G46CYRBX267 in mem_parts_used list, and generate SPD ID for these parts. DRAM Part Name ID to assign MT53E512M32D1NP-046 WT:B 0 (0000) H54G46CYRBX267 0 (0000) BUG=b:337173071 BRANCH=firmware-dedede-13606.B TEST=Run command "go run \ ./util/spd_tools/src/part_id_gen/part_id_gen.go \ JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ \ src/mainboard/google/dedede/variants/pirika/memory/\ mem_parts_used.txt" Change-Id: I9b1a2a622d0ca1298671b1da58beacc1b4244769 Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82094 Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-13mb/asus/p8z77-m: Support AC97 front audio panelKeith Hui
Add a nvram option for front audio panel type. If it is set to AC97, reprogram front line out and microphone pins to match vendor firmware under same configuration. TEST=On asus/p8z77-m housed in an AOpen H340D case with an AC97 front audio panel, front panel line out port is now available as headphone port in Fedora 39 with this patch applied and option set correctly. And it works. Without the patch (or with this option set to HD Audio), front audio ports are completely inoperable. Change-Id: I39ccf066d87c5744a697599861719182768e0728 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-05-13mb/google/rambi: Use <device/dram/ddr3.h>Elyes Haouas
Change-Id: I3aa669042908b92d7b270df077a352e197071780 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82354 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-13mb/intel/{harcuvar,kunimitsu}: Use <spd.h> and <dram/ddr{3,4}.h>Elyes Haouas
Change-Id: I2d73f7815e83e8bf0c6d0a402d32bc99c32c7d90 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82243 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-13mb/google/{eve,glados}: Use <spd.h> and <dram/ddr3.h>Elyes Haouas
Change-Id: I48b833a3727d4b7d7c50371dbe8f090983d80e36 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-13mb/google/brya/var/riven: Copy VBT data file from nivviksDavid Wu
Add data.vbt file for riven recovery image. Select INTEL_GMA_HAVE_VBT for riven as it has a VBT file now. The VBT file is copied from the nivviks reference board. BUG=b:337169542 TEST=build pass Change-Id: I499c1b3e61581483a1640375270f7707ebe8deeb Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82269 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-13mb/google/brox: Disable c1 state auto-demotionAshish Kumar Mishra
Disable c1 state auto-demotion support for brox BUG=None BRANCH=None TEST=Boot brox and verify in fsp debug logs Change-Id: I18d40cd721d46fce4702cf1a943583cd41c03cf4 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82104 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-12mb/google/rex/var/deku: Correct FVM Itrip for GT VR domainTony Huang
Previous CL misspelling VR domain to IA not GT which cause FVM Itrip(GT) not set correctly. This CL corrects it to VR_DOMIAN_GT and confirm FVM Itrip(GT) has set to 54. BUG=b:320410462 BRANCH=firmware-rex-15709.B TEST= FSP debug emerge-ovis coreboot intel-mtlfsp check overrides setting IccLimit[1] = 216 ( 1/4 A) Change-Id: I99df053869aa11b7c82aa0b7f7ec0acf73467a76 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-05-12vc/amd/opensil: introduce common mpio/chip.h header fileFelix Held
The chip drivers in the devicetree use the path where the corresponding chip.h file resides both to include this chip.h file in the static.c generated by util/sconfig from the devicetree and also for the names of the chip config and chip ops struct. To be able to build a SoC using either the MPIO chip driver from the openSIL stub or from the actual openSIL glue code without needing different devicetree files for the different cases, introduce a common MPIO chip.h file that then includes the correct MPIO header file. The chip config and ops structures also need to be renamed to take this change into account. Thanks to Matt for pointing out how to make the path to the actual MPIO chip.h file configurable via a Kconfig setting. This allows overriding this path from site-local without the need to have any reference to site-local in the upstream code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iead97d1727569ec0d23a2b9c4fd96daff4bebcf6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82262 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-12mb/protectli/vault_cml: use combo v1/v2 FSPMichał Kopeć
Also switch configs to use combo v1/v2 FSP The reason for this change is to simplify configuration - instead of multiple targets for VP4630 and VP4650 or VP4670, it's now possible to have one target covering all VP46x0. Change-Id: I1a6f6e873e4ec35b9777dc17c0495151348d1d88 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81963 Reviewed-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-12mb/google/brox/var/greenbayupoc: Configure board for SODIMM useEren Peng
Configure SODIMM settings for greenbayupoc. The SODIMM settings are copied from mainboard/google/brya/variants/baseboard/brask/memory.c. BUG=b:336955026, b:332230842 TEST=emerge-brox coreboot chromeos-bootimage, flash and boot to OS using Hynix HMAG56EXNSA051N 4G and Micron MTA8AFT1G64HZ-3G2R1 8G SODIMM. Change-Id: I1552cadfa81c48fe561947ded078bcca2e6bc6ad Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82085 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-12mb/google/brya/var/riven: Generate SPD ID for supported partsDavid Wu
Add supported memory parts in mem_parts_used.txt, and generate SPD id for these parts. 1. MT62F1G32D4DR-031 WT:B (Mircon) 2. MT62F512M32D2DR-031 WT:B (Mircon) 3. H9JCNNNBK3MLYR-N6E (Hynix) 4. K3LKLKL0EM-MGCN (Samsung) 5. K3LKBKB0BM-MGCP (Samsung) 6. H9JCNNNCP3MLYR-N6E (Hynix) BUG=b:337169542 TEST=build pass Change-Id: I0ff3b1e14fb8bb87d8fc9cbe0e177a5bcedef08c Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82255 Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-05-09mb/google/brox: Sending End of Post (EOP) asynchronouslyKarthikeyan Ramasubramanian
Currently EOP message is sent to CSE late in the boot flow. Instead send it asynchronously to save ~10 ms in boot time. BUG=b:337330958 TEST=Build Brox BIOS Image and boot to OS. Change-Id: I229d16a5dcd072958db3f59a9c364bf7508b3047 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-08mb/google/brox: Fix the pad reset config for WLAN Wake interruptKarthikeyan Ramasubramanian
Update the pad reset config for WLAN Interrupt from PLTRST to DEEP so that it can still act as a wake source during S3 suspend. BUG=b:336398012 TEST=Build Brox BIOS image and boot to OS. Suspend to S0ix & S3 and wakeup successfully using Wake on WLAN. 268 | 2024-05-07 13:56:44-0700 | S0ix Enter 269 | 2024-05-07 13:57:07-0700 | S0ix Exit 270 | 2024-05-07 13:57:07-0700 | Wake Source | GPE # | 3 271 | 2024-05-07 13:59:01-0700 | ACPI Enter | S3 273 | 2024-05-07 13:59:26-0700 | Wake Source | PME - WIFI | 0 274 | 2024-05-07 13:59:26-0700 | ACPI Wake | S3 275 | 2024-05-07 13:59:26-0700 | Wake Source | GPE # | 3 Change-Id: Ie0d6e6c8fefdd081e252ea99d6e3c559a5330b0e Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82234 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-08mb/google/brox/var/brox: increase PsysPmax from 21.5W to 208WLawrence Chang
According to Brox HW design, the PsysPmax is supposed to be 208W. This patch changes PsysPmax setting from 21.5W to 208W. Change-Id: I43f4b00a54dc0dfe6bd690492f9ef92698c9b903 Signed-off-by: Lawrence Chang <lawrence.chang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Shelley Chen <shchen@google.com>
2024-05-08mb/asrock/z97_extreme6: Add new mainboardAngel Pons
That's an ATX mainboard with a LGA1150 socket and four DDR3 DIMM slots. Porting was done using autoport and then doing a bunch of manual edits. This board has two socketed DIP-8 SPI flash chips and a physical switch to choose which one should the system boot from. As long as one of them contains a bootable firmware image, it is possible to reflash the other chip using the internal programmer by flipping the switch after booting to OS. Even if one somehow manages to flash unbootable firmware to both chips, they are socketed: one can carefully remove them from the socket and reflash them externally, which is a relatively safe procedure (when compared to in-circuit flashing, especially if the board isn't designed to safely be flashed in-circuit). In short, the board is hard to brick. Haswell MRC.bin cannot be used because it lacks support for the Z97 PCH found on this mainboard. Broadwell MRC.bin only works with Haswell CPUs so far, as raminit fails on Broadwell CPUs for an unknown reason. Maybe it's something about RcvEn, but it's unlikely it can easily be fixed. Working: - All four DIMM slots - Broadwell MRC.bin for raminit purposes - Serial port to emit spam - POST code display - S3 suspend/resume - All rear USB 3.0 ports - Internal USB 2.0 port - Audio output (green jack) - Integrated graphics (libgfxinit) - HDMI - VBT - Intel GbE (I218-V PHY and PCH MAC) - Realtek RTL8111E GbE - At least one SATA port - M2_1 slot (Gen3 x4, bifurcated from CPU) - Flashing internally with flashrom - SeaBIOS (current version) to boot Arch Linux - NCT6791D Super I/O software-based fan control tested using `sensors` and `pwmconfig`, all 6 fan tachometers and 5 PWM outputs work fine. Untested for now (i.e. should work, will eventually test): - DVI-I, DisplayPort - EHCI debug - Front USB 2.0 and 3.0 ports - The other audio jacks (as well as SPDIF) - The other PCIe and M.2 ports - Non-Linux OSes - PS/2 combo port (can only test with a keyboard) Untestable (i.e. cannot test due to unavailable hardware): - Thunderbolt AIC (Add-In Card) support Not working: - Broadwell CPUs, they require more magic to work (working on it). - Booting from ASM1062 SATA ports with SeaBIOS. Other payloads were not tested. It seems that the problem is with the controllers. - Super I/O automatic fan control: not yet implemented in coreboot. To control fans, use software fan control methods in the meantime. - Acer B247Y board driving a FHD panel of a Samsung S24E650 monitor, connected to the board's HDMI output says "Unsupported resolution" after libgfxinit configured the iGPU outputs in linear framebuffer mode. HDMI output works fine after Linux's i915 driver takes over. Not sure if it's specific to the monitor: the HDMI cable is beaten up, and it is hard to replace (need to relocate the logic board so that the ports are accessible). Change-Id: If1d22547725e59f435de36b973e1bf4f334269a9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Máté Kukri <kukri.mate@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 11:58:33 +0000