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2020-06-25mb/amd/mandolin: Quote string in Kconfig that contains /Patrick Georgi
Newer versions of Kconfig require that. Change-Id: I95f889d462ace1b912b5e6c7320973e8a826f3cb Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42773 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25mb/ocp/deltalake: Enable IPMI KCSMorgan Jang
Config the IO port for IPMI KCS and set bmc_boot_timeout for checking BMC self test result. TEST=Check if the BMC IPMI reponse data is correct or not. Change-Id: I675060299b486986ebc39d8f714615b3e13de89a Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41023 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25mb/google/octopus/variants/bobba: fix disable_xhci_lfps_pm by skuSheng-Liang Pan
due to overridetree.cb set disable_xhci_lfps_pm = 0, need correct condition expression to let function work. BUG=b:146768983 BRANCH=octopus TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] is set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I53621d7674a531adfa40e8703cb2cd01c50376b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42564 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25mb/google/zork: Move PCIE_RST0_L configuration to early GPIO tableFurquan Shaikh
This change moves the configuration of PCIE_RST0_L as native function to happen in early GPIO table. This ensures that the PERST# signal is deasserted as soon as possible when the system comes out of sleep state in case the sleep path asserted/deasserted the PERST# as GPIO out. A big difference in functionality with this change is that PCIE_RST0_L signal is now configured as part of RO, which should be fine since all PCIe devices have a second AUX_RESET_L signal or use PCIE_RST1_L to control the actual reset to the device. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I21a9c25b5a8a6d502cdb79cbe0dbad6ef98d6d63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42739 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25mb/google/zork: Add support for WiFi power sequencingFurquan Shaikh
This change replaces variant_wifi_romstage_gpio_table() with variant_pcie_power_reset_configure() to handle the reset and power sequencing for WiFi devices pre- and post- v3 version of schematics. These are the requirements that need to be satisfied: 1. As per PCI Express M.2 Specification Revision 3.0, Version 1.2, Section 3.1.4 "Power-up Timing", PERST# should stay disabled until `TPVPGL` time duration after device power has stabilized. Value of TPVPGL is implementation specific. 2. For Intel WiFi chip, it is known to get into a bad state if the above requirement is violated and hence requires a power cycle. 3. On pre-v3 schematics: - For both dalboz and trembyle references, GPIO42 drives WIFI_AUX_RESET_L which is pulled up to PP3300_WIFI. - For both dalboz and trembyle references, PP3300_WIFI is controlled using GPIO29. This pad gets pulled high by default on PWRGOOD because of internal pull-up. But, at RESET# it is known to have a glitch. When GPIO29 gets pulled high, it causes WIFI_AUX_RESET_L to be pulled high as well. This violates the PCIe power sequencing requirements. Hence, for pre-v3 schematics on both dalboz and trembyle, following sequence needs to be followed: a. Assert WIFI_AUX_RESET_L. b. Disable power to WiFi. c. Wait 10ms to allow WiFi power to go low. d. Enable power to WiFi. e. Wait 50ms as per PCIe specification. f. Deassert WIFI_AUX_RESET_L. 4. On v3 schematics: - For trembyle: WIFI_AUX_RESET_L is driven by GPIO86 which has an internal PU as well as an external PU to PP3300_WIFI. - For dalboz: WIFI_AUX_RESET is driven by GPIO29. This is active high and has an internal PU. It also has an external 1K PD to overcome internal PU. - For both dalboz and trembyle references, PP3300_WIFI is controlled by GPIO42 which has an internal PU and external PD. Trembyle schematics have a comment saying strong PD of 2.2K but the stuffed resistor is a weak one (499K). ON dalboz, it uses a weak PD (which doesn't look correct and instead should be a strong PD just like trembyle). Having a strong PD ensures that the WiFi power is kept disabled when coming out of G3 until coreboot configures GPIO42 as high. - Thus, for v3 schematics, following sequence needs to be followed: a. Assert WIFI_AUX_RESET{_L} signal. b. Enable power to WiFi. c. Wait 50ms as per PCIe specification. d. Deassert WIFI_AUX_RESET{_L} signal. BUG=b:157686402, b:158257076 TEST=Verified that QCA and AX200 cards both continue working. Tested QCA on Dalboz and Trembyle. Tested AX200 on morphius. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I532131ee911d5efb5130d8710f3e01578f6c9627 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42738 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25mb/google/zork: Update ramstage GPIOs for v3 schematics for dalboz referenceFurquan Shaikh
This change updates the baseboard GPIO table in ramstage to match v3 version of dalboz reference schematics. All variants using this reference are accordingly updated to configure the GPIOs that changed as part of v3 schematics. BUG=b:157165628, b:157744136, b:157743835 TEST=Compiles Signed-off-by: Martin Roth <martinroth@chromium.org> Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: If9d0e35801f9f9b15eddeb4ec7068fed6d401307 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2251394 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Auto-Submit: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42725 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25mb/google/zork: Update ramstage GPIOs for v3 schematics for trembyle referenceFurquan Shaikh
This change updates the baseboard GPIO table in ramstage to match v3 version of trembyle reference schematics. All variants using this reference are accordingly updated to configure the GPIOs that changed as part of v3 schematics. BUG=b:157088093, b:154676993, b:157098434 TEST=Compiles Signed-off-by: Martin Roth <martinroth@chromium.org> Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ib1d6ee2e995c1fca229c20ea63da9a45fb89f64a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2251393 Reviewed-by: Aaron Durbin <adurbin@google.com> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42724 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25mb/google/zork: Update _v3 romstage and wifi GPIO tables for dalbozFurquan Shaikh
This change updates _v3 version of romstage and wifi GPIO tables to match v3 schematics. BUG=b:157165628, b:157744136, b:157743835 TEST=Compiles Signed-off-by: Martin Roth <martinroth@chromium.org> Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Id8b46fcb4552af6eda5b50224b0557bae37f9ebd Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2251392 Reviewed-by: Aaron Durbin <adurbin@google.com> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42723 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25mb/google/zork: Update _v3 romstage and wifi GPIO tables for trembyleFurquan Shaikh
This change updates _v3 version of romstage and wifi GPIO tables to match v3 schematics. BUG=b:157088093, b:154676993, b:157098434 TEST=Compiles Signed-off-by: Martin Roth <martinroth@chromium.org> Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ic605559b3226e2ad9b5b3f3fa45c4aa9f9b5fe22 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2251391 Reviewed-by: Aaron Durbin <adurbin@google.com> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42722 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25mb/google/zork: Prepare variants for v3 schematicsFurquan Shaikh
This change updates variant_romstage_gpio_table() and variant_wifi_romstage_gpio_table() to support v3 version of schematics for dalboz and trembyle reference designs. gpio_set_stage_rom and gpio_set_wifi are divided into two groups: a) Pre-v3 (GPIO table for pre v3 schematics): * gpio_set_stage_rom_pre_v3 * gpio_set_wifi_pre_v3 b) v3 (GPIO table for v3+ schematics): * gpio_set_stage_v3 * gpio_set_wifi_v3 Currently, both _v3 is a copy of _pre_v3, but will be updated in follow-up CLs to make it easier to identify what changed from _pre_v3 to _v3. BUG=b:157088093, b:154676993, b:157098434, b:157165628, b:157744136, b:157743835 TEST=Compiles Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I444875d93100c2f2abdb6dec4312861fd89d9b78 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2251390 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42721 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25mb/google/zork: Drop RAM_ID configuration from romstage gpio tableFurquan Shaikh
RAM_ID GPIOs are configured by ABL based on the information added to APCB. coreboot does not need to configure these pads. This change drops the RAM_ID configuration from trembyle baseboard. Dalboz never really configured RAM_IDs in coreboot. BUG=b:154351731 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ie1dfcc3c185304d917ab4386920445ba0119ac69 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2252710 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42720 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25mb/google/zork: Move variant_early_gpio_table to gpio_baseboard_common.cFurquan Shaikh
This change moves the GPIOs that need to be configured for early access in coreboot to early_gpio_table[] in gpio_baseboard_common.c. These GPIOs include: * Pads to talk to EC * Pads to talk to TPM * Pads to talk to serial console These should be configured in the first stage that runs coreboot i.e. in case of VBOOT_STARTS_BEFORE_BOOTBLOCK, it should be done as part of verstage (which starts on PSP), else it should be done as part of bootblock (which is the first stage that runs on x86). This change drops GPIO_137 from early_gpio_table since that is not really required in early stages. BUG=b:154351731 TEST=Verified that trembyle still boots. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ifbdbb02cbfc65ddb68f0ae75cf4b1f2ea1656b91 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2252709 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-24mb/amd/mandolin: maximize CBFS sizeFelix Held
Change-Id: Ib829da0972bb7ec98f66fe8fe683289d91ad58dc Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-24jasperlake: enable DPTF functionality for dededeSumeet R Pawnikar
Enable DPTF functionality on jasperlake based dedede platform BRANCH=None BUG=None TEST=Built for dedede system Change-Id: I17b6e4e96abee6181b0d1f94c356a32aa82c19b9 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41668 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-24mb/google/zork: Add UPD xhci0_force_gen1 for Trembyle and EzkinilLucas Chen
Add UPD xhci0_force_gen1 for Trembyle and Ezkinil. The default setting is set to disable, and set enabled for Ezkinil. Trambyle -> set default as disable. Ezkinil -> set enable by request. BUG=b:156314787 BRANCH=trembyle-bringup TEST=Build. Verified the setting will be applied on Ezkinil/Trembyle. Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Change-Id: I65d06bfe379f9e42101bfae1a02a619ee2f24052 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2216090 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-24mb/google/volteer/malefor: Update overridetree.cbWilliam Wei
1) Based on malefor schematics, disable unused I2C port, USB port, TBT PCIe 2) Add audio device to the tree BUG=b:150653745, b:154973095 TEST=FW_NAME=malefor emerge-volteer coreboot chromeos-bootimage Boot to kernel and check the devices' function worked properly. Signed-off-by: William Wei <wenxu.wei@bitland.corp-partner.google.com> Change-Id: I9ce465705e8b8f67ddbc9e4eb06c5a8bfac65fcb Reviewed-on: https://review.coreboot.org/c/coreboot/+/42246 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-24volteer: Create volteer2 variantNick Vaccaro
Create the volteer2 variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.1.1). Modified to alphabetize and update to duplicate latest volteer changes currently in the review and merge pipeline. Added the following missing files from the variants/volteer2/ folder: - gpio.c - include/variant/acpi/dptf.asl - acpi/mipi_camera.asl - Makefile.inc - memory/dram_id.generated.txt - memory/Makefile.inc - memory/mem_list_variant.txt - overridetree.cb BUG=b:159135047 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_VOLTEER2 Change-Id: I987c72b83dc993af248a753a2caa56be0f26c1ad Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42605 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-24ACPI: Replace uses of CBMEM_ID_ACPI_GNVSKyösti Mälkki
These are the simple cbmem_find() cases. Also drop the redundant error messages. Change-Id: I78e5445eb09c322ff94fe4f65345eb2997bd10ef Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-06-24volteer: Create delbin variantZhuohao Lee
Create the delbin variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.1.1). BUG=b:158797761 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_DELBIN Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Change-Id: Icf5fc6b9cc6a7c47e52103b2d396bcddb26adf50 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-24mb/amd/mandolin: resize EC FMAP section to match EC firmware sizeFelix Held
The EC firmware is 128k including its header, so there's no need to reserve another 4k for the header. TEST=Mandolin still boots. Change-Id: Id3a7a087bf37461ca8ad3da9a809f13d7f0d570c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42705 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-23hatch: Create wyvern variantPaul Fagerburg
Create the wyvern variant of the puff reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.1.1). BUG=b:158269582 BRANCH=None TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_WYVERN Signed-off-by: Paul Fagerburg <pfagerburg@google.com> Change-Id: Id7a090058d2926707495387f7e90b3b8ed83dac7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42551 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-23hatch: Create faffy variantEdward O'Callaghan
Create the faffy variant of the puff reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.1.1). V.2: Manually modified to keep Kconfig sorted. BUG=b:157448038 BRANCH=None TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_FAFFY Signed-off-by: Edward O'Callaghan <quasisec@google.com> Change-Id: I5f14c2d6144ce3c2e48488ca81f31b3c04dc5fb9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42717 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-23mb/amd/mandolin/acpi: drop gpe.aslFelix Held
Change-Id: I366108334006c81a4d5fb193f583a1e83f7c1456 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-23mb/google/zork: Add support for fingerprint deviceFurquan Shaikh
This change adds support for fingerprint device in overridetree for the following variants: 1. berknip 2. morphius 3. trembyle Generates the following node in SSDT1: Scope (\_SB.FUR1) { Device (CRFP) { Name (_HID, "PRP0001") // _HID: Hardware ID Name (_UID, Zero) // _UID: Unique ID Name (_DDN, "Fingerprint Reader") // _DDN: DOS Device Name Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { UartSerialBusV2 (0x002DC6C0, DataBitsEight, StopBitsOne, 0x00, LittleEndian, ParityTypeNone, FlowControlNone, 0x0040, 0x0040, "\\_SB.FUR1", 0x00, ResourceConsumer, , Exclusive, ) GpioInt (Level, ActiveLow, ExclusiveAndWake, PullDefault, 0x0000, "\\_SB.GPIO", 0x00, ResourceConsumer, , ) { // Pin list 0x0006 } }) Name (_S0W, 0x04) // _S0W: S0 Device Wake State Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x0A, 0x03 }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x01) { Package (0x02) { "compatible", "google,cros-ec-uart" } } }) } } BUG=b:147853944 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I7ccb3633332ce3e388293872af7b22f1867c8465 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-23palkia: separate the gpio pins control for the second touchZhuohao Lee
There are two touch screen controllers on the Palkia device. One is on the lid; another is on the base. To support the different control path (for example: turning off the base's touch event when we don't want to use it however still keeping the lid's touch event), we use the different gpio pins to control the second touch. As a result, we need to modify the devicetree to adopt this change. With this change, we can control the primary and secondary touch screen controller respectively. BUG=b:149714955 TEST=lid/base touch screen works correctly Change-Id: I1f896e334e51c78300af724cbef8d57641ae5612 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-23mb/google/hatch: Make puff and variants share common mainboard.cEdward O'Callaghan
Here we consolidate some of the mainboard.c duplication between Puff and it's variants. Customizations can be done later via introducing a devicetree parameterisation. BUG=b:154071868 BRANCH=none TEST=none Change-Id: I75c2de7ae8efd544d800bc77e34e667c3afa4b01 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42672 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22src/mainboard: Remove unused include 'sandybridge.h'Elyes HAOUAS
Change-Id: I9356a56c34d1c6746cf8acfe931386ffed58ba74 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-22mb/amd/mandolin/hda_verb: use AZALIA_RESET and AZALIA_PIN_CFG macrosFelix Held
TEST=Doesn't change the resulting binary for BUILD_TIMELESS=1. Change-Id: I9fccc53c3d56116027e28a9eec6ec27202017a79 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-22mb/google/volteer/variants/terrador: Enable Cmd MirrorDavid Wu
Enable CmdMirror for Terrador to achieve optimum routing from SoC to DRAMs BUG=b:156435028 BRANCH=none TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I0db9fff0dddf35c99a6cb2a90d40886ed8e18686 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-22mb/emulation/qemu-i440fx,q35: Fix comment stylePaul Menzel
The comment fits in 96 characters, so do it, also getting rid of the unwanted multi-line comment style. Add a dot/period to the end of the sentence. Change-Id: I7b5c7ea5da00d649aa06361e0e0cf2431874a6ec Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-22mb/google/volteer/variants/volteer: clean up gpio.cNick Vaccaro
Remove an unneccessary comment and group the variant_early_gpio_table together based on GPIO group. Changed static variable name gpio_table to override_gpio_table to be more descriptive. BUG=none TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer to kernel. Change-Id: Iabe810df1e5a3df35e3543ab81b9fdb6f76c223a Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42577 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22mb/google/volteer: move volteer devices to overridetree.cbNick Vaccaro
Move the following volteer-specific devices from baseboard's devicetree.cb into volteer's overridetree.cb file: - Goodix Touchscreen - ELAN Touchscreen - ELAN Touchpad - SAR0 Proximity Sensor Adjust the other variant's overridetree.cb files to correspond to the changes made to the baseboard's devicetree.cb in this change. BUG=b:159241303, b:154646959 TEST='emerge-volteer coreboot chromeos-bootimage', flash and boot volteer to kernel and verify that the trackpad works. Change-Id: I30f8266ec87a7cde293c84d3e687d133207b8d59 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-22mb/google/volteer: update fw_config definitionNick Vaccaro
Update fw_config definition in devicetree.cb to match current definition for volteer. BUG=b:159157584 TEST=none Change-Id: I761893818231880d86fd13cfa61319157d06a7d5 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42331 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22mb/google/volteer: Disable D3Cold for TCSS along with pass through modeJohn Zhao
The pass through mode (SW CM) RTD3 is not supported until QS platform. D3Cold is needed to be disabled along with upstream TBT firmware signed_TGL_HR_4C_A0_rev6_pre4_SW_CM_PM_support_ENG_VER_perst_check_fix. This temporary patch will need to be reverted once PM RTD3 support is validated on QS platform. BUG=b:159050315 TEST=Verfiy PM S0ix along with upstream TBT firmware. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I98ed991e4185abf1f3168e33b099e0e97c9075f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42504 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Divya Sasidharan <divya.s.sasidharan@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22mb/google/volteer: Override power limits with SKU-specific limitsTim Wawrzynczak
Using guidance from Intel, a new set of power limits (PL1, PL2 & PL4) are available for TGL-U. They are dependent upon the SKU of the CPU that the mainboard is running on. Volteer is updated here to use these new limits. To accomplish this, the SoC chip config's power_limits_config member was expanded to an array, which can be indexed by POWER_LIMITS_*_CORE macros. Just before power limits are applied, the correct set of them is chosen from the array based on System Agent PCI ID. Therefore, a TGL board should have two sets of power limits available in the devicetree. BUG=b:152639350 TEST=On a Volteer SKU4 (4-core), verified the following console output: CPU PL1 = 15 Watts CPU PL2 = 60 Watts CPU PL4 = 105 Watts Change-Id: I18a66fc3aacbb3ab594b2e3d6e2a4ad84c10d8f0 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-06-22mb/ocp/deltalake: add RW_MRC_CACHE flash regionJonathan Zhang
Add RW_MRC_CACHE flash region to hold MRC cache data. With memory training skipped for subsequent reboots, the boot time is reduced by 8 minutes on OCP Delta Lake server, when FSP verbose logging is turned on. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I27ed00100e1ea9e29b0e71ea5a8397cd550e193a Reviewed-on: https://review.coreboot.org/c/coreboot/+/42025 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22mb/ocp/deltalake: Add OCP Delta Lake mainboardJonathan Zhang
OCP Delta Lake server is a one socket server platform powered by Intel Cooper Lake Scalable Processor. The Delta Lake server is a blade of OCP Yosemite V3 multi-host sled. TESTED=Successfully booted on both YV3 config A Delta Lake server and config C Delta Lake server. The coreboot payload is Linux kernel plus u-root as initramfs. Below are the logs of ssh'ing into a config C deltalake server: jonzhang@devvm2573:~$ ssh yv3-cth root@ip's password: Last login: Mon Apr 20 21:56:51 2020 from [root@dhcp-100-96-192-156 ~]# lscpu Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Byte Order: Little Endian CPU(s): 52 On-line CPU(s) list: 0-51 ... [root@dhcp-100-96-192-156 ~]# cbmem 34 entries total: 0:1st timestamp 28,621,996 40:device configuration 178,835,602 (150,213,605) ... Total Time: 135,276,123,874,479,544 [root@dhcp-100-96-192-156 ~]# cat /proc/cmdline root=UUID=f0fc52f2-e8b8-40f8-ac42-84c9f838394c ro crashkernel=auto selinux=0 console=ttyS1,57600n1 LANG=en_US.UTF-8 earlyprintk=serial,ttyS0,57600 earlyprintk=uart8250,io,0x2f8,57600n1 console=ttyS0,57600n1 loglevel=7 systemd.log_level=debug Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Change-Id: I0a5234d483e4ddea1cd37643b41f6aba65729c8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/40387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-22mb/google/kukui: Add Hynix 4GB discrete LPDDR4X DDR supportHuayang Duan
Support 4GB H9HCNNNCPMMLXR-NEE discrete DDR bootup. BUG=b:156691665 BRANCH=none TEST=Boots correctly and stress test passes on Kukui. test cmd: memtester 1000M Change-Id: I0b29cc1cf0d51eb9d6af112858563193ffa88652 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42502 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22mb/prodrive/hermes: Disable xDCIPatrick Rudolph
The PCI device is used for debugging only and as Windows 10 has no default driver for it, disable it to not scare end users about "missing" drivers. Change-Id: I0b42a9b55f00826c5920c1c259b38382bdcdde72 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42509 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22mb/google/volteer: Change VCM and EEPROM configs for ov8856Daniel Kang
TGL RVP and Volteer use ov8856 camera module from different vendors. TGL RVP from Foxlink and Volteer from Sunny. ov8856 sensor is identical for the two modules but VCM and EEPROM are different. Originally, Volteer ACPI was set to align with Sunny module, GT9679. But it turned out GT9679 is compatible with Foxlink's DW9768. So Volteer camera ACPI configuration doesn't need to keep GT9679. BUG=b:158188369 BRANCH=none TEST=Build and boot volteer proto 2 board. Start a camera app and check user-facing camera functionalities. Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Change-Id: I792608f86a59b16545dfa4edf6508de7a444bb26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Daniel H Kang <daniel.h.kang@intel.corp-partner.google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-06-22mb/google/dedede: Re-configure the USB ACPI objectsKarthikeyan Ramasubramanian
In waddledee and waddledoo, discrete & integrated BT signals are routed to different USB ports. In all the other variant boards, discrete & integrated BT signals are routed to the same USB port (port 8 - index 7). Re-configure the USB devices accordingly. Also device configuration in override tree are applied only if there is a matching device in base devicetree. So configure all the USB devices in base devicetree and turn them off. BUG=b:154064148 TEST=Ensure that the SSDT contains the ACPI objects for enabled USB devices. Change-Id: I1b8bf7f4db1d2661f310bf4874428a6d1de222c6 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42554 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22device/smbus_host: Declare common early SMBus prototypesKyösti Mälkki
Change-Id: I1157cf391178a27db437d1d08ef5cb9333e976d0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-22mb/google/dedede: Add VCM and NVM entry for OV8856 sensorPandya, Varshit B
Add DW9768 VCM device and add its entry in the OV8856's _DSD to allow the V4L2 driver to use the VCM functionality. Also add ACPI entries for AT24 NVM device, this will enumerated as a generic NVM device and not part of the V4L2 framework. BUG=b:155285666 BRANCH=None TEST=Build and able to see DW9768 and AT24 getting listed I2C3 lanes and able to capture image using world facing camera. Change-Id: I19e4a4107c5bc9d96f718d654df50e2705b98c03 Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-22cpu/x86/smm: Use already defined APM_CNT messagesKyösti Mälkki
Change-Id: Ie9635e10dffe2f5fbef7cfbd556c3152dee58ccc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-22mb/google/hatch: Stop AP power-off on Puff & variants cr50 updatesEdward O'Callaghan
Fix Puff and its variants to not shutdown the AP before the cr50 reboot. This is the same approach that Sarien do to remain on during a cr50 cycle. BUG=b:154071064 BRANCH=none TEST=none Change-Id: I5f92b4f769654b67c10c91e4cc7b2bce785e302f Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42497 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22mb/google/hatch: Make puff and variants share common dptf.aslEdward O'Callaghan
Here we consolidate some of the dptf.asl duplication between Puff and it's variants. Customizations can be done later either as a direct copy or preferably via introducing a #define. BUG=b:154071868 BRANCH=none TEST=none Change-Id: I35fa1e152adb5f04fb6ef1bd2448376cf9f37980 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2020-06-22mb/google/hatch: Make puff and variants share common ec.hEdward O'Callaghan
Here we consolidate some of the ec.h duplication between Puff and it's variants. BUG=b:154071868 BRANCH=none TEST=none Change-Id: I13dfe09da5c7a19677b156063bb51a58bc059b93 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2020-06-21mb/protectli/vault_kbl: Enable Intel PTTMichał Żygowski
TEST=tweak PCR banks in SeaBIOS TPM menu, run tpm2_pcrlist in Linux Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I7c443a25ca7259df9c0a07615d0502f47d25792e Reviewed-on: https://review.coreboot.org/c/coreboot/+/42565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-21amd/mandolin: unbreak SeaBIOS VBIOS supportFelix Held
Commit 86ba0d73f34185533e5e2d4258aa3bf3dba40ed4 added VBIOS support for Raven2 silicon and changed the VBIOS file names to the format including the PCI device revision number. Upstream SeaBIOS expects the file to have only the PCI vendor and device IDs in the CBFS file name, so it doesn't find the VBIOS any more after that patch got applied. This patch adds the path and CBFS file name to include the Picasso VBIOS a second time under the CBFS file name SeaBIOS expects. This is a workaround and not a clean solution, but avoids breakage. It's separated from the rest of the Mandolin support, so it can just be reverted after a proper fix is implemented. https://chromium-review.googlesource.com/2015963/ in combination with a links file in CBFS might solve the issue for most of the cases, but it's not sure yet if for all, so a proper fix might require more than that. BUG=b:153675508 Change-Id: I4d9042615965b6a2d9255c194cf23368264ffe54 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42433 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-21mb/amd/mandolin: Add Picasso CRBFelix Held
Mandolin is the CRB for AMD Picasso and Dali. The mainboard code still needs a little cleanup and verification, but I'll do that in a follow-up to have a non Chromebook board using the Picasso SoC code in tree as soon as possible to be able to detect some possible breakage. BUG=b:130660285 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I2b4a78e1eef9f998e1986da1506201eb505822eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/33772 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-20mb/google/jecht: Correct hda_verb mic pin configsMatt DeVillier
Commit 0148fcb4 [Combine Broadwell Chromeboxes using variant board scheme] incorrectly flipped the mic pin configs for verb NIDs 0x18 and 0x19, so set them back to the correct values, which match the original Chromium sources (where the NID identifiers in the pin config comments were reversed, which was the source of the confusion originally. Test: build/boot guado variant, verify mic attached to 3.5mm jack functional Change-Id: I65b813c8f801303682762ce5a7446e07af117b9f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42518 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-20mb/google/beltino/**/hda_verb.c: Correct mic pin configsMatt DeVillier
Commit 0558d0c [mb/google/beltino/**/hda_verb.c: Correct pin configs] incorrectly flipped the mic pin configs for verb NIDs 0x18 and 0x19, so set them back to the correct values, which match the original Chromium sources (where the NID identifiers in the pin config comments were reversed, which was the source of the confusion originally. Test: build/boot panther and zako variants, verify mic attached to 3.5mm jack functional Change-Id: I172a0bb299049d113a0272ee9c790b25b6242cad Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42499 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-20mb/google/zork: rename fch_apic_routing struct to fch_irq_routingFelix Held
fch_apic_routing is used as name of an array that init_tables() populates with the APIC IRQ routing information. Also the fch_pirq array where fch_apic_routing was used as struct name contains the IRQ mapping for both PIC and APIC mode, so rename it to fch_irq_routing. Change-Id: Iba7a2416c6e07cde1b8618bdabf31b00e3ca4dd1 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-20mb/google/zork: remove redundant IRQ routing configurationFelix Held
The PIC and APIC IRQ routing tables are pre-populated with PIRQ_NC in init_tables(), so the fch_pirq table entries where both IRQ numbers are set to fch_pirq are redundant and can be removed. Change-Id: I0d9b4f25e12a66cf86d1ad541955c3d2fe336c5a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-19soc/amd: move acpi_wake_source.asl to common directoryFelix Held
Files are both identical and common for both SoCs. Change-Id: I54b78108d342a0fd03bf70ffe6a09695c5678eb4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42545 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-19mb/google/zork: Disable UART 1, 2 and 3Raul E Rangel
We don't use these on zork, so lets save the power. BUG=b:153001807 TEST=Boot OS and make sure UART 1, 2 and 3 are not probed and remain powered off. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I2fadeba779b66ec2fb13951b9487118ef0737a94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-19tigerlake: add unique acpi device ids for dptfSumeet R Pawnikar
Add unique new acpi device ids for dptf for Tiger Lake soc based platforms and update volteer speficic dsdt.asl file accordingly. The Linux kernel driver expects these new acpi device ids for dptf functionalities. BUG=None BRANCH=None TEST=Build and boot on volteer system Change-Id: I7dbb812c0fc0f5084c98cf2752ce7ddce8e4d50e Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-19Kconfig: Escape variable to accommodate new Kconfig versionsPatrick Georgi
Kconfig 4.17 started using the $(..) syntax for environment variable expansion while we want to keep expansion to the build system. Older Kconfig versions (like ours) simply drop the escapes, not changing the behavior. While we could let Kconfig expand some of the variables, that only splits the handling in two places, making debugging harder and potentially messing with reproducible builds (e.g. when paths end up in configs), so escape them all. Change-Id: Ibc4087fdd76089352bd8dd0edb1351ec79ea4faa Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-06-19mb/*/*/Kconfig: guard board name in quotesPatrick Georgi
New kconfig dislikes unquoted slashes. Change-Id: Ief242de081071021b9c904a24535d025f6674270 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42480 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-19mb/pcengines/apu2: Update GPIO Reads & writesMartin Roth
The APU2 was using the soc/amd/common functions to do GPIO reads and writes. The functions that were being used are getting eliminated in the SOC directory, but since the APU isn't using the rest of that code (as it's not using the rest of the SOC codebase), it proved to be problematic to use the updated functions. The solution I've put in place here is to pull everything needed for the GPIO reads & writes into the gpio_ftns.c & h files. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ied39c114bdf3637977d21f56fd7db428c52e4706 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-06-18mb/bap/ode_e21XX: Drop left over unmaintained ROMCC boardElyes HAOUAS
Remove unmaintained and unsupported old ROMCC board. This board wasn't hooked up for build. Change-Id: Idd907311dde187aa62d29a9d3943b6d5c08a1f71 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-06-18mb/google/dedede: Add support for 16 MiB flash map descriptorKarthikeyan Ramasubramanian
Upcoming variant boards will use 16 MiB SPI ROM. So add support for 16 MiB flash map descriptor. BUG=b:155107866,b:152981693 TEST=Build different variant boards. Ensure that waddledoo which is using 32 MiB SPI ROM boots. Cq-Depend: chrome-internal:3107306 Change-Id: I8a6868da3280a662ff3a30623804ff135e6cbfbc Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-18mb/google: remove cannonlake dptf.asl include file from dsdt filesSumeet R Pawnikar
Remove cannonlake dptf.asl include file from all the dsdt files as per soc/intel/common/acpi code changes for dptf. BUG=None BRANCH=None TEST=Build and boot on the system Change-Id: I961a3ecb27e7bb7bb0b98c8630900bada0531639 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-18mb/google/hatch: fix variants' selection of CHROMEOS_DSM_CALIBMatt DeVillier
CHROMEOS_DSM_CALIB requires/selects CHROMEOS, so only select if CHROMEOS already selected, otherwise building for non-ChromeOS targets fails. Test: build HELIOS for non-ChromeOS target (Tianocore payload) Change-Id: Ic0fd3b0a0efbc5a1f6896eb379569a55cb0f67f8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-18mb/google/volteer/variants/terrador: Disable EC SW syncDavid Wu
It is the reference board of TGL-Y platform, we want to disable EC SW sync for Proto stage, it would be re-enabled before EVT stage. BUG=b:156435028 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ie7999e24e9c173d4870b35ce1728f3dcc8dcac29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42090 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17mb/google/volteer: remove unused GPP_H23Nick Vaccaro
BUG=b:157567939 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer to kernel. Change-Id: I3046cf3a359e833a5d204f78ab84312e8665061f Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42411 Reviewed-by: Jes Klinke <jbk@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17mb/volteer: Set IomTypeCPortPadCfg default to 0x09000000Brandon Breitenstein
Temporary workaround for S0ix issues related to FSP's handling of 0 value. When IomTypeCPortPadCfg is 0 FSP completely skips any flow related to this value which seems to be causing issues with s0ix. This is still being debugged and a final solution will be made when available BUG=b:159151238 TEST=flash image with workaround to volteer and verify that s0ix cycles correctly. Change-Id: Id79dd1c49958389cdb666b3760abd821bc1973a8 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42268 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17soc/amd/picasso: rename PICASSO_UART Kconfig optionFelix Held
The PICASSO_UART Kconfig option is about using the internal MMIO UART controllers in Picasso for console, so rename it to PICASSO_CONSOLE_UART Change-Id: I38ac9ee96af826fe49307b4d0e055a43fcbd4334 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-17mb/google/hatch: mushu: Add F75303 temp sensor to dptfPuthikorn Voravootivat
Update the following in dptf.asl - Add support for TSR3 - Change TSR0/TSR1/TSR2/TSR3 From: Charger, 5V, GPU , None To: Charger, GPU, F75303_GPU, F75303_GPU_POWER - Adjust fan/cpu trip point accordingly - Fix formating in dptf.asl - Throttle charger when TSR0 (charger) is hot instead of throttle CPU BUG=b:158676970 BRANCH=None TEST=grep . /sys/class/thermal/thermal_zone5/{type,temp} /sys/class/thermal/thermal_zone5/type:TSR3 /sys/class/thermal/thermal_zone5/temp:50800 Change-Id: Iedbb6bc7c1e59a027119c70791b9bc8a4d83ff87 Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42270 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Bob Moragues <moragues@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17mb/google/puff: add MST and LSPCON details to variants devicetreeShiyu Sun
Added device hid info to the MST and LSPCON devices on kaisa, duffy and noibat. BRANCH=None BUG=b:156546414 TEST=None Signed-off-by: Shiyu Sun <sshiyu@chromium.org> Change-Id: I7b54512cd88e7280374c188315cabc2fba197f69 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-06-16mb/pcengines/apu2/mainboard.c: unify hexadecimal notation using capital lettersPiotr Kleinschmidt
mainboard_intr_data table mixed hexadecimal notation with both small and capital letters. Now, it is unified to capitals only. Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com> Change-Id: Icd8cf4324e72e87e7e98869872785523fb4e1809 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42388 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-16sb/amd/x/hudson: Replace hudson_enable_smi_generation()Kyösti Mälkki
Change-Id: I08b2d1af16c247e66bf1a352887b0f9387055225 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-15i945 boards: Factor out MAX_CPUSAngel Pons
At least one mobile 945 series northbridge supports 4 threads, because the dual-core Atom 330 CPU supports Hyper-threading. Therefore, we use that as the default for this chipset. Change-Id: I899ed1644d9b2da4fc72f09233a421200770110d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41845 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15gm45 boards: Factor out MAX_CPUSAngel Pons
The gm45 northbridge supports at most 4 threads. However, the only two mobile Core 2 Quad models are not BGA956, so account for that as well. Change-Id: Ie198ac4c366ec0bd53ddb337b6f9c03c331c73f5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-15pineview boards: Factor out MAX_CPUSAngel Pons
Pineview has at most 4 threads. Change-Id: I0f45f002d0bab0345bc061ac3c7a29237a536cc5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41843 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15haswell boards: Factor out MAX_CPUSAngel Pons
ULT only has 4 threads, but we are not changing it here to preserve binary reproducibility. Change-Id: I041c5dff2de514244f9c919c4c475cca979c34ce Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41842 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15x4x boards: Factor out MAX_CPUSAngel Pons
LGA775 CPUs can have at most 4 threads, and Eaglelake supports them. As this socket is also used by other chipsets, temporarily place this symbol into the northbridge scope until all chipsets are factored out. Change-Id: I6e01363d995e135815cc70779e0cd5baf806cf60 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-15arrandale boards: Factor out MAX_CPUSAngel Pons
Arrandale CPUs have at most 4 threads. Change-Id: Ifecbf5583011ff5e36c576d582a6276bc9b72803 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41840 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15sandybridge boards: Factor out MAX_CPUSAngel Pons
Also update autoport accordingly. Change-Id: I12481363cf0e7afc54e2e339504f70632e8d72e2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41839 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14mb/google/volteer: Disable HDA PCI device when AUDIO=NONEDuncan Laurie
If there is no installed audio daughter board on volteer then the HDA driver in the kernel will crash on resume. In order to prevent this disable the PCI device when AUDIO=NONE probe match is true. BUG=b:147462631 TEST=boot on volteer and ensure that the PCI device at 0:1f.3 is gone Change-Id: I4a436e1b76418030bf635427e490b54a713fdd33 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-14mb/google/zork: Drop OEM_BIN configsFurquan Shaikh
Zork family does not use OEM binary and so this change drops the configs required for adding this binary. Change-Id: Id38c67030e4055ab16934d1a900ee1cea5843b54 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-14mb/google/zork: Enable ELOG optionsFurquan Shaikh
This change enables following ELOG options for zork family: ELOG ELOG_BOOT_COUNT ELOG_GSMI ELOG_BOOT_COUNT_CMOS_OFFSET BUG=b:158875638 TEST=Verified that kernel reports GSMI loading correctly: [ 5.308982] gsmi version 1.0 loaded Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I4f34a814e744e863f1fbfc19e37209cb7febbdcc Reviewed-on: https://review.coreboot.org/c/coreboot/+/42332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-14mb/google/volteer/var/terrador: Update dq/dqs mappingsDavid Wu
Update dq/dqs mappings based on terrador schematics. BUG=b:156435028,b:151978872 BRANCH=none TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I97697a3dd9b88eaffe6e2b1be7bd346979cbc956 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-14mb/google/volteer: Enable thermal sensor 4 in DPTF for volteerDeepika Punyamurtula
Enables the fourth thermal sensor for fan in DPTF for volteer BRANCH=None BUG=b:149722146 TEST= On volteer system check `cat /sys/class/thermal/thermal_zone5/type` for TSR3 Signed-off-by: Deepika Punyamurtula <deepika.punyamurtula@intel.com> Change-Id: Ie11496828133aa71f1017f759516e2e5d3dff2d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-06-14mb/google/puff: add MST and LSPCON details to devicetreeShiyu Sun
Added device hid info to the MST and LSPCON devices. BRANCH=None BUG=b:156546414 TEST=Manual tested and able to see update on sysfs and ssdt table Signed-off-by: Shiyu Sun <sshiyu@chromium.org> Change-Id: Iaef6c08f241ea671d1487a8524162dbb438b8e98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-14mb/google/hatch/vr/puff: Set up PL2 and PsysPL2Tim Chen
This patch adds correct PL2 baseline setting and PsysPL2 for different SKUs. There is no way to identify the barral jack power rating, the assumption is following that ships with the product: 1. i3/i5/i7: 90W BJ 2. Celeron/Pentium: 65W BJ For Type-C adapter, we don't have Pcritcial (10ms) data, keeps the original settings as 90% of adapter rating for PsyspL2/PL4 and PL2 as min(PL2, 0.9n) where n is adapter rating power. BUG=b:143246320 TEST=Run with U62 and Celeron CPU and ensure the PL2 settings are correct Change-Id: Ib16d4f65707801b430f06892ab45ecfa7551593f Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-06-14mb/google/fizz: add variant chipset display initJeff Chase
The Endeavour variant does not have a DisplayPort input so there's no need to wait for it. BUG=b:147830399 BRANCH=none TEST=boot endeavour; check coreboot logs Signed-off-by: Jeff Chase <jnchase@google.com> Change-Id: I30c7c47f19a61ce66c6c923864d80870d2761859 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2020-06-14mb/google/dedede: Enable early EC software syncMeera Ravindranath
BUG=none BRANCH=none TEST=Verify sysjump from EC console, EC sync in romstage in AP console and crossystem reflect ecfw_act as RW Change-Id: Ief96fe481c94acef3754881cf1f453699fbfa52e Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41396 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14mb/google/dedede: Select Recovery Cache Kconfig optionMeera Ravindranath
BUG=none BRANCH=none TEST=Boot WaddleDoo in recovery and populate the recovery MRC cache. The subsequent recovery boot should boot out of the stored recovery MRC cache and skip memory training. Change-Id: Ief86fe481c94abef3754881cf1f454699fbfa52e Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41162 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14mb/google/hatch: Switch USB2 port1 and port3 on NoibatEdward O'Callaghan
Switch USB2 port1 and port3 for noibat due to circuit change. BUG=b:154585046,b:156429564 BRANCH=none TEST=none Change-Id: I711038624f3efe397be73c29a940b3e17802598f Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42296 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-13treewide: Add Kconfig variable MEMLAYOUT_LD_FILEFurquan Shaikh
This change defines a Kconfig variable MEMLAYOUT_LD_FILE which allows SoC/mainboard to provide a linker file for the platform. x86 already provides a default memlayout.ld under src/arch/x86. With this new Kconfig variable, it is possible for the SoC/mainboard code for x86 to provide a custom linker file as well. Makefile.inc is updated for all architectures to use this new Kconfig variable instead of assuming memlayout.ld files under a certain path. All non-x86 boards used memlayout.ld under mainboard directory. However, a lot of these boards were simply including the memlayout from SoC. So, this change also updates these mainboards and SoCs to define the Kconfig as required. BUG=b:155322763 TEST=Verified that abuild with --timeless option results in the same coreboot.rom image for all boards. Change-Id: I6a7f96643ed0519c93967ea2c3bcd881a5d6a4d6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42292 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-13mb/google/zork: update DRAM SPD table for vilbozPaul Ma
Add DRAM support for vilboz: Hynix H5AN8G6NCJR-VKC # 0b0000 Hynix H5ANAG6NCMR-VKC # 0b0001 Samsung K4A8G165WC-BCWE # 0b0010 Hynix H5AN8G6NDJR-XNC # 0b0011 Micron MT40A512M16TB-062E-J # 0b0100 Samsung K4AAG165WA-BCWE # 0b0101 Micron MT40A1G16KD-062E-E # 0b0110 BUG=b:157523051 BRANCH=none TEST=build Change-Id: I251fd9cc7bc51bfdeaa577f7034da750e684dc99 Signed-off-by: Paul Ma <magf@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-12mb/google/volteer/var/voxel: Add memory parts and generate DRAM IDsFurquan Shaikh
This change adds memory parts used by variant voxel to mem_list_variant.txt and generates DRAM IDs allocated to these parts. This variant is not yet supported by coreboot but DRAM IDs need to be generated for it. In the coming days, variant voxel will be added to coreboot. BUG=b:157732528 Change-Id: I8780beec987deb8fed11bb8f84275dcba4768514 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-06-12mb/google/volteer: Customize PCH VR settings for better Sx power savingsVenkata Krishna Nimmagadda
For Volteer mainboard, this patch set optimized values for PCH external VR settings and ext rail voltage/current, to achieve better power savings in sleep states. v1p05 and vnn power rails can be used as an alternative source by-passing vccin_aux during Sx. This by-pass feature, enables us to shutdown vccin_aux rail which is higher voltage rail compared to v1p05 and vnn. These both rails were disabled by default in FSP. Changes in this patch are: 1. v1p05 and vnn rails are enabled and enabled supported voltage types in S0i1, S0i2, S0i3, S3, S4, S5 states. They were disabled by default. 2. Icc Max for v1p05 changed to 500 mA from default 100 mA. 3. vnn rail's voltage is changed to 5 V from default 4.2 V. BUG=None BRANCH=None TEST="Build and boot volteer and check VR settings with Intel ITP-XDP debugger and verify approx 250 mW power savings in Sx" Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com> Change-Id: Ib46423872c956af9aaa92902fce552d5447237c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42223 Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-12mb/google/dedede: Add new variant botenPeichao Wang
Add initial support for boten variant board. BUG=b:158023819 BRANCH=None TEST=build Change-Id: I56fe901c6aec781fac217ab08f7583cc25788688 Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Marco Chen <marcochen@google.com>
2020-06-12mb/google/hatch: Remove unused USB2 port from NoibatEdward O'Callaghan
This port isn't packed on the board, so remove from the devicetree. BUG=b:154585046,b:156429564 BRANCH=none TEST=none Change-Id: Ib4aee337f67453adcebff7e93e25db7a838e3b2d Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42269 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-12mb/google/puff: Update i2c[2] and i2c[3] rise and fall timesSam McNally
BRANCH=none BUG=b:158713330 TEST=Flashing the LSPCON firmware works Change-Id: Ib371f6954115145047c70cfd25262026cce087fd Signed-off-by: Sam McNally <sammc@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-06-11vc/amd/fsp/platform_descriptors: drop prefix from PCIe/DDI structsFelix Held
The picasso_ prefix on the fsp_pcie_descriptor and fsp_ddi_descriptor structs isn't needed, since this code is picasso-specific, so drop it. Change-Id: Ia6a0ddb411aa64becc3c23a876f2ea43cb68e028 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42252 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-11mb/google/dedede: Add new variant drawciaWisley Chen
Add initial support for drawcia BUG=b:158540280 BRANCH=None TEST=build Change-Id: Ic775bb2a93581e422379ca90127e3581bbf3c89e Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Marco Chen <marcochen@google.com>
2020-06-11mb/google/volteer: Update DPTF TSR2 sensor ID for volteerDeepika Punyamurtula
Update DPTF_TSR2_SENSOR_ID to 2. Fixes the issue where TSR1 and TSR2 have the same DPTF_TSR#_SENSOR_ID value causing them to report the same temperature under /sys/class/thermal and also swap TSR0 and TSR1 in DTRT to match physical sensor in volteer schematics BRANCH=None BUG=b:149722146 TEST=On volteer system check TSR1 and TSR2 temperatures, should report different values `cat /sys/class/thermal/thermal_zone[3,4]/temp` Also verify other TSRs using `cat /sys/class/thermal/thermal_zone*/temp` and `ectool tempsinfo all ; ectool temps all` Signed-off-by: Deepika Punyamurtula <deepika.punyamurtula@intel.com> Change-Id: Idc5f35e4faf59b0ee726eb32a08eab4654fb342d Reviewed-on: https://review.coreboot.org/c/coreboot/+/42232 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 03:21:49 +0000