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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2020-06-19 17:15:51 +0200 |
|---|---|---|
| committer | Michał Żygowski <michal.zygowski@3mdeb.com> | 2020-06-21 17:02:58 +0000 |
| commit | 7896b8ce59f88d7cd65bf7c9dfc3f9b1f9f2c640 (patch) | |
| tree | ca2d75027e4857be97ab3d0087660215c47cfba6 /src/mainboard | |
| parent | 08e8cab57841cd1e2cc47bb9899b16a531e1a1f5 (diff) | |
mb/protectli/vault_kbl: Enable Intel PTT
TEST=tweak PCR banks in SeaBIOS TPM menu, run tpm2_pcrlist in Linux
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I7c443a25ca7259df9c0a07615d0502f47d25792e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/protectli/vault_kbl/Kconfig | 3 | ||||
| -rw-r--r-- | src/mainboard/protectli/vault_kbl/devicetree.cb | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/protectli/vault_kbl/Kconfig b/src/mainboard/protectli/vault_kbl/Kconfig index 8c09a60b6e..518bb6dca5 100644 --- a/src/mainboard/protectli/vault_kbl/Kconfig +++ b/src/mainboard/protectli/vault_kbl/Kconfig @@ -11,6 +11,9 @@ config BOARD_SPECIFIC_OPTIONS select SOC_INTEL_KABYLAKE select SPI_FLASH_MACRONIX select SUPERIO_ITE_IT8772F + select MAINBOARD_HAS_CRB_TPM + select HAVE_INTEL_PTT + select TPM2 config IRQ_SLOT_COUNT int diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index d3e8b2305c..bb408a4351 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -305,4 +305,7 @@ chip soc/intel/skylake device pci 1f.5 off end # PCH SPI device pci 1f.6 off end # GbE end + chip drivers/crb + device mmio 0xfed40000 on end + end end |