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Turn off GPP_H13 (EN_PP3300_SD_X) in s0ix for power saving. It reduces
about 3mW of power consumption in s0ix on pirrha proto board.
BUG=b:300845527
TEST=Built and verified GPP_H13 voltage was 0V in s0ix.
Also verified SD card worked after s0ix for 20 times.
Change-Id: I5ec53820276e50f5b8b01584595118cf2dc4c95c
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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This patch reverses ISH UART pin configuration to allow ISH to enter
into suspend mode. This UART port is for debugging purposes.
BUG=b:302612549
TEST=On Google/rex platform with ISH enabled, do suspend_stress_test
This test must pass
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I8aba45420744a3990e1f9637c3b31ea2e0f78f87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78049
Reviewed-by: Tanu Malhotra <tanu.malhotra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Set USB port which corresponds PORTSCN/PORTSCXUSB3 register bits for
enable USB wake.
BUG=b:302230434
TEST=Verify USB-A device could wake up Boxy
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I0f6300dc6bbb6fb8226151e49e38f0450b1e71b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78144
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set USB port which corresponds PORTSCN/PORTSCXUSB3 register bits for enable USB wake.
The physical USB slot is 6, USB2 port5 for Bluetooth, total USB2 port num is 7, USB3 keep 6.
BUG=b:300844110
TEST=Verify USB-A device could wake up Taranza
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Ied92c4a70bc594bd189dcb942f1a445412509464
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78068
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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This panel is never actually enabled on Geralt. The derived project
won't use this panel either. Therefore, remove this panel support.
BUG=none
BRANCH=none
TEST=emerge-geralt coreboot
Change-Id: I97ed5b341724ed42098b2c17d0eb75eab881dbb1
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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The tolerance of ADC voltage table is too small. Update the table values
accordring to the suggestion from the hardware team. The patch is
prepared for the derived projects. There is no actual issue now.
BRANCH=none
BUG=b:301908091
TEST=check firmware screen
Change-Id: I3bde30b6bbe79c81e276f23f4110715c3278d42c
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Add VCM power control to configure 2.8V and reset pin, and VCM can
be powered on/off properly.
BUG=b:292907385
TEST=Run ITS test
Change-Id: I242025836fd50076a40ffcc4e5d4a5d5bc6fb4d0
Signed-off-by: Serin Yeh <serin.yeh@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78170
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Certain devices are enabled in Alder Lakes chipset.cb, so remove
them from the devicetree.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I929af0bed6c2e1024b4787424a8fe466edce5a36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78198
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I1b0052b569b575fec7893322dec0280c9f1ed79f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78197
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Updating FSP to v4301.01 caused a strange flicker when connecting
an external display. Update the VBT to 251 from 242 with the exact
same settings to resolve this.
Change-Id: I36bb2cc92e744e761ec6af9c026c429373c1750a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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The SPL_TABLE_FILE and SPL_RW_AB_TABLE_FILE Kconfig options provide a
way to override the default SPL file configured in the SoC's fw.cfg file
by passing the '--spl-table' parameter to amdfwtool which will then use
the override instead of the SPL file from the fw.cfg file. When
SPL*_TABLE_FILE is an empty string, the corresponding add_opt_prefix
call in the makefile will result in no '--spl-table' parameter being
passed to amdfwtool, so it'll use the default SPL file from fw.cfg. In
order to not pass an SPL override by default, remove the default from
the SPL_TABLE_FILE in the SoC's Kconfig. The SoC default pointed to the
same SPL file as in fw.cfg file anyway. Now only when a mainboard sets
this option to point to a file, that file will be used as an override.
This override is used to include a special SPL file needed for the
verstage on PSP case on the Chromebooks. Since SPL_TABLE_FILE is an
empty string by default, neither the SPL_TABLE_FILE Kconfig option nor
it being evaluated in the Makefile need to be guarded by HAVE_SPL_FILE,
so remove the dependency in the Kconfig and the ifeq in the Makefile.
Before this patch, the HAVE_SPL_FILE option controlled two things that
shouldn't be controlled by the same Kconfig option: Only when
HAVE_SPL_FILE was set to y, the SPL_TABLE_FILE override was taken into
account, and it also controls if spl_fuse.c got added to the build which
when added will send the SPL fusing command to the PSP. So the case of
needing an SPL file override, but not updating the SPL fuses wasn't
supported before.
The SPL file in the amdfw part will be used by the PSP bootloader for
the anti-rollback feature which makes sure that the SPL file version
isn't lower than what is in the SPL fuses. For this the SPL file needs
to be present in the PSP directory table. The SPL version check happens
way before we're running code on the x86 cores. The SPL fusing PSP
command that can be sent by coreboot will tell the PSP to update the SPL
fuses so that the fused minimal SPL version will be updated to the
current SPL version.
Since the former HAVE_SPL_FILE option now only controls if the SPL
fusing command will be sent to the PSP mailbox, rename it to
PERFORM_SPL_FUSING to clarify what this will do and update the help text
correctly describe what this does.
TEST=With INCLUDE_CONFIG_FILE set to n, timeless builds for both Birman
with Phoenix APU and Skyrim result in identical binaries.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6cec1f1b285fe48e81a961414fbc9978fa1003cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78178
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add probe fw_config to USB C1/A0 port on daught_board for DB_1A sku.
BUG=b:294456574
TEST=emerge-nissa coreboot
Change-Id: I2261b0e4d2b673b6186a435cce8dc6a4ccacb0a7
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: I1439f785cb9ceeefab9d24caa88e35bd43f68315
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: I5ff9170ac6a3f50830a707dacf4f941587e531ef
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75076
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: Iface0fd1d44649c6d9773940818e028e3d3a4292
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: I5a321680b1b84ca0b2598d2446ff10257947a733
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: I80bd87aa2f97da74a1bbcf05b16f0d5980e142f2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: I6b71c7c5c9e32e21c757c0ed0e9c6bd9d58a4f75
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78131
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: I6a78efa4be2ee34e7dac06a8b8014da12b21fbdc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: I817faab0438a35d2e8859342e7c2b2dbaa0afeeb
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78129
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: Iec0829ba80d3d4b4bc79e14a97d085930c4c5202
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78128
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: If6b666478e15a8e843b50b60be490593349240bd
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: I5527d5968be35f52b912d9d6e1d9f46f24569bbc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: Ic199a60013ceedfd15b191a5fe707be6654ad3a2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75078
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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During suspend, the ISH I2C transactions cannot go through
because the GPIO pads remain the pervious value.
The IO Standby State (IOSSTATE) needs to be changed to keep I2C bus
active and functional during suspend.
BUG=b:302612549
TEST=on Google/rex platform with ISH enabled, do suspend_stress_test
and check that no i2c failure.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I9a2c902ed56461f3a535428db399c2050756f2da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78179
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Li1 Feng <li1.feng@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set default to enabled for hibernate on setup failure for all devices
using a Google EC. This will have no impact on devices that don't
bring the GSC down on hibernate, but will provide a recovery path
for all devices that do.
BUG=b:296439237
TEST=Force error on Skyrim with custom build, boot normally with
normal build
Change-Id: I2d9e8f75b25fb6c530a333024c342bea871eb85d
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78098
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BOARD_SPECIFIC_OPTIONS is duplicate to BOARD_GOOGLE_CORSOLA_COMMON.
Thus, move all selects to the latter option.
Change-Id: I498c6671b2dfc72820fc522744af7ce3b0a62930
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Yidi Lin <yidilin@google.com>
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ASPM on the WLAN PCIe bus introduces large latency spikes, which can be
measured with cyclictest:
$ cyclictest --policy=rr --priority=12 --interval=10000 --threads=1 --loops=6000
Disabling ASPM for WLAN reduces the latency spikes from 2,500-3,000 usec
down to 35-65 usec. These latency spikes can impact the user when
real-time processes like Audio (cras) are starved of CPU time, leading
to buffer underruns resulting in crackling/distorted audio.
ASPM is already disabled for Nipperkin devices (CB:63537), so this CL
disables it for both in the shared declaration of
guybrush_czn_dxio_descriptors.
Power impact for Dewatt:
* ASPM enabled
power_VideoCall.FDO_25min_webrtc
w_energy_rate 7.425043688811071
power_Idle.default20min
wh_energy_used 1.4164200000000022
* ASPM disabled
power_VideoCall.FDO_25min_webrtc
w_energy_rate 8.779998551703423
power_Idle.default20min
wh_energy_used 1.4860800000000012
When using Google Meet over WiFi, power increases by ~1.5W.
BUG=b:297970318
TEST=cyclictest --policy=rr --priority=12 --interval=10000 --threads=1 --loops=6000
Change-Id: I16940987d598943bd5d6ace8b4008eba4d4a177c
Signed-off-by: Tim Van Patten <timvp@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77963
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Implement support for elan i2c touchscreen and use fw_config
to pick between i2c or HID-over-i2c touchscreen.
Support G2 TS have different slave address by fw_config
BUG=b:295272539
BRANCH=firmware-nissa-15217.B
TEST=build and verified touchscreen work
Change-Id: I5e3f85106606d84e1cfa204e62b7b2662db6546b
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
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Change-Id: I28a90c236e17d1ea15f5416fab8be7360494e92e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Enable hibernate on TPM setup error for Skyrim devices.
BUG=b:296439237
TEST=Force the error by hard coding the return code and observe the
device entering hibernate.
BRANCH=None
Change-Id: Ibf96b830f07dac98035d3152c8ec220685a912bc
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77668
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Convert TPM functions to return TPM error codes(referred to as
tpm_result_t) values to match the TCG standard.
BUG=b:296439237
TEST=build and boot to Skyrim
BRANCH=None
Change-Id: Ifdf9ff6c2a1f9b938dbb04d245799391115eb6b1
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77666
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Convert hex print values to use the %#x qualifier to print 0x{value}.
BUG=b:296439237
TEST=build and boot to Skyrim
BRANCH=None
Change-Id: I0d1ac4b920530635fb758c5165a6a99c11b414c8
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78183
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ifb4d7dda5fcf1ccacb901b24e4f7cf6945ee16e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76503
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TESTED: AMD onyx reaches x86 code
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Change-Id: I95d84f93663a80f322fd4d7cdeb35ccfe0ec7d21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76498
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure PL1 and PL2 are configured for powerformance.
Based on values from Intel Meteor Lake UH Power Map document ID:640982
BUG=b:286834207
TEST=Build and boot google/ovis and check ACPI SSDT for DPTF entries
Change-Id: Ia40884b3abd1417dea6ad291de4845762ee01966
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77623
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Modify the settings:
1)Add fw_config probe on USB type C for "DB_1C_LTE".
2)Add fw_config probe on USB type A for "DB_1A_HDMI".
BUG=b:296791122
TEST=build and check USB functions on craask
Change-Id: I2775098ab380995e62f264bc51a430762c256c4b
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78169
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Rather than disabling C State demotions for every single Raptor
Lake board due to an issue with S0ix, regardless of if they even
use S0ix, configure it in the mainboard.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I4f941a549bc717ae2f8ec961ead7ac7668347c99
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Configure the rcomp, dqs and dq tables based on the schematic.
BUG=b:298337185
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=dochi emerge-brya coreboot
Change-Id: I182e287423e6f784712c5004a6fe2d12a5b36190
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
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Add PLx from JSL PDG (ID: 613095) in taranza devicetree.
Add ramstage.c in Makefile.inc and update Taranza power limits in
taranza ramstage.c.
BUG=b:296004956
TEST=emerge-dedede coreboot and check psys and PLx value on taranza
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Id43bb91bc9efb91cb074b075122cce4f22e0716c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Configure I2C5 timing in devicetree to ensure I2C devices
meet timing requirement.
BUG=b:300177424
TEST=Build and check I2C devices timing meet spec.
| | I2C5-Before | I2C5-After |
|-------------|-------------|------------|
| FSMB(KHz) | 445.400 | 343.638 |
| TLOW(us) | 1.543 | 2.068 |
| THIGH(us) | 0.475 | 0.604 |
| THD:STA(us) | 0.603 | 0.711 |
| TSU:STA(us) | 0.612 | 0.611 |
| TSU:STO(us) | 0.605 | 0.611 |
| TBUF(us) | >1.914 | >2.044 |
Change-Id: I3bb678b66d55c6bfaff76e3e5500a2a3bc3a2c61
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78111
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Add 4th sensor device for DTT tuning.
BUG=b:292134655
TEST=Built and verified DTT tool could monitor the new sensor device
Change-Id: I62f50711af81dfc1566d655f6dcfc66f68dbc794
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
|
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: I8530bb9b89a12ae831a4716bdec8c66c7f3f74a4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: I73844dc4686dd014ec2209e296cc4aff47280e9f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
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BOARD_SPECIFIC_OPTIONS is duplicate to BOARD_GOOGLE_OAK_COMMON.
Thus, move all selects to the latter option.
Change-Id: Id80b8a9bcad9337c8aa76fa6e5d2c9752b8021b7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
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BOARD_SPECIFIC_OPTIONS is duplicate to BOARD_GOOGLE_BASEBOARD_GUYBRUSH.
Thus, move all selects to the latter option.
Change-Id: I570c3cfd3d100ad90e35ec5d89686cb6a4bd8e82
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
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Facilitates correct profile selection by SOF Windows drivers.
Profiles for nokris and quandiso will be added once correct board
configs can be determined.
TEST=build/boot Win11 on google/craask, verify correct audio profiles
loaded, audio functional.
Change-Id: Id4582b5dd74a4905ea509813ec99663577360095
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
|
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This adds support for booting the Librem L1UM v2 mainboard with
coreboot, using binaries from the original BIOS.
The following features have been tested on PureOS:
- USB: front USB3, rear USB3, USB2 header on board
- SATA: 8x SATA ports, one M.2 M-key shared with SATA0
- PCIe: two PEG slots, one PCIe slot from PCH, and one M.2 M-key
- Network: 2x GbE
- Video: BMC VGA and IPMI
- Serial: Physical serial port, provided by BMC SuperIO
- Hardware monitor
- POST code display
- TPM2
These binaries are extracted from the original BIOS:
- Intel Management Engine
- Intel Firmware Descriptor
This was developed and tested on a Librem L1UM v2 using a Core i7-9700
CPU. Native graphics init works for the Aspeed AST2500 BMC.
For development, the serial port console works from bootblock. Early
init waits for the BMC to finish booting since this is required for
serial port output.
Change-Id: I990f6024d65098a9553d7d1fe7f36614cc55ea19
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75090
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Add Makefile.inc to include five generic LPDDR5 SPDs for the following
parts for Dochi:
DRAM Part Name ID to assign
MT62F1G32D2DS-023 WT:B 0 (0000)
K3KL8L80CM-MGCT 1 (0001)
H58G56BK8BX068 0 (0000)
BUG=b:298337185
TEST=USE="project_dochi emerge-brya coreboot"
Change-Id: If0fd4bc950cef484db53b7b21849cfdfdd7816a5
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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Instead of selecting board-specific options under the common option and
making them conditional, move them to their related board option.
Change-Id: If9bea61cb84590e7455add908fa7722c60444503
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
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The tolerance of LCM voltage table is too small which leads to wrong
panel ID detection. Fine tune LCM ADC voltages based on hardware
calculations.
BUG=b:300418909
TEST=FW screen display normally
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: Id8dec043584f4c552837f70adb491584bfda7acf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
|
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Adopt TCG standard naming and definitions for TPM Return codes.
BUG=b:296439237
TEST=Build and boot to OS on skyrim
BRANCH=None
Change-Id: I60755723262ec205a4c134948b0250aac4974d35
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77665
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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BOARD_SPECIFIC_OPTIONS is duplicate to BOARD_GOOGLE_CHERRY_COMMON.
Thus, move all selects to the latter option.
Change-Id: I080201761d0a06d3b8a5a29de6085dde58960a60
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75085
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BOARD_SPECIFIC_OPTIONS is duplicate to BOARD_GOOGLE_ASURADA_COMMON.
Thus, move all selects to the latter option.
Change-Id: Id80523dce70f13f64a49b71656276c51e80ae5cd
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75084
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: Id69ea99b452e4214fcc81335a5c961b4da3ce48b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: Id85503a5ec970ea92c07b99ec7048c521d85c79b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75026
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: Id450a4b6e409a548ee4d79b8b2ebf30ef61a3e27
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78083
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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No Windows driver exists or is needed, so hide to prevent an unknown
device from being listed in Windows Device Manager.
TEST=build/boot Win11 on frostflow, verify unknown device for the
fingerprint reader no longer present.
Change-Id: I666e92706f698608f2df92c8296cfb615d5ece67
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
No Windows driver exists or is needed, so hide to prevent an unknown
device from being listed in Windows Device Manager.
TEST=build/boot Win11 on dewatt, verify unknown device for the ACP
machine driver no longer present.
Change-Id: I44d25fd2ea75593383cbb14f2324d4376b399de7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
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No Windows driver exists or is needed, so hide to prevent an unknown
device from being listed in Windows Device Manager.
TEST=build/boot Win11 on morphius, verify unknown device for the ACP
machine driver no longer present.
Change-Id: I14347ab6c840066db4ff700eff1aad4cf6faf66b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
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1. Support world facing usb camera on usb2_port7.
2. Update MB/DB fw_config to distinguish LTE and non-LTE devices.
BUG=b:296506936
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I0c508475fdc86f0d7357f19684bdaae06e77fc27
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77398
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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- GPIO changes:
GPP_B5 ==> I2C_P_SENSOR_SDA
GPP_B6 ==> I2C_P_SENSOR_SCL
GPP_H19 ==> P_SENSOR_INT_L
- I2C SX9324 support
- Disable GPIOs when sub board LTE not used
BUG=b:296506936
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I5ed82b125b6c594225efca418017ef42f4f63b9d
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
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GPIO changes
- GPP_D8 ==> SD_CLKREQ_ODL
- GPP_D17 ==> SD_WAKE_N
- GPP_H12 ==> SD_PERST_L
- GPP_H13 ==> EN_PP3300_SD_X
Genesys Logic GL9750 support
BUG=b:296506936
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: Ib7c80f43680481c0d1a18662fa494012390a984d
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77391
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Quandiso doesn't support mipi WCAM.
BUG=b:296506936
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I8a166d0bb1c034f2e3a5af7456500abd078e93f9
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77389
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update files copied from yavilla
- fw_config setting
- GPIO setting
- Kconfig setting
- overridetree setting
- SPD memory parts
- variant setting
BUG=b:296506936
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
flash bin file in DUT
Change-Id: Ibbef42a1f891d0cf0309aa76edd7ec5dd664588e
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77361
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Dedede boards which select AUDIO_AMP_UNPROVISIONED via fw_config use
rt1015 for the speaker topology, not max98360a.
TEST=build/boot Win11 on google/magpie, verify correct audio profile
selected.
Change-Id: I5b75bd8fd37d2837de3c5bd25a02411a6982103b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
|
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Add data.vbt file and Kconfig to use it.
Extracted from google firmware genesis_13324.283.0
TEST=build genesis with FSP GOP display init
Change-Id: If836b214da1350111d7b7d1f24865199f814c521
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
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Add data.vbt file and Kconfig to use it.
Extracted from google firmware ambassador_13324.283.0
TEST=build ambassador with FSP GOP display init.
Change-Id: I5c47700c5abe7d96112702d48a2b749f1784a494
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78032
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Without the PCH UART GPIOs set early, there is no serial console
output until ramstage. Add them to the early GPIOs for all puff
variants.
TEST=build/boot google/puff (wyvern) with serial console enabled,
verify console output starts in bootblock.
Change-Id: Ica0506b2b80e4fac0d3ca11b4cfdd128ce424b36
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78029
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Brya queries the TPM in early ramstage (pre-device init) to determine
if the CR50 has support for long-pulse interrupts. If the TPM (and
underlying I2C controller) hasn't already been setup in verstage, it
will fail to do so in ramstage since the I2C controller has not yet
been initialized. To work around this, initialize the TPM in bootblock
for the non-vboot case, to ensure the I2C controller is set up when
needed in early ramstage.
TEST=build/boot google/brya (banshee), verify no I2C errors in cbmem
console when initializing TPM in early ramstage.
Change-Id: I26f0711a9cc4c2eb9837f258cadf391d337994c9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78028
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds ACPI entries for SAR Proximity Sensors as below
SAR1 Sensor:
- SAR1_INT_L : GPP_E00
- I2C5 7-bit address 0x28
SAR2 Sensor:
- SAR2_INT_L : GPP_E08
- I2C 7-bit address 0x2c
BUG=b:297977526
TEST=Able to build and boot google/rex.
w/o this patch:
Total 6 devices are listed below:
> ls -lt /sys/bus/iio/devices/iio:device*
/sys/bus/iio/devices/iio:device5 -> ../../../devices/LNXSYSTM:00/
LNXSYBUS:00/PNP0A08:00/device:07/
/sys/bus/iio/devices/iio:device0 -> ../../../devices/pci0000:00/
0000:00:1f.0/PNP0C09:00/GOOG0004:0
/sys/bus/iio/devices/iio:device2 -> ../../../devices/pci0000:00/
0000:00:1f.0/PNP0C09:00/GOOG0004:0
/sys/bus/iio/devices/iio:device4 -> ../../../devices/pci0000:00/
0000:00:1f.0/PNP0C09:00/GOOG0004:0
/sys/bus/iio/devices/iio:device1 -> ../../../devices/pci0000:00/
0000:00:1f.0/PNP0C09:00/GOOG0004:0
/sys/bus/iio/devices/iio:device3 -> ../../../devices/pci0000:00/
0000:00:1f.0/PNP0C09:00/GOOG0004:0
w/ this patch:
Total 8 devices are listed below:
> ls -lt /sys/bus/iio/devices/iio:device*
/sys/bus/iio/devices/iio:device6 -> ../../../devices/pci0000:00/
0000:00:19.1/i2c_designware.4/i2c-
/sys/bus/iio/devices/iio:device5 -> ../../../devices/LNXSYSTM:00/
LNXSYBUS:00/PNP0A08:00/device:07/
/sys/bus/iio/devices/iio:device7 -> ../../../devices/pci0000:00/
0000:00:19.1/i2c_designware.4/i2c-
/sys/bus/iio/devices/iio:device0 -> ../../../devices/pci0000:00/
0000:00:1f.0/PNP0C09:00/GOOG0004:0
/sys/bus/iio/devices/iio:device2 -> ../../../devices/pci0000:00/
0000:00:1f.0/PNP0C09:00/GOOG0004:0
/sys/bus/iio/devices/iio:device4 -> ../../../devices/pci0000:00/
0000:00:1f.0/PNP0C09:00/GOOG0004:0
/sys/bus/iio/devices/iio:device1 -> ../../../devices/pci0000:00/
0000:00:1f.0/PNP0C09:00/GOOG0004:0
/sys/bus/iio/devices/iio:device3 -> ../../../devices/pci0000:00/
0000:00:1f.0/PNP0C09:00/GOOG0004:0
Change-Id: I0a518d58915f9f4dbe58a45c4dc5875abbfda135
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78045
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
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Intel Meteor Lake QS silicon provides better size optimized pre-x86
reset blobs.
This patch creates a new flash layout (FMD) for QS to accommodate those
optimizations, and renames the existing FMD for ES (pre-prod) silicon.
Comparative analysis between QS and ES flash layout is here:
For QS silicon:
- SI_ALL reduced from 9MB to 8MB.
- SI_BIOS increased by 1MB (from 23MB to 24MB) to fill in the 32MB SPI
layout.
- ME_RW_A/B reduce from ~4.5MB to 4MB.
- Ensure RW-B slot is starting at 16MB boundary.
- Unused space increased by 1MB.
For ES silicon:
- SI_ALL: 9MB
- SI_BIOS: 23MB
- ME_RWA/B: 4.5MB (for ISH) and 4.4MB (non-ISH).
- Unused space 3MB (for release) and 2MB (for debug) layout.
Change-Id: I881832a6b11a35710d4e847feadcc544b1f5d048
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77994
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
|
|
Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: I590b7fb5f5f52cbf1a61c65f8fac757e36feac5e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75028
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: I866333a234203dc2da3d4dd8c4f87e4cfa332787
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: Ia4ed3491e6a32659b957285ab20ad47c9085083c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75025
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: I097d50a7af7c8ea48369806e8bb73734a8e84470
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75024
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: Id7f9b598cc9df51ddf664b851172cc96a710c580
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75023
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: I3f4965b8b253983ad1f8db77e1b91860a270c305
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: If2c9c52f1e2866082df8e534b1a074639bb62db2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75020
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: Idf4a566af3853636945709c88c03fb8e777211c2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: Iaa73bf7f85f840299c467b7d712546d3f72a4e75
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: Id1b0d375670f9e59047eff737bc17e61bf93175e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75016
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: I1033a974a818308b31e1334cad5869d2cd81bd9e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75017
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: I207e25059a9fb9e6a951018e954662931b3f8b93
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75018
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: Id060f781b87567da2756c89275002b9ea4f4976c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75015
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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No drivers exists or are needed, so use devicetree hidden keyword to
set the ACPI status to hidden to prevent unknown devices from showing
in Windows Device Manager.
TEST=build/boot Win11 on morphius, verify unknown devices for the
fingerprint reader and stylus detection are no longer shown.
Change-Id: I992c0ec8d97c6041e3a268445613bfa42dd8b279
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Enable wake-on-DP by adding USB mux events to the wake mask. The EC
wakes the AP with these events for DP connect/disconnect.
BUG=b:294307786
TEST=DP connect/disconnect wakes the DUT appropriately.
Change-Id: I864b03d08ce3d756bf4987d886db621d937483ce
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78034
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Karis uses PIXA touchpad, update related settings.
BUG=b:294155897
TEST=(1) emerge-rex coreboot
(2) Test on karis, touchpad function works
Change-Id: I26e3257485c4abe050de7a79c6d3b72dbd048710
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77517
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This board is similar to x11ssm-f but has a proprietary form factor with
NVMe and a single x16 slot (potentially bifurcated to 2x x8) and a x4
slot.
Change-Id: I53a0b6012ae64cf1ba4b625f11aaf771637307f3
Signed-off-by: Kieran Kunhya <kieran@kunhya.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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BUG=b:299374763
TEST=emerge-rex coreboot
Change-Id: I40fc768522e8679337c3b9f5497278e9f4639c3e
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77888
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch ensures that the
`DRIVERS_INTEL_MIPI_SUPPORTS_PRE_PRODUCTION_SOC` config is enabled if
the underlying platform is built with a pre-production SoC (aka
`SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON` config is enabled).
BUG=b:300652989
TEST=Ensures `DRIVERS_INTEL_MIPI_SUPPORTS_PRE_PRODUCTION_SOC` is enabled
for google/rex4es aka all variants with ES silicon.
Change-Id: Ieda39427915fa3973b832376ec20fc414ac2bedd
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77993
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
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The tree contains engineering sample boards, that ship with
pre-production Meteor Lake SoC. These boards are not sold.
BUG=b:300652989
TEST=Ensure mainboards like google/rex4es and screebo4es have
`SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON` config enabled.
Change-Id: I1a875a0f1d2c38582f35250ebe645e53599f62de
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77992
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
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Add the eMMC MMIO device to the devicetree and make it use the common
AMD eMMC driver. Since there is now a device for this in the devicetree,
also use this device to determine if the FSP should be told if the eMMC
controller is supposed to be disabled.
TEST=On Mandolin the eMMC controller both disappears in the Windows 10
device manager and in dmesg on Ubuntu 2022.04 LTS
TEST=Morphius with NVMe SSD still works
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5453b69df776d2ce1f3be11e37cd26c8c64f0cd5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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GPP_C06 is the report pin of the touchpanel and has no actual function.
Disable this pin to solve the leakage problem.
BUG=b:298529441
BRANCH=none
TEST=Test success by EE.
Change-Id: I13f25788c0258639da4e277e7a15454a08d1599b
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77716
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Make naming convention consistent across all functions return values.
BUG=b:296439237
TEST=Boot to OS on Skyrim
BRANCH=None
Change-Id: If86805b39048800276ab90b7687644ec2a0d4bee
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77536
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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With commit b7832de0260b042c25bf8f53abcb32e20a29ae9c ("x86: Add .data
section support for pre-memory stages"), the `ENV_HAS_DATA_SECTION'
flag and its derivatives can now be removed from the code.
Change-Id: Ic0afac76264a9bd4a9c93ca35c90bd84e9b747a2
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77291
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit dc7cc5bc6edf ("mb/google/skyrim: Disable
USE_SELECTIVE_GOP_INIT") but limits the default enablement to Skyrim
variant only, to allow for continued testing.
BUG=b:271850970
BRANCH=skyrim
TEST=build/boot ChromeOS R117+ on google/skyrim, verify no display init
failures with feature enabled on cold/warm boots or S0i3 resume.
Change-Id: I21c70111a5f407a7e8dd1ad1f2c2759ddb91893e
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Update PLDs to match the port layout:
Front (left to right):
A4, A3, A2
Back (left to right):
C0, A0, A1
BUG=b:264960828
TEST=USB2 and USB3 ports are peered correctly in the kernel:
Before:
$ cd /sys/devices/pci0000:00/0000:00:14.0
$ ls -l $(find . -name peer)
./usb1/1-0:1.0/usb1-port1/peer -> ../../../usb2/2-0:1.0/usb2-port1
./usb1/1-0:1.0/usb1-port2/peer -> ../../../usb2/2-0:1.0/usb2-port2
./usb1/1-0:1.0/usb1-port3/peer -> ../../../usb2/2-0:1.0/usb2-port3
./usb1/1-0:1.0/usb1-port4/peer -> ../../../usb2/2-0:1.0/usb2-port4
./usb1/1-0:1.0/usb1-port5/peer -> ../../../usb2/2-0:1.0/usb2-port5
./usb1/1-0:1.0/usb1-port6/peer -> ../../../usb2/2-0:1.0/usb2-port6
./usb2/2-0:1.0/usb2-port1/peer -> ../../../usb1/1-0:1.0/usb1-port1
./usb2/2-0:1.0/usb2-port2/peer -> ../../../usb1/1-0:1.0/usb1-port2
./usb2/2-0:1.0/usb2-port3/peer -> ../../../usb1/1-0:1.0/usb1-port3
./usb2/2-0:1.0/usb2-port4/peer -> ../../../usb1/1-0:1.0/usb1-port4
./usb2/2-0:1.0/usb2-port5/peer -> ../../../usb1/1-0:1.0/usb1-port5
./usb2/2-0:1.0/usb2-port6/peer -> ../../../usb1/1-0:1.0/usb1-port6
After:
$ cd /sys/devices/pci0000:00/0000:00:14.0
$ ls -l $(find . -name peer)
./usb1/1-0:1.0/usb1-port1/peer -> ../../../usb2/2-0:1.0/usb2-port1
./usb1/1-0:1.0/usb1-port2/peer -> ../../../usb2/2-0:1.0/usb2-port3
./usb1/1-0:1.0/usb1-port3/peer -> ../../../usb2/2-0:1.0/usb2-port4
./usb1/1-0:1.0/usb1-port4/peer -> ../../../usb2/2-0:1.0/usb2-port6
./usb1/1-0:1.0/usb1-port5/peer -> ../../../usb2/2-0:1.0/usb2-port5
./usb1/1-0:1.0/usb1-port7/peer -> ../../../usb2/2-0:1.0/usb2-port2
./usb2/2-0:1.0/usb2-port1/peer -> ../../../usb1/1-0:1.0/usb1-port1
./usb2/2-0:1.0/usb2-port2/peer -> ../../../usb1/1-0:1.0/usb1-port7
./usb2/2-0:1.0/usb2-port3/peer -> ../../../usb1/1-0:1.0/usb1-port2
./usb2/2-0:1.0/usb2-port4/peer -> ../../../usb1/1-0:1.0/usb1-port3
./usb2/2-0:1.0/usb2-port5/peer -> ../../../usb1/1-0:1.0/usb1-port5
./usb2/2-0:1.0/usb2-port6/peer -> ../../../usb1/1-0:1.0/usb1-port4
Change-Id: I682a153d6b757e1b66373c622a6fcfbf389184e3
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77877
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update PLDs to match the port layout:
Front (left to right):
C0, A1, A0
Left side:
C1
Also enable the usb 3.1 device.
BUG=b:264960828
TEST=USB2 and USB3 ports are peered correctly in the kernel:
Before:
$ cd /sys/devices/pci0000:00/0000:00:14.0
$ ls -l $(find . -name peer)
./usb1/1-0:1.0/usb1-port1/peer -> ../../../usb2/2-0:1.0/usb2-port1
./usb1/1-0:1.0/usb1-port3/peer -> ../../../usb2/2-0:1.0/usb2-port3
./usb1/1-0:1.0/usb1-port4/peer -> ../../../usb2/2-0:1.0/usb2-port4
./usb1/1-0:1.0/usb1-port5/peer -> ../../../usb2/2-0:1.0/usb2-port5
./usb1/1-0:1.0/usb1-port6/peer -> ../../../usb2/2-0:1.0/usb2-port6
./usb2/2-0:1.0/usb2-port1/peer -> ../../../usb1/1-0:1.0/usb1-port1
./usb2/2-0:1.0/usb2-port3/peer -> ../../../usb1/1-0:1.0/usb1-port3
./usb2/2-0:1.0/usb2-port4/peer -> ../../../usb1/1-0:1.0/usb1-port4
./usb2/2-0:1.0/usb2-port5/peer -> ../../../usb1/1-0:1.0/usb1-port5
./usb2/2-0:1.0/usb2-port6/peer -> ../../../usb1/1-0:1.0/usb1-port6
After:
$ cd /sys/devices/pci0000:00/0000:00:14.0
$ ls -l $(find . -name peer)
./usb1/1-0:1.0/usb1-port1/peer -> ../../../usb2/2-0:1.0/usb2-port1
./usb1/1-0:1.0/usb1-port2/peer -> ../../../usb2/2-0:1.0/usb2-port3
./usb1/1-0:1.0/usb1-port3/peer -> ../../../usb2/2-0:1.0/usb2-port4
./usb1/1-0:1.0/usb1-port4/peer -> ../../../usb2/2-0:1.0/usb2-port2
./usb1/1-0:1.0/usb1-port5/peer -> ../../../usb2/2-0:1.0/usb2-port5
./usb1/1-0:1.0/usb1-port6/peer -> ../../../usb2/2-0:1.0/usb2-port6
./usb2/2-0:1.0/usb2-port1/peer -> ../../../usb1/1-0:1.0/usb1-port1
./usb2/2-0:1.0/usb2-port2/peer -> ../../../usb1/1-0:1.0/usb1-port4
./usb2/2-0:1.0/usb2-port3/peer -> ../../../usb1/1-0:1.0/usb1-port2
./usb2/2-0:1.0/usb2-port4/peer -> ../../../usb1/1-0:1.0/usb1-port3
./usb2/2-0:1.0/usb2-port5/peer -> ../../../usb1/1-0:1.0/usb1-port5
./usb2/2-0:1.0/usb2-port6/peer -> ../../../usb1/1-0:1.0/usb1-port6
(Ports 5 and 6 are not used on boxy but are peered by default)
Change-Id: I1563d9eaa27353c8c97225a0a6ecc238e9275ce2
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
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This patch eliminates the need to maintain separate FMD files for rex
variants and rex variants with ISH. It does this by using the
BOARD_GOOGLE_MODEL_REX_EC_ISH config to differentiate between ME-RW
layout sizes.
TEST=Able to build and boot google/rex and google/rex_ec_ish.
Change-Id: Ibb6ee9aad9fb68198c6c1a1d5978f77d53a2e3ac
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77895
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
