summaryrefslogtreecommitdiff
path: root/src/mainboard
AgeCommit message (Collapse)Author
2020-09-29mb/intel/jslrvp: Update PMC as hidden deviceMaulik V Vaghela
This change allows treating the PMC as a 'hidden' PCI device on JasperLake, so that the MMIO & I/O resources can be exposed as belonging to this device, instead of the system agent and LPC/eSPI. Original patch for jasperlake SoC here: CB:42018 This change was missing for JasperLake rvp board. TEST=Checked PMC init function is called and also checked PCI resource for PMC device 1f.2. Change-Id: I7531d32c62d3f9735938f744f2892ab9c9bebddf Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-28mb/google/fizz/endeavour/gpio: Reflow long linesMaxim Polyakov
Use the 96 character limit. Change-Id: I865288051869e50602a579a6999b1b23ef68ec2f Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-28mb/google/octopus/variants/fleex: Only do LTE power off for LTE skuEric Lai
Only do LTE power off for LTE sku in order to save extra 130ms delay for non-LTE sku. BUG=b:168075958 BRANCH=octopus TEST=build image and verify on the DUT with LTE DB. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: If983185ff2f09fb1b2553c6ff1a1473d3254de4b Reviewed-on: https://review.coreboot.org/c/coreboot/+/45687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com>
2020-09-28mb/clevo/cml-u/Kconfig: Remove MAINBOARD_SMBIOS_PRODUCT_NAMEElyes HAOUAS
MAINBOARD_SMBIOS_PRODUCT_NAME is duplicated. Change-Id: I011f83c4d4e0657256839db207bfd1517922744c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-28mb/google/zork: Set eMMC presetsRaul E Rangel
They should be tuned per board to get the best signal and boot time. This fixes the HS400 preset, so it's correctly set to A. It also changes the SDR50 and DDR50 presets to B. We can't boot correctly when DDR50 is set to A. I chose 1 as the init kHz value since that's what depthcharge uses to calculate the init clock. BUG=b:159823235 TEST=Boot Ezkinil and dump SDHCI preset registers. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie2f3497b65d771820ab1a803fec73265547f8906 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-09-28mb/ocp/deltalake: add LPC device entry in ACPIJonathan Zhang
PCH LPC device is on CSTACK. Add LPC ACPI device entry. Without this change, following error message shows up in target OS boot log: ACPI BIOS Error (bug): Failure looking up [\_SB.PCI0.LPCB], AE_NOT_FOUND (20180105/dswload-211) ACPI Error: AE_NOT_FOUND, During name lookup/catalog (20180105/psobject-252) ACPI Error: AE_NOT_FOUND, (SSDT:COREBOOT) while loading table (20180105/tbxfload-228) ACPI Error: 1 table load failures, 1 successful (20180105/tbxfload-246) Also TPM device is not created. TESTED=Booted DeltaLake DVT, run following command in target OS: [root@dhcp-100-96-192-153 ~]# dmesg | grep tpm [ 7.331890] tpm_tis MSFT0101:00: 2.0 TPM (device-id 0x1B, rev-id 16) Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I8614f6951389bd5c8f8f33522d0a9a9160ac3f66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-09-28mb/google/octopus/var/fleex: Use Wifi SAR table for non-LTE sku onlyEric Lai
Use Wifi SAR table for non-LTE sku only. BUG=b:169115341 BRANCH=octopus TEST=Check no SAR table can be loaded with sku id 4. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I086fa14a9f23e4a0fc0ef8085040219c932dbf17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45640 Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28mb/volteer: Use Genesys Logic GL9755 for Delbin, Volteer2Ravi Sarawadi
Enable newly added PCIe Gen2 to SD 4.0 card reader controller GL9755 for Delbin and Volteer2. BUG=b:166141961 TEST=Boot to kernel on Delbin, Volteer2 boards. Check PC10 in IDON. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I2589ab2334625ec0d20dbdd5f3a31d98235aad2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/45708 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28mb/purism/librem_whl: Drop 3Gbps SATA limit; enable and set SATA tuning paramsMatt DeVillier
Some Librem Minis exhibit issues with 6Gbps SATA operation on certain SSDs, setting the Receiver Equalization Boost Magnitude adjustment resolves this, so limiting SATA speeds to 3Gbps is no longer needed. Test: build/boot Librem Mini with Crucial SATA SSD, observe no issues booting, no ATA-related errors in dmesg on PureOS 10 / kernel 5.8.7 Change-Id: I8b3cbcff7f181bcab35d71e859033578c822bb20 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-28mb/purism/librem_skl: Enable and set SATA tuning paramsMatt DeVillier
Some Librems have issues with 6Gbps SATA operation on certain SSDs, setting the Receiver Equalization Boost Magnitude adjustment resolves this. Test: build/boot Librem 15v3 with Crucial SATA SSD, observe no issues booting, no ATA-related errors in dmesg on PureOS 10 / kernel 5.8.7 Change-Id: I078deeff7fc54694393b5b16c41c5d622b332781 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-28mb/google/volteer/variants/eldrid: Configure GPP_S4 and GPP_S5nick_xr_chen
GPP_S4 and GPP_S5 use as DMIC pins that need to be defined as NF2 BUG=b:168564129 Signed-off-by: nick_xr_chen <nick_xr_chen@wistron.corp-partner.google.com> Change-Id: Ia1fca960ac85f253882f0aa68b370eed49ac67b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
2020-09-28mb/google/volteer/var/terrador: Enable audio SMBIOS OEM stringKevin Cheng
It needs to use probe statement in overridetree.cb to enable the cache of fw_config field implemented by cb:44782 and cb:44783. BUG=b:161963281 TEST= dmidecode -t 11 shows correct audio fw_config. Handle 0x0009, DMI type 11, 5 bytes OEM Strings String 1: DB_USB-USB4_GEN2 String 2: AUDIO-MAX98373_ALC5682I_I2S_UP4 Signed-off-by: Kevin Cheng <kevin.cheng@intel.com> Change-Id: I68c19b67d945aaca3e9ebec87eb27a4b07e1a49e Reviewed-on: https://review.coreboot.org/c/coreboot/+/45673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-28mb/google/zork: update telemetry settings for berknipKevin Chiu
update telemetry to improve the performance. BUG=b:168581158 BRANCH=zork TEST=1. emerge-zork coreboot 2. pass AMD SDLE test Change-Id: Ib93905cd89132664b06f2476e94494e96980642c Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-28mb/google/dedede/var/magolor: apply DPTF settingRen Kuo
add tcc, critical, passive policy, and pl values from thermal team BUG=b:168353037 TEST=build and verify by thermal tool Change-Id: I887d494ff097a881d519a456f24578a278323051 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45453 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28mb/google/dedede/var/magolor: Add ACPI camera supportRen Kuo
1. enable DRIVERS_INTEL_MIPI_CAMERA/SOC_INTEL_COMMON_BLOCK_IPU 2. add IPU/VCM/NVM/CAM0 in devicetree BUG=b:166527568 TEST= build and verify function by cam ap on DUT Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: Ica6aa8ddc03a1dab5b548a759825dd3a4de3101f Reviewed-on: https://review.coreboot.org/c/coreboot/+/45329 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28mb/google/dedede/var/madoo: Clean-up static camera ASL fileKarthikeyan Ramasubramanian
Camera ACPI tables are generated at run-time for all variants of Dedede. BUG=None TEST=Build madoo variant. Change-Id: Icb74c01a0a6dbc620466b64cd2b5652408ca41b9 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-09-28mb/google/volteer: Improve Eldrid Port 1 USB2 Eye Diagramnick_xr_chen
In order to pass DB type-C USB2 eye diagram, DB USB2 PHY register needs to be overridden. port#1 PortUsb20Enable=1 Usb2PhyPetxiset=7 Usb2PhyTxiset=7 Usb2PhyPredeemp=3 Usb2PhyPehalfbit=0 BUG=b:169105751 Signed-off-by: nick_xr_chen <nick_xr_chen@wistron.corp-partner.google.com> Change-Id: If076c644783fa2992ac062d6469f9c49e6d5ff24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-28mb/acer/g43t-am3: add Acer G43T-AM3 mainboardMichael Büchler
Adds a new port for the Aspire G43T-AM3. It is from an Aspire M3800 desktop model of which I only own the mainboard. The silkscreen label calls it "G45T/G43T-AM3 V:1.0". In DMI data it is additionally called Acer EG43M. The Aspire M5800 model seems to use the same mainboard. The BIOS you can download from Acer is identical for both. Various similar mainboards by Acer exist: G41T-AM, G43T-AM, G43T-AM4, Q45T-AM, to name a few. ECS has some models that are obiously based on the same design, e.g. G43T-WM and G43T-M. This model is a microATX-sized board with an LGA 775 socket, four DDR3 DIMM slots, one PCIe x16 slot, one PCIe x1 slot and two PCI slots based on the Intel G43 chipset. The port was started by copying mb/intel/dg43gt (not going to lie here) and adapting things by looking at dumps from the system when running with the vendor BIOS. Serial console output is possible by soldering to a point at the corresponding Super I/O pin. The service manual for the board was helpful for setting the correct PCI IRQ links. It can be found publicly on the internet as the "Acer Aspire M3800 Service Manual". Working: - CPUs from Pentium Dual-Core E2160 to Core 2 Quad Q9550 at FSB1333 - Native raminit - All four DIMM slots at 1066 MHz (tested 2x2GB + 2x4GB) - PS/2 mouse - PS/2 keyboard (needs CONFIG_SEABIOS_PS2_TIMEOUT, tested: 500) - USB ports (8 internal, 4 external) - All six SATA ports - Intel GbE - Both PCI ports with various cards (Ethernet, audio, USB, VGA) - Integrated graphics (libgfxinit) - HDMI and VGA ports - boot with PCIe graphics and SeaBIOS - boot with PCI VGA and SeaBIOS - Both PCIe ports - Flashing with flashrom - Rear audio output - SeaBIOS 1.14.0 to boot slackware64 - SeaBIOS 1.14.0 to boot Windows 10 (needs VGA BIOS) - Temperature readings (including PECI) - Super I/O EC automatic fan control - S3 suspend/resume - Poweroff Not working: - Resource issues with the VGA BIOS of a PCI rv100-based card - Super I/O voltage reading conversions Untested: - The other audio jacks or the front panel header - On-board Firewire - EHCI debug - VBT (was extracted and added, but don't know how to test) - Super I/O GPIOs Signed-off-by: Michael Büchler <michael.buechler@posteo.net> Change-Id: I846cf5f4f1ef27fc644676a4c6f7a333e061f6cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/44167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-28mb/intel/tglrvp: Add DTT support for tglrvpSumeet R Pawnikar
Add DTT (Dynamic Tuning Technology) support for Tiger Lake based rvp board. Set power limits and CPU sensor thresholds for DTT based thermal control. BRANCH=None BUG=None TEST=Build and boot on tglrvp board Change-Id: I0dbee370b8dc9e1e3ae6f1a1101047ac6fd76f53 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-09-28mb/google/vilboz: update telemetry settingsChris Wang
update the telemetry setting for second SDLE testing(for APU power adjusting). Those values are used to power calibration the APU power and achieving the best performance. BUG=b:160698427 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I4cf5b8f090befd6a3c4990f44f2f200bc66aa1f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44804 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28mb/google/zork: update telemetry settings for dirinbozKevin Chiu
update telemetry to improve the performance. BUG=b:168585079 BRANCH=zork TEST=emerge-zork coreboot Change-Id: I464b90550aaa1666ce3f2393856bf46fe7686d1d Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-28mb/google/dedede/var/drawcia: Enable EC keyboard backlightWisley Chen
BUG=b:168847046 TEST=emerge-dedede coreboot chromeos-bootimage Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Change-Id: I16ed22aa5e270ad2d5c964764cc134b72941d4e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-09-28mb/google/zork/vilboz: Add new memory part H5ANAG6NDMR-XNCAmanda Huang
Add new ID for memory part H5ANAG6NDMR-XNC. Command to generate files: go build gen_part_id.go local variant=vilboz ./gen_part_id ../../../src/mainboard/google/zork/spd ../../../src/mainboard/google/zork/variants/${variant}/spd/ ../../../src/mainboard/google/zork/variants/${variant}/spd/mem_parts_used.txt BUG=b:165611994 TEST=none Change-Id: Iaf613d54bf23b637e38917937ce3e78702b26a28 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45682 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28mb/google/zork/vilboz: Remove unused memory part IDsAmanda Huang
These parts have not been used in any vilboz devices. Removing so IDs can be assigned more efficiently. Command to generate files: go build gen_part_id.go local variant=vilboz ./gen_part_id ../../../src/mainboard/google/zork/spd ../../../src/mainboard/google/zork/variants/${variant}/spd/ ../../../src/mainboard/google/zork/variants/${variant}/spd/mem_parts_used.txt BUG=b:165611994 TEST=none Change-Id: I99614acaf45db0556120c883577494d9f753ea12 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45679 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28util: Add new memory part for zork boardsAmanda Huang
Add memory part H5ANAG6NDMR-XNC. Attributes are derived from data sheets. BUG=b:165611994 TEST=Compared generated SPD with data sheets and checked in SPD Change-Id: Ifdcc7536441e9f0b94543c6f06fe466596f752dc Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-09-28mb/google/zork: disable eMMC per FW_CONFIG for MorphiusKevin Chiu
Morphius has SSD/eMMC SKU, we should turn off eMMC if storage is NVMe SSD. BUG=b:169211959 BRANCH=zork TEST=1. emerge-zork coreboot 2. Check eMMC is enabled or disabled based on the eMMC bit in FW_CONFIG. Change-Id: I67d5d77ce3d827ae89b82529de59925f67eaf894 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2020-09-27mb/Kconfig: Drop ROM sizes below 256KiBNico Huber
Not even our emulation targets can build with these anymore. Change-Id: If108a17f824a31c375a43cb4903ee07c65217f6e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45753 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-25mb/google/volteer: Wake on AC connect and disconnectAbe Levkoy
Add AC connect and disconnect to S0ix lazy wake sources. BUG=b:161466940 BRANCH=master TEST=Connect and disconnect charger in S0ix; observe wake Change-Id: I30046a379ff75c33b991e355cc8d142241ee8b2e Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45669 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-25volteer: Create boldar variantRonak Kanabar
Create the boldar variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). Add "memory/Makefile.inc" generated by gen_part_id.go BUG=b:162202257 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_BOLDAR Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Change-Id: I92b4b917448d8e5e9176cb983adf7b209956d2c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-25mb/google/zork: Modify I2C3 CLK for Woomax to meet I2C specificationKane Chen
Modify I2C3 setting to follow I2C specification(lower than 400kHz). Original setting: .rise_time_ns = 125 .fall_time_ns = 37 Change to: .rise_time_ns = 110 .fall_time_ns = 34 BUG=b:169207742 BRANCH=None TEST=emerge-zork coreboot chromeos-bootimage Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I0f0b791c3e701ebf6b336a8cb259eeb74c46af5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/45644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-09-25mb/google/zork: Modify USB 2.0 PHY parameters for WoomaxKane Chen
Modify USB 2.0 PHY parameters for improve usb eye diagram. 1. USB 2.0 TypeC port0: .com_pds_tune = 0x03, .sq_rx_tune = 0x3, .tx_fsls_tune = 0x3, .tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, .rx_vref_tune = 0xf, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, 2. USB 2.0 TypeC port3: .com_pds_tune = 0x03, .sq_rx_tune = 0x3, .tx_fsls_tune = 0x3, .tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_pulse_tune = 0x0, .tx_rise_tune = 0x1, .rx_vref_tune = 0xf, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, BUG=b:169207729 BRANCH=zork TEST=emerge-zork coreboot chromeos-bootimage Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I764238485a1a81eb0d4740ac58c80a43f965f550 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45641 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-25mb/clevo/cml-u: remove the duplicate WiFi PCIe device in devicetreeMichael Niewöhner
Change-Id: Ibb46bbf0c889bb8b3fd1a4c0331dc719baffc7a2 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45678 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-25mb/clevo: Rename l140cu to cml-uFelix Singer
In addition to CB:45664, rename clevo/l140cu to clevo/cml-u being able to add more variants under a generic mainboard later. Change-Id: I9c16e24830ebb80752df302aa2e63d9df8edad95 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45665 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-24mb/clevo/l140cu: Make usage of variant mechanismFelix Singer
Clevo mainboards can be grouped by their common platform. Therefore, restructure the mainboard directory as a first step, so that the variant mechanism is used. This moves most of the code into the variant dir, since the L140CU is the only variant at the moment. Change-Id: I9ad1c06f9db854cac1dd420c53dc0c9f010ed716 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45664 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-24soc/intel/cnl: drop lpit.asl in favor of common versionMichael Niewöhner
Drop lpit.asl from CNL and switch to the common one in the three boards currently using it. The only difference between the two is the usage on macros in common code instead of plain integer values. Change-Id: Iefbd18db7f4c560dce16c4119fde4f4cfbeafb84 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-24mb/google/volteer: Enable CnviBtAudioOffloadJohn Zhao
This change enables CnviBtAudioOffload. FSP is invoked to configure BT over USB and BT I2S pins for cAVS connection. BUG=b:169045123 TEST=Verifed CnviBtCore and CnviBtAudioOffload settings and FSP configuration. Booted up to kernel on Volteer. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I1780da0824d145a79743d5cffdea4821236d4f74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naveen M <naveen.m@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-24mb/google/volteer/var/voxel: Update gpio settings for EVTSheng-Liang Pan
Based on EVT schematic and gpio table of voxel, update gpio settings for voxel EVT. BUG=b:156841729 TEST=FW_NAME=voxel emerge-volteer coreboot chromeos-bootimage Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Idf88d83ad6d873283eb1eb8a45459ae3e74df124 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45173 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-24mb: Copy system76/lemp9 to clevo/l140cuFelix Singer
Copy system76/lemp9 to clevo/l140cu, since it's a Clevo notebook actually and both have the same mainboard. This commit is meant to create a working copy for clevo/l140cu. The only changes are names. Further patches will follow to make this mainboard more generic. Since system76/lemp9 is based on System76's EC firmware, EC stuff does not work correctly yet. This will be fixed in another patch. Tested on TUXEDO InfinityBook S 14 v5 and PCZ Lafité Pro 14. Change-Id: I7c2993256fd9123a8013df5ba8292ea1ead10f74 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-23mb/google/zork: simplify flashmap fileFelix Held
Now that we're using fmaptool to parse the .fmd file, we can use some short forms and omit unnecessary information. BUG=b:157068645 TEST=None BRANCH=zork Change-Id: I81c121d4fce13a9d2aad4477955cb4770794d244 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-23mb/amd/mandolin: simplify flashmap fileFelix Held
Now that we're using fmaptool to parse the .fmd file, we can use some short forms and omit unnecessary information. BUG=b:157068645 TEST=Timeless build for amd/mandolin resulted in identical binary. BRANCH=zork Change-Id: I196c7857f165e75b543c1bda650e044b5ad0664e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-23mb/intel/tglrvp: Enable Intel Speed Shift Technology for Tigerlake RVPShreesh Chhabbi
BUG=none TEST=Build for Tigerlake RVP and boot to OS. Test if following sysfs is populated. cat /sys/devices/system/cpu/intel_pstate/ Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Change-Id: Ie3d9691e149a6fbc19c6691896126d04c680fde3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45609 Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-23mb/google/octopus: Set ModPhyIfValue to default value 0x12Marx Wang
0x12 will be more stable according to validation result on SD card and USB devices. BUG=b:163382089 BRANCH=none TEST=check if SD cards and USB devices work properly Signed-off-by: Marx Wang <marx.wang@intel.com> Change-Id: Ic98f27b6164daa3667009300439c61fed43a4a0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/45573 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Henry Sun <henrysun@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-23mb/dell: Fix uninitialized variables usageJohn Zhao
Coverity detects uninitialized variables through PASS_BY_REFERENCE usage. Fix this issue by initializing variables before their uage. Found-by: Coverity CID 1429765, 1429772, 1429780 TEST=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ie583b072a76949fb3f17c1271a6427ee942db0ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/45611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-09-23treewide: rename GENERIC_SPD_BIN to HAVE_SPD_BIN_IN_CBFSMichael Niewöhner
The name GENERIC_SPD_BIN doesn't reflect anymore what that config is used for, so rename it to HAVE_SPD_BIN_IN_CBFS. Change-Id: I4004c48da205949e05101039abd4cf32666787df Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45147 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-22mb/*: drop GENERIC_SPD_BIN from boards without soldered memoryMichael Niewöhner
Drop GENERIC_SPD_BIN from boards selecting it, despite having no soldered memory. Change-Id: Id05fe45007d5662ff9bee326f28470df1206fcff Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45146 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-22mb/system76/lemp9: gpio: convert gpio.h to a cleaner formatMichael Niewöhner
Convert gpio.h to a compacter, cleaner format by keeping gpios in a single line, where possible. This was done with the following fancy vim regex replacement commands. (Neither sed, nor awk multiline matching syntax are friends with me...) Just open src/mainboard/system76/lemp9/gpio.h with vim, type : before pasting each command, press enter and see how the format changes. g#^\t//#d %s/^\t\t/\t/ g/PAD_.*$\n\n[^/]/s/\n// g#// NC#d %s#^\t// \(.*\)\n\t// \(.*\)#\t// \1 \2#g %s#^\t// \(.*\)\n\t\(PAD_.*,\)#\t\2\t\t/* \1 */ %s#^// \(GP.*\)#\t/* ------- GPIO Group \1 ------- */# Finally some indents and multiline comments need to be fixed manually. Test: images built with TIMELESS do not differ. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I9054274dc4c8942935b6a4789bfc1547dd3d4017 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-09-22mb/system76/lemp9: convert inverted SCI/SMI macros to _LOW macroMichael Niewöhner
Convert PAD_CFG_GPI_S*I(..., INVERT) to PAD_CFG_GPI_S*I_LOW(...), which is better understandable. Change-Id: I147c82d738623bff54122ad5ef8ece028c562cab Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45488 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-22mb/kontron: Drop unneeded empty linesElyes HAOUAS
Change-Id: Ie106bbc8222dce60c837042a313d069289c79322 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-22mb/google: Drop unneeded empty linesElyes HAOUAS
Change-Id: I4151d1a6ce94763432f307fbc8bc4afe229856ea Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-22soc/intel/jasperlake: Enable processor thermal control using PCI_DEVFNSumeet R Pawnikar
Enable processor thermal control using PCI dev path function instead of Device4Enable parameter in devicetree. This change removes the dependency on Device4Enable in devicetree. We can enable and disable this thermal control using on and off support with PCI device entry in devicetree. BRANCH=None BUG=None TEST=Built and tested on dedede board Change-Id: I0463236996ad001af506c9966840b27fe44d60d2 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-22src/mainboard: Add missing <console/console.h>Elyes HAOUAS
"post_code()" needs <console/console.h>. Change-Id: Ice92d5e259b369da949006bf471a0cb249291897 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-22mb/apple/macbook21/acpi: Convert *.asl to ASL 2.0 syntaxElyes HAOUAS
It changes the binary for apple/macbook21 because of optimization of "Store" instruction. Generated build/dsdt.dsl files are same. Change-Id: I16b5180f8a8c44e6bc3ef353a99ef92a381b3295 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-22mb/google/dedede/variants/madoo: Adjust I2Cs CLK to meet specJohn Su
After adjustment on madoo Touch Pad CLK: 381.9 KHz Touch Screen CLK: 389.4 KHz Audio CLK: 380.9 KHz BUG=b:168565823 BRANCH=master TEST=USE=build madoo and measure by scope with madoo. Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: If281f9a8614e3e0ef20893b456f46e68ecb0631d Reviewed-on: https://review.coreboot.org/c/coreboot/+/45406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-09-21mb/system76/lemp9: gpio: convert the remaining raw pads to macrosMichael Niewöhner
Convert the EC and touchpad interrupt pads from raw to macros. This was done with intelp2m. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I79d2cca0f300e6daf1c1923a1882e4cc1ffc3c8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/43648 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21mb/intel/tglrvp: Enable CSE Firmware Lite SKUJamie Ryu
CSE Lite SKU is CSE FW designed for Chrome and this enables CSE Lite SKU support for tglrvp. BUG=None TEST=Build and boot tglrvp with CSE Lite and Consumer SKU Change-Id: Ia5f3e8125b5e7760a62f7fb46aeeae85c32e2037 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41132 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21treewide/Kconfig: Drop unneeded empty linesElyes HAOUAS
Change-Id: If8aa28a22625b7b2cf9b58958de87ee752f637f6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-21mb/intel: Drop unneeded empty linesElyes HAOUAS
Change-Id: I3fdc521d30155c4275c336afe03244311f584e71 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44617 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21mb/msi: Drop unneeded empty linesElyes HAOUAS
Change-Id: Id51da519582856b1856479b641599e14f79fd1ad Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-21mb/protectli: Drop unneeded empty linesElyes HAOUAS
Change-Id: I051dc318c5f881bc58b1a4460faad6af22049b39 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-21mb/scaleway: Drop unneeded empty linesElyes HAOUAS
Change-Id: If56031a7b39d1c1b3ebf6d19376f19ec8c7cef1a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-21mb/sifive: Drop unneeded empty linesElyes HAOUAS
Change-Id: I5274bc7206ba333d06f5defc35fdede540a7148f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-21mb/roda/rk886ex: Drop unneeded empty linesElyes HAOUAS
Change-Id: I229d3995983a05cdd7fef1609a65f31b9f8f2969 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-21mb/dell: Drop unneeded empty linesElyes HAOUAS
Change-Id: I3d0ca401cf5268962bcd9074f94c37724cc0a836 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-21mb/supermicro: Drop unneeded empty linesElyes HAOUAS
Change-Id: I1aae6c0291ad329c8cc125cd18ba22dfd63d979b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-21mb/asus/am1i-a: Drop unneeded empty linesElyes HAOUAS
Change-Id: Ib56b56c05df154522172bff2e6746280286a481f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-21mb/hp/z220_sff_workstation: Add empty lines after "SPDX"Elyes HAOUAS
Change-Id: Ief8df9ef0d6ecb675680aa5120738f5099034139 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45245 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21mb/gizmosphere: Drop unneeded empty linesElyes HAOUAS
Change-Id: If631055dffa79e7562d6238f6e0b88ad1c7d38b4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-21mb/jetway: Drop unneeded empty linesElyes HAOUAS
Change-Id: Id9837eda69d725539a82b3c98f63a57240051c5b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-21mb/elmex: Drop unneeded empty linesElyes HAOUAS
Change-Id: I6dc9f153270fe501d53ab44c902401893aacf1b9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-21mb/pcengines: Drop unneeded empty linesElyes HAOUAS
Change-Id: Ica6a885721b3a88814973d1cf086d2d4bc3d922d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-21mb/asrock: Drop unneeded empty linesElyes HAOUAS
Change-Id: I035b66e749e9a3e1bde13c8ed7ceafeb1edbbfa4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-21mb/lippert: Drop unneeded empty linesElyes HAOUAS
Change-Id: I82c2527039a9bd278e57cfbd88a009ee5ba03e1d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-21mb/samsung: Drop unneeded empty linesElyes HAOUAS
Change-Id: I76d5292871c1578f9d27d46b7a2c485a14c3017b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-21mb/amd: Drop unneeded empty linesElyes HAOUAS
Change-Id: I2ceeae8dd25663203549a87b4e9524a631fa92f8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-21mb/lenovo: Drop unneeded empty linesElyes HAOUAS
Change-Id: Icad51da75d99dd541f8f2621a16eae13a596d264 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-21mb/google/hatch/Kconfig: Make cse override depend on lite skuEdward O'Callaghan
Lets have the Kconfig depend more directly on CSE_LITE_SKU than indirectly on the PUFF baseboard. BUG=none BRANCH=puff TEST=builds Change-Id: I8784b506629ceedc2770dc86d8caabbef5eb8a1d Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45523 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21mb/google/octopus: Clean up LTE power off functionEric Lai
All octopus board share the same power off sequence. Move to smihandler.c instead variant.c. BUG=b:168075958 BRANCH=octopus TEST=build image and verify on the DUT with LTE DB. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I2be5a656fb42fff99c56d21aaa73ed9140caad37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45436 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21mb/intel/tglrvp: Enable HECI interfaceJamie Ryu
This is to enable Intel ME communication interface HECI1 by devicetree for PAVP with CSE Lite. PAVP feature is enabled with CSE Lite SKU for Chrome and HECI1 interface is required between kernel and CSE Lite. BUG=None TEST=Build and boot tglrvp. Run lspci and check pcie device 00:16.0 Communication controller: Intel Corporation Device a0e0 Change-Id: I23117fa96503942e6a72765dd3fd1cc762e3f705 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-21mb/google/dedede/var/madoo: Add Wifi SAR for madooDtrain Hsu
Add wifi sar for madoo. Using tablet mode of fw config to decide to load custom wifi sar or not. BUG=b:165105210 TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ic6128b966c952cdc02a6359c14fa41f22265039a Reviewed-on: https://review.coreboot.org/c/coreboot/+/45439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-09-21mb/51nb/x210/gpio: 3/4 Fix PAD_RESET to convert to PAD_NC()Maxim Polyakov
Fix this bit field to convert to target macros PAD_NC() macros. This is part of the patch set "mb/51nb/x210/gpio: Rewrite pad config using intelp2m": CB:43566 - 1/4 Decode raw register values CB:43567 - 2/4 Exclude fields for PAD_CFG CB:43568 - 3/4 Fixes PAD_RESET to convert to PAD_NC() CB:43410 - 4/4 Convert field macros to PAD_CFG Change-Id: I73a3d78457c1e50dc9625a47394e340181516696 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43568 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21mb/51nb/x210/gpio: 2/4 Exclude fields for PAD_CFGMaxim Polyakov
This patch excludes bit fields that must be ignored (1,2) in order to convert current macros to target PAD_CFG_*() macros. The following commands were used for this: ./intelp2m -fld cb -ign -t 1 -file ../../src/mainboard/51nb/x210/gpio.h - ignore RO bit fields; - ignore RX Level/Edge Configuration (bit 26:25) and RX/TX Buffer Disable (bit 9:8) for the native function, because it does not affect the pad in this mode. This is part of the patch set "mb/51nb/x210/gpio: Rewrite pad config using intelp2m": CB:43566 - 1/4 Decode raw register values CB:43567 - 2/4 Exclude fields for PAD_CFG CB:43568 - 3/4 Fixes PAD_RESET to convert to PAD_NC() CB:43410 - 4/4 Convert field macros to PAD_CFG Change-Id: Id0196b20783126c36f8552534b7ec3bd9049a24f Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43567 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21mb/razer/blade_stealth_kbl: 2/3 Exclude fields to match PAD_CFGMaxim Polyakov
This patch excludes bit fields that must be ignored (1,2) in order to convert current macros to target PAD_CFG_*() macros. The following commands were used for this: ./intelp2m -fld cb -ign -t 1 -file ../../src/mainboard/razer/ blade_stealth_kbl/gpio.h - ignore RO bit fields; - ignore RX Level/Edge Configuration (bit 26:25) and RX/TX Buffer Disable (bit 9:8) for the native function, because it does not affect the pad in this mode. This is part of the patch set "mb/razer/blade_stealth_kbl/gpio: Rewrite pad config using intelp2m": CB:43857 - 1/3 Decode raw register values CB:43858 - 2/3 Exclude fields for PAD_CFG CB:43411 - 3/3 Convert field macros to PAD_CFG Change-Id: Ia36c5d0cd449a32d76351a87a33a55196ae78443 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43858 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Mimoja <coreboot@mimoja.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21mb/razer/blade_stealth_kbl: 1/3 Decode raw register valuesMaxim Polyakov
Use the intelp2m utility [1,2] with -adv options to convert the pad configuration format with the raw values of the DW0 and DW1 registers to the format with the bit fields macros: PAD_FUNC(), PAD_RESET(), PAD_TRIG(), PAD_BUF(), PAD_PULL(), etc... ./intelp2m -fld cb -t 1 -file ../../src/mainboard/razer/ blade_stealth_kbl/gpio.h This is part of the patch set "mb/razer/blade_stealth_kbl/gpio: Rewrite pad config using intelp2m": CB:43857 - 1/3 Decode raw register values CB:43858 - 2/3 Exclude fields for PAD_CFG CB:43411 - 3/3 Convert field macros to PAD_CFG Tested with BUILD_TIMELESS=1, Razer Blade Stealth, remains identical. [1] https://github.com/maxpoliak/pch-pads-parser [2] https://review.coreboot.org/c/coreboot/+/35643 Change-Id: I7c4a29f87b56c5ec7e4b74274ae677c4c08c2e8c Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Mimoja <coreboot@mimoja.de>
2020-09-21mb/51nb/x210/gpio: 1/4 Decode raw register valuesMaxim Polyakov
Use the intelp2m utility [1,2] with -fld=cb options to convert the pad configuration format with the raw values of the DW0 and DW1 registers to the format with the bit fields macros: PAD_FUNC(), PAD_RESET(), PAD_TRIG(), PAD_BUF(), PAD_PULL(), etc... ./intelp2m -fld cb -t 1 -file ../../src/mainboard/51nb/x210/gpio.h This is part of the patch set "mb/51nb/x210/gpio: Rewrite pad config using intelp2m": CB:43566 - 1/4 Decode raw register values CB:43567 - 2/4 Exclude fields for PAD_CFG CB:43568 - 3/4 Fixes PAD_RESET to convert to PAD_NC() CB:43410 - 4/4 Convert field macros to PAD_CFG Tested with BUILD_TIMELESS=1, 51NB-X210, remains identical. [1] https://github.com/maxpoliak/pch-pads-parser [2] https://review.coreboot.org/c/coreboot/+/35643 Change-Id: I19282c985cf35a9f99be449915aa9bab7e03472d Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43566 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21volteer: set GSPI CS to deasserted by defaultCaveh Jalali
This sets the state of GSPI chip select to 1 (deasserted) as applied by the FSP during the silicon init phase. GSPI 0 and 1 are set to CS mode manual in the SerialIoGSpiCsMode section which means we need to explicitly configure CS to deasserted in the SerialIoGSpiCsState section. GSPI0 is the CR50 and GSPI1 is the fingerprint sensor. We were running into problems where the normal expected CS toggle sequence to wake up CR50 did not work because CS was already asserted when it was expected to be deasserted, leading to TPM timeouts. BUG=b:168090038 TEST=booted on volteer, no more "TPM flow control failure" messages; verified fingerprint enrollment still works. Change-Id: I47aa5db429d75e66095d58a1eb77963dcfc3b9f3 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45384 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21mb/google/volteer: Add firmware configuration for MAX98373_ALC5682I_I2S_UP4Frank Wu
Add MAX98373_ALC5682I_I2S_UP4 firmware configuration option and configure GPIOs properly for UP4 design. The design is also for Halvor. BUG=b:153680359, b:163382106 TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage, fw_config value in Halvor: > AUDIO=MAX98373_ALC5682I_I2S_UP4 ectool cbi set 6 0x00000400 4 2 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Ie25f278dfbdc2f41a36b70403699a2e3c2234600 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-21mb/google/volteer: fw_config: Add fields for keyboard featuresDuncan Laurie
Add newly defined fields for presence of keyboard backlight and number pad to the firmware configuration table. We don't have a need to use these in coreboot (yet) but this keeps the bit definitions in sync. BUG=b:166707536 TEST=abuild -t google/volteer Change-Id: I066e445f7d0be056e45737d2c538be1850ae85aa Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-20mb/system76/lemp9: move LPC options to the devicetreeMichael Niewöhner
Change-Id: I7b7acdc51c848541fb39926bc8de1115c026dd05 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45496 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-20mb/system76/lemp9: correct CBFS_SIZEMichael Niewöhner
The BIOS region size is 0xc00000, not 0xa00000. Correct this. Change-Id: I88cb0d4b9a590a32672054aa0db7f9a92070ff6d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-09-20mb/system76/lemp9: enable SATA ALPM capabilityMichael Niewöhner
Enable SATA Link Power Management capability to be able to save power. TEST: /sys/class/scsi_host/host*/link_power_management_policy exists. Change-Id: I88de28cfb266af3fcd6e498a08a24b46c992cb9d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45492 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-20mb/system76/lemp9: drop disabled options from devicetreeMichael Niewöhner
Drop all options with zero-value, since they already default to 0. Change-Id: I2a1a91778e83dc49c6dcf2d518cd3591f7ec4cfa Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45491 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-20mb/google/zork: update morphius dptc clamshell/tablet mode settingKevin Chiu
clamshell/tablet: Slow_ppt_limit(W) 20 Fast_ppt_limit(W) 24 Slow_ppt_time_constant 5 Stapm_time_constant 200 Sustained_power_limit(W) 12 clamshell: Temperature limit(C') 100 tablet: Temperature limit(C') 70 BUG=b:157943445 BRANCH=zork TEST=1. emerge-zork coreboot 2. change mode and check "thermctl_limit" will change Change-Id: I1eda1411766e446b673046236f7cc4015696521f Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45520 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-19mb/system76/lemp9: move subsystem id from Kconfig to devicetreeMichael Niewöhner
Change-Id: I21e7e53787b115f50093d7caa72285ce480cef52 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-19mb/up/squared: move subsystem id from Kconfig to devicetreeMichael Niewöhner
Change-Id: Icf62a73ee568d9369c53bd767bd4cfb736ea76f1 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-19apollolake boards: Enable CSE in devicetreeSubrata Banik
Enable CSE PCI device Bus 0: Device 0x0f: Function 0x00 to let Intel common cse block code can use this device. Calling me_read_config32(offset) function from ramstage: Without this CL : HECI: Global Reset(Type:1) Command BUG: me_read_config32 requests hidden 00:0f.0 PCI: dev is NULL! With this CL : HECI: Global Reset(Type:1) Command HECI: Global Reset success! Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I97d221ae52b4b03ecd859d708847ad77fe4bf465 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-18trogdor: Move EN_PP3300_DX_EDP for CoachzJulius Werner
This patch updates the display power enable GPIO which moved from 30 to 52 for Coachz. Veterans of this project know that there's no point trying to ask *why* this change was necessary -- the pins move in mysterious ways and all we can do is watch and wonder. Pin 30 is now used for a new camera reset GPIO... surely, there must have been some excellent reason why that pin couldn't just have become pin 52 instead. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I00ad6a6249df66006b4f2b953a0a2449bd478f6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/45306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Philip Chen <philipchen@google.com>
2020-09-18mb/google/octopus/variants/fleex: support LTE power sequenceEric Lai
GPIOs related to power sequence are GPIO_67 - EN_PP3300 GPIO_117 - FULL_CARD_POWER_ON_OFF GPIO_161 - PLT_RST_LTE_L 1. Power on: GPIO_67 -> 0ms -> GPIO_117 -> 30ms -> GPIO_161 2. Power off: GPIO_161 -> 30ms -> GPIO_117 -> 100ms -> GPIO_67 3. Power reset: - keep GPIO_67 and GPIO_117 high and - pull down GPIO_161 for 30ms then release it. BUG=b:168075958 BRANCH=octopus TEST=build image and verify on the DUT with LTE DB. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I9b56ef8ff346c1d4edd5aad04d4a7396c4702ffc Reviewed-on: https://review.coreboot.org/c/coreboot/+/45193 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-18mb/google/volteer: Remove redundant GPIO decls in EldridTim Wawrzynczak
GPP_A19 and GPP_A20 are already declared as NC in the baseboard. Change-Id: I02f5751a70b51a197320b865d18da3a4ffeb87f7 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45485 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-18mb/google/volteer/eldrid: Add option to enable WiFi SAR configsMalik_Hsu
This change adds a user selectable option to enable all WiFi SAR configs that apply to volteer BUG=b:168169690 TEST=1. cros-workon-volteer start coreboot-private-files-baseboard-volteer 2. USE="project_eldrid" emerge-volteer chromeos-config coreboot-private-files-baseboard-volteer 3. check wifi_sar-eldrid.hex in coreboot-private/3rdparty/blobs/baseboard-volteer Change-Id: I6b74cd2b34ebb99cc59d456e28fd7ab2399d71d0 Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45233 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-18superio/nuvoton: Inline `nuvoton_hwm_select_bank`Angel Pons
There's no need to place a single-line function in its own compilation unit, and then guard it behind a Kconfig symbol. This also allows using this function in stages other than ramstage. Change-Id: I103a4ea4cef24844d382854c9358bbb37d229e04 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42130 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>