diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-09-19 11:49:05 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-09-24 18:55:19 +0000 |
| commit | 733c462c13ff29eaef1195de5ae61e06211ca719 (patch) | |
| tree | a49d1213222f87eb480f7e99644d79aaae5acf7e /src/mainboard | |
| parent | c8e309779f54827d8f30907ab8e3439582625a65 (diff) | |
soc/intel/cnl: drop lpit.asl in favor of common version
Drop lpit.asl from CNL and switch to the common one in the three boards
currently using it.
The only difference between the two is the usage on macros in common
code instead of plain integer values.
Change-Id: Iefbd18db7f4c560dce16c4119fde4f4cfbeafb84
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/drallion/dsdt.asl | 2 | ||||
| -rw-r--r-- | src/mainboard/google/hatch/dsdt.asl | 2 | ||||
| -rw-r--r-- | src/mainboard/google/sarien/dsdt.asl | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl index ef2a94e1bd..c9f7391977 100644 --- a/src/mainboard/google/drallion/dsdt.asl +++ b/src/mainboard/google/drallion/dsdt.asl @@ -40,7 +40,7 @@ DefinitionBlock( #include <southbridge/intel/common/acpi/sleepstates.asl> /* Low power idle table */ - #include <soc/intel/cannonlake/acpi/lpit.asl> + #include <soc/intel/common/acpi/lpit.asl> /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index d43a499519..d60da37503 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -37,7 +37,7 @@ DefinitionBlock( #include <southbridge/intel/common/acpi/sleepstates.asl> /* Low power idle table */ - #include <soc/intel/cannonlake/acpi/lpit.asl> + #include <soc/intel/common/acpi/lpit.asl> /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index b666fbc4f6..0382fcb8dd 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -40,7 +40,7 @@ DefinitionBlock( #include <southbridge/intel/common/acpi/sleepstates.asl> /* Low power idle table */ - #include <soc/intel/cannonlake/acpi/lpit.asl> + #include <soc/intel/common/acpi/lpit.asl> #if CONFIG(EC_GOOGLE_WILCO) /* Chrome OS Embedded Controller */ |