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2024-02-13mb/google/brox: Set display output type for eDP panelMatt DeVillier
Set the display type for the LCD panel configured via the gfx/generic driver. This will ensure the correct DID/device address are generated in the SSDT. Change-Id: If63374329ed5eb4330517ca1bf2ba1ada24fa54a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80244 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-13mb/google/brox: Use name 'LCD0' for internal panel outputMatt DeVillier
The GMA driver generates the brightness controls expecting the name LCD0, so we need to use it here as well so that the DSDT and SSDT parts match. Change-Id: Id52f7c0e542423ba08eeed89bf9b171e540e10e4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-13mb/google/rex: Use name 'LCD0' for internal panel outputMatt DeVillier
The GMA driver generates the brightness controls expecting the name LCD0, so we need to use it here as well so that the DSDT and SSDT parts match. Change-Id: Id93cfea93edfefc8237b53214734531b811b36e4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80202 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-13mb/google/rex: Set display output type for eDP panelMatt DeVillier
Set the display type for the LCD panel configured via the gfx/generic driver. This will ensure the correct DID/device address are generated in the SSDT. Change-Id: I8f390c58710c91bf77555f664e8f89f08ca59b30 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-02-13mb/google/hatch/var/jinlon: Ensure LCD backlight controls generatedMatt DeVillier
Jinlon disables the eps device if no privacy screen is present, so add a second generic gfx device 'no_eps' to handle that case, so that ACPI backlight controls are generated either way. Add logic to ensure only one of the two devices is active. TEST=build/boot Win11 on google/hatch (jinlon), ensure LCD backlight controls present and functional on device both with and without a privacy screen. Change-Id: Icf20de97d26c8be76c84e87d5dc6ed1a4b6dbfbc Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80178 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-13mb/google/hatch/var/jinlon: Use name 'LCD0' for internal panel outputMatt DeVillier
The GMA driver generates the brightness controls expecting the name LCD0, so we need to use it here as well so that the DSDT and SSDT parts match. TEST=build/boot Win11 on google/hatch (jinlon), verify LCD brightness controls are functional. Change-Id: I4204a518876bed38584260f7566d4d6c9aaa042f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80177 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-13mb/google/brya/var/*: Use name 'LCD0' for internal panel outputMatt DeVillier
The GMA driver generates the brightness controls expecting the name LCD0, so we need to use it here as well so that the DSDT and SSDT parts match. TEST=build/boot Win11 on google/brya (redrix), verify brightness controls are functional. Change-Id: I389553b2ddc5b09d165229e2d8066cacf852b82c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80174 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Won Chung <wonchung@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-02-13mb/google/drallion: Drop GMA default panelMatt DeVillier
Redundant when generic gfx driver is used Change-Id: I8ed1eede05f531f4c76e7fa168c2b92fae7e45cb Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-13mb/google/drallion: Use name 'LCD0' for internal panel outputMatt DeVillier
The GMA driver generates the brightness controls expecting the name LCD0, so we need to use it here as well so that the DSDT and SSDT parts match. TEST=build/boot Win11 on google/drallion, verify brightness controls are functional. Change-Id: I6fbdd0c5606ec8f2c497e85bf46d388957f15fa5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80175 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-02-13mb/google/puff: Hide LSPCON device from WindowsMatt DeVillier
Puff-based Chromeboxes use a LSPCON for HDMI 2.0 output, but no driver exists or is needed for Windows. Use the devicetree hidden keyword to set the ACPI status to hidden for these devices, to prevent unknown devices from being listed in Windows Device Manager. TEST=build/boot Win11 on google/wyvern, verify no unknown devices in Windows Device Manager for either LSPCON device. Change-Id: Ib646e01a337b8d7baf20a886c49a8cb64d6408f3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78040 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-02-13mb/google/volteer/drobit: Add a board-specific VBT fileMatt DeVillier
Add a board-specific VBT file compatible with the latest FSP release (requires VBT version 250). TODO: Update all other volteer VBTs to v250 from v240. TEST=build/boot google/volteer (drobit) with edk2 payload Change-Id: Ie25a77be5204dfc8b888082492a285973843037c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80183 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-02-12mb/asus/p8z77-m/hda_verb.c: Use existing defines for NC pinsKeith Hui
Goal is to use existing defines for all pins to make the file self-documenting, but it would make lines too long, so I'll just start with the NC pins. TEST=Timeless binary did not change. Change-Id: I6da02d7bc4c87cc8477d687b238e6e6c9aec62cd Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79733 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-12ec/lenovo/h8/acpi: Support pulsing LEDLOGO on Haswell ThinkPadsEvgeny Sorokin
The name LEDLOGO comes from schematics. It's the red indicator, embedded in the dot of the 'i' of the ThinkPad logo on laptop's lid. In vendor firmware, this led starts fading in-and-out, or, in other words, pulsing, when laptop is put to S3. It helps to determine whether the laptop is in S3 just by taking a look at the logo. As of now, coreboot doesn't do anything with this particular indicator, it's always in enabled (on) state, which is not very convenient. This patch fixes it. Tested on T440p. Change-Id: I85fb69c8c1bed8635a1b31e9b8385c7036bb46dd Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80437 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-09mb/google/brox: Initialize TCHSCR_RST_L to 0Shelley Chen
TCHSCR_RST_L signal was originally being configured to 1 in gpio.c but this was causing some leakage. Configuring it to 0 initially in romstage fixes this. Also, make sure that EN_PP3300_TCHSCR is initialized in romstage as well. BUG=b:322249892 BRANCH=None TEST=Make brox boots and touchscreen is still working Change-Id: I5bf1901a3a40a38237b950abcb758f96aebcc1cf Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80300 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-09mb/google/nissa: Skip GPP_F15 GPIO locking to avoid IRQ stormWeimin Wu
There is an existing issue for nissa where wake up from RTC wake is not working during suspend_stress_test. The phenomenon of the issue is that after pulling out the stylus, can see an interrupt storm occurs, checking through: "cat /proc/interrupts | grep acpi". When the counter of interrupt is greater than a certain value, "Disabling IRQ #9" will occur, so RTC wake is not working. Reference: https://review.coreboot.org/c/coreboot/+/65086 This patch skips the locking for GPP_F15 to allow kernel to configure it later. The interrupt storm of acpi disappears. BUG=b:321348117 TEST=1. cat /proc/interrupts | grep acpi there isn't interrupt storm of acpi when pulling out stylus. 2. The stylus tools panel will pop up when pulling out it. 3. Inserts stylus can wakeup DUT after powerd_dbus_suspend. 4. Passed: suspend_stress_test -c 2500 --suspend_min=15 --suspend_max=20 Change-Id: Ie143c43e0555d17d8a290f17637b537fba806144 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80316 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-09mb/google/nissa/var/anraggar: Config DP AUX BIAS according to fw_configWeimin Wu
EVT mini-build changes redriver IC from PS8745 to ANX7493, the ANX7493 not support DP AUX BIAS, so connects DP AUX BIAS of DB to SOC directly. Add DB_AUX_BIAS bit field to fw_config for compatibility. BUG=b:320235566 TEST=DP function of MB and DB workable Change-Id: I53974ec7444912a63d0fe0a9303c9e5d6941f68d Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80259 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-08mb/google/puff/var/*: Clean up SerialIO/I2C config in overridetreeMatt DeVillier
Ensure that the SerialIoDevMode config and common_soc_config registers for each variant are programmed consistently with the devices' enabled status in that variant's overridetree; remove and disable extraneous devices as appropriate. TEST=build/boot several puff variants, verify all components working as expected, nothing missing from cbmem, lspci, etc. Change-Id: Ib9d0cf48e405be7c00c553646651fc6f28c4e3f0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80164 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-08mb/google/puff/var/*: Drop redundant device entries in overridetreeMatt DeVillier
Now that the puff baseboard uses chipset devicetree references, remove all references whose value is identical to the chipset devicetree default or the baseboard default, since they are pointless clutter. TEST=tested with rest of patch train Change-Id: Iada32111367fdc964d6126ee43e261c1feb123cf Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-08mb/google/puff: Delegate I2C device configuration to overridetreeMatt DeVillier
Don't enable the i2c controllers, since the variants will enable the ones they need individually in their overrridetrees. Disable gspi1 since all variants disable it in their overridetrees. TEST=tested with rest of patch train Change-Id: Ia9c67a8e05923a080e31d04721ecae4c810e82e8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-08mb/google/puff: Drop devicetree entries identical to chipset.cbMatt DeVillier
Now that puff uses chipset devicetree references, remove all references whose value is identical to the chipset devicetree default, since they are pointless clutter. TEST=tested with rest of patch train Change-Id: I3a515f13df1252ed2b769a535da22a523c95c359 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80141 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-08mb/google/puff: Use chipset dt reference namesFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous. Change-Id: I06a3acca0a72ff158a0143acc87d9479b2deb0d5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-02-08mb/google/nissa/var/yaviks: Enable USE_MTCL and DRIVERS_MTK_WIFIDavid Ruth
This patch selects the DRIVERS_MTK_WIFI and USE_MTCL configs for google/yaviks as the first platform that provides a country list to the Linux kernel via an ACPI function (MTCL) in SSDT for MediaTek WiFi chipsets that are capable of operating on the 6GHz band. BUG=b:295544553 TEST=Build on similar model (PUJJO) that I have access to and verify the flag and feature work as intended. TEST=Add wifi_mtcls.bin blob to cbfs TEST=Build coreboot for pujjo `emerge-nissa coreboot chromeos-bootimage` TEST=Verify that MTCL defined in the file is present: TEST=`acpidump -b` TEST=`iasl ssdt.dat` TEST=`less ssdt.dsl` TEST=Search for MTCL Change-Id: Iec54fc582d68b443665fceda47187c28f1a9216c Signed-off-by: David Ruth <druth@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80305 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-02-08mb/google/brox: Handle GPI_INT pin lower to GPI_WAKEAshish Kumar Mishra
In case where PAD_CFG_GPI_INT() is initialized with a pin value lower to PAD_CFG_GPI_IRQ_WAKE() for same GPIO community the set_ioapic_used() is only called for the PAD_CFG_GPI_IRQ_WAKE() pin. Due to this the IRQ associated with PAD_CFG_GPI_INT() is found free by find_free_unique_irq() during IRQ assignment and assigned to other pins which causes IRQ conflicts BUG=b:322984217 BRANCH=None TEST=Boot test on brox, check if correct IRQ assigned to EC Change-Id: I8c3d557e888b8d0ceac203f49b702910fba26d6d Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80334 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-07mb/google/brya/var/xol: Update GPIO configurationsSeunghwan Kim
Upload initial GPIO configuration for xol based on proto schematics. BUG=b:319506033 BRANCH=firmware-brya-14505.B TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage xol proto board can boot to ChromeOS Change-Id: I224e58628e44571c07ce034136d690587e62be08 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80325 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-07mb/google/brya/var/xol: Update Kconfig and devicetreeSeunghwan Kim
Upload the initial devicetree and update Kconfig for xol following proto schematics. BUG=b:319506033 BRANCH=firmware-brya-14505.B TEST=FW_NAME=xol emerge-brya coreboot Change-Id: I411932eb4872d77993394a290e8afdd1a0038faf Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80324 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-02-06soc/intel/xeon_sp/smihandler: Lock SMM_FEATURE_CONTROL on all socketsPatrick Rudolph
Remove hardcoded B:D:F numbers for the first socket and pass the PCI addresses to be locked within SMM by using the smm_pci_resource_store. This allows to lock down SMM on all sockets without knowing the actual bus topology or PCI segment group at compile time where the UBOX devices reside on. Tested: SMM is locked on all 4 sockets instead of just one. Change-Id: Ica694911384005681662d3d7bed354a60bf08911 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80247 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-05mb/google/brox: Fix the I2C configurationKarthikeyan Ramasubramanian
Update the I2C configuration to match the usage such that only required I2C controllers are enabled. BUG=b:319390850 TEST=Build Brox BIOS image and boot to OS. Ensure that only the required I2C controllers are enabled. Change-Id: I9f24beb9ef587163362cc6ded88efb05be1329b9 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80303 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-03mb/google/rex/var/karis: Follow rex0 CNVi/PCIe switchingTyler Wang
Follow reference design rex0, keep the GPIO settings of CNVi/PCIe. Only set GPP_F04,GPP_F05/GPP_S01,GPP_S02 to NC when WIFI_PCIE/WIFI_CNVI is selected. BUG=none TEST=Build and test on karis Change-Id: Id23a2cfe0639f2d423980db9badc16c1477434d1 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80215 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-02-03mb/google/rex/var/karis: Update fw_config KB_TYPE fieldTyler Wang
Update element "KB_TYPE_CA" for align fw_config. Only EC will reference KB_TYPE field in fw_config. This CL is just for align fw_config. BUG=none TEST=emerge coreboot pass Change-Id: Ied54f78dddd9dddca1272fc31c9502fc11c61dde Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eran Mitrani <mitrani@google.com>
2024-02-02mb/amd/birman: add Phoenix with openSIL mainboard optionFelix Held
Introduce BOARD_AMD_BIRMAN_PHOENIX_OPENSIL which selects the openSIL based Phoenix SoC code. Since the Phoenix chip.c is different due to some FSP-specific data structures in there that are guarded in the openSIL case, a separate devicetree for the openSIL case is added. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I248102e92818b2d395d561a4bf2627f80906b2f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-02-02mb/amd/birman: add _FSP postfix to BOARD_AMD_BIRMAN_PHOENIXFelix Held
Rename the BOARD_AMD_BIRMAN_PHOENIX option to BOARD_AMD_BIRMAN_PHOENIX_FSP to distinguish between the FSP-based SoC initialization and the non-FSP based one. Also change the MAINBOARD_PART_NUMBER string to 'Birman_Phoenix_FSP'. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id3293a07cd1b1833df15ee0a40cad3127e19b7df Reviewed-on: https://review.coreboot.org/c/coreboot/+/80290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-02-02mb/amd/birman/Kconfig: fix comment on endifFelix Held
The last 'endif' belongs to the 'if BOARD_AMD_BIRMAN_COMMON' in line 26, so fix the comment. Commit 35a30de7afcc ("mb/amd/birman: Use common option for variant configuration") changed that condition, but missed updating this comment, so do this now. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I986e5a456e8f9fd92aacd007479c861feea06199 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-02-01mb/google/brox: Enable HDA Codec ALC256Poornima Tom
On Brox, HDA Codec used is ALC256. Add verb table for the same. Also, add the related device tree changes for HDA related registers. Realtek High Definition Audio Configuration- Version : 5.0.3.1 BUG=b:317398558 BRANCH=None TEST=verified HDA on Brox. HDA Sound cards detected. Headphone working verified. Device listed under sysfs as below: cat /sys/bus/hdaudio/devices/ehdaudio0D0/chip_name ID 256 cat /sys/bus/hdaudio/devices/ehdaudio0D0/vendor_name Realtek Change-Id: I1edd5aee053debe39b34048266703031c088cd00 Signed-off-by: Poornima Tom <poornima.tom@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79723 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-31device/device.h: Rename busses for clarityArthur Heymans
This renames bus to upstream and link_list to downstream. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-31mb/google/rex/variants/deku: correct GPIO E08 and E22 configurationEran Mitrani
GPP_E08 and GPP_E22 were set incorrectly previously. This CL corrects these settings according to schematics. BUG=b:305793886 TEST=Built FW image correctly. Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I8e427350e1ee564f9d6566bdfe1f42c92c87a711 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-01-31include/device/device.h: Remove CHIP_NAME() macroNicholas Sudsgaard
Macros can be confusing on their own; hiding commas make things worse. This can sometimes be downright misleading. A "good" example would be the code in soc/intel/xeon_sp/spr/chip.c: CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev, This appears as CHIP_NAME() being some struct when in fact these are defining 2 separate members of the same struct. It was decided to remove this macro altogether, as it does not do anything special and incurs a maintenance burden. Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80239 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-31mb/google/brya: Correct Ti50 EC-is-trusted logiczengqinghong
With Cr50, the GPIO EC_IN_RW is used to determine whether EC is trusted. However, With the switch to Ti50, it is determined by Ti50's boot mode. If the boot mode is TRUSTED_RO, the VB2_CONTEXT_EC_TRUSTED flag will be set in check_boot_mode(). Therefore in the Ti50 case get_ec_is_trusted() can just return 0. The current code of get_ec_is_trusted() only checks the GPIO, which causes the EC to be always considered "trusted". Therefore, correct the return value to 0 for TPM_GOOGLE_TI50. BUG=b:321172119 TEST=emerge-nissa coreboot chromeos-bootimage TEST=firmware_DevMode passed in FAFT test Change-Id: I308f8b36411030911c4421d80827fc49ff325a1b Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp- partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-30mb/google/rex/variants/deku: Add H58G66BK7BX067 to RAM ID tableTony Huang
Add RAM ID for H58G66BK7BX067 0 (0000) BUG=b:322528721 BRANCH=firmware-rex-15709.B TEST=Run part_id_gen tool without any errors Change-Id: I31538988d1329d9e2f45d862eb0ae05c0d6a179e Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-01-30mb/google/rex/var/karis: Set SOC_TCHSCR_RST output low in bootblockTyler Wang
Check MTL EDS2, SOC_TCHSCR_RST(GPP_C01) default setting is NF1. Set SOC_TCHSCR_RST to output low in early_gpio_table. BUG=none TEST=Build and test on karis, touchscreen function works Change-Id: Ieebd3cf3c320bc895d036c372f792ec7b5d7ebf9 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-30mb/google/rex/var/karis: Toggle NVMe PWR pin to reset SSDTyler Wang
Follow reference design rex0, toggles NVMe PWR pin as soon as in early stage to make NVMe ready sooner. BUG=none TEST=Build karis and try warm reboot from OS console. Check the DUT with WD SSD boots to OS again. Change-Id: I24a702f02278355c4f2137f0d05c8a9da7cb3c1c Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80213 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-30mb/google/geralt: Increase VM18 LDO voltage to 1.9V for CiriCong Yang
The current panel voltage measured at mainboard side is 1.79V and the voltage at panel side is 1.74V. Since the panel requires 1.8V or more, increase the circuit voltage to 1.9V to meet the panel requirement. After adjustment mainboard side voltage is 1.89V and panel side is 1.84V. BUG=b:322080023 TEST=Check ciri vm18 ldo voltage BRANCH=None Change-Id: I6d6193d45409f53c0b656890c44ddaef253c5e01 Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80198 Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-27soc/amd: use common ACPI_SCI_IRQ definitionFelix Held
ACPI_SCI_IRQ is defined as 9 for all AMD SoCs, so move the definition to the common amdblocks/acpi.h. Since all but Stoneyridge's soc/acpi.h are now empty, delete those files too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8210c98dc4cf2c6001d5273d132053278ff7fea5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80222 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-27mb/siemens/mc_ehl3: Use PSE GbE 0 instead of PSE GbE 1Jan Samek
As a result of hardware changes on this board, the PHY previously routed to the PSE GbE 1 is now routed to PSE GbE 0 on the Elkhart Lake SoC. This patch changes the device PCI ID in the board's devicetree and accordingly, the GPIO configuration. BUG=none TEST=Boot into Linux and observe whether both PSE GbE 0 and PCH GbE are working, while PSE GbE 1 remains inactive (not listed by 'ip link') . Change-Id: I322371f944d15134e6f48ecd84a4026c2fced27b Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2024-01-27mb/siemens/mc_ehl5: Set LVDS re-power delay to 1 sMario Scheithauer
The currently used panel type could work with 500 ms but increasing the value to 1 second allows to use a wider range of LVDS LCD panels, as many of them specify the delay of 1 s as minimum. The patch has already been made for mc_ehl3 and serves the purpose of standardization. commit c0221aa980d3 ("mb/siemens/mc_ehl3/lcd_panel.c: Set LVDS re-power delay to 1 s") Change-Id: Ife26ff27b41298ceeed7d9aed0c1ae5553ab5ff8 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com>
2024-01-27mb/google/nissa/var/anraggar: Enable BT audio offloadJianeng Ceng
This patch enables Cnvi BT Audio Offload feature and also configures the virtual GPIO for CNVi Bluetooth I2S pads. BUG=b:303157827 TEST=Build and boot to anraggar. Verify the config from serial logs. w/o this CL - ``` [SPEW ] -- CNVi Config -- [SPEW ] CNVi Mode= 1 [SPEW ] Wi-Fi Core= 1 [SPEW ] BT Core= 1 [SPEW ] BT Audio Offload= 0 [SPEW ] Pin Muxing ``` w/ this CL - ``` [SPEW ] -- CNVi Config -- [SPEW ] CNVi Mode= 1 [SPEW ] Wi-Fi Core= 1 [SPEW ] BT Core= 1 [SPEW ] BT Audio Offload= 1 [SPEW ] Pin Muxing ``` Change-Id: I9e6731c8ceaad6ee58b525d4246fa769bfe1b0c7 Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80001 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-27mb/google/brya/var/omniknight: Add WIFI SAR tablejamie_chen
Add WIFI SAR table for omniknight. BUG=b:320172979 TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I70e79577612b3d5c4dc0f92211f87cbea0532d5d Signed-off-by: jamie_chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80152 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2024-01-27mb/google/rex: Organize models configs alphabeticallySubrata Banik
This patch ensures the baseboard and variant configs (inside Kconfig and Kconfig.name) are organized in alphabetic order. TEST=execute make menuconfig and verify the google/rex variants order are alphabetically correct. Change-Id: I0acc2cec21b4607856127b04c400ec416f0c0dd2 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80206 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Jakub Czapiga <czapiga@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-26mb/google/dedede/var/galtic: Support for Samsung K4U6E3S4AB-MGCLDaniel Peng
Add the new memory support: Samsung K4U6E3S4AB-MGCL BUG=b:320137193 BRANCH=firmware-dedede-13606.B TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\ part_id_gen.go JSL lp4x \ src/mainboard/google/dedede/variants/galtic/memory/ \ src/mainboard/google/dedede/variants/galtic/memory/\ mem_parts_used.txt" Change-Id: I3f6c784a194e141a3dd1e5a37b3cf12106e692d6 Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80150 Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-01-26mb/google/brox: Enable TouchscreenShelley Chen
BUG=b:300690448,b:319393777 BRANCH=None TEST=tested on a device with i2cdetect Also tested with evtest and make sure Wacom is listed Change-Id: I4f528b0d778c8c4a4e83774d5c167ccb2d6afd9a Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79895 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-26mb/google/brox: Remove CNVi BluetoothShelley Chen
This is causing an assertion error on the devices that don't have CNVi enabled because CNVi is hidden behind a FW_CONFIG flag in the overridetree now. BUG=b:319188820 BRANCH=None TEST=emerge-brox coreboot chromeos-bootimage make sure we can boot to kernel on device. Change-Id: Ifcfbc04825d4d4e7f2874a4c52f9c5cf3e657856 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80211 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-26src, util: Clean up makefile.inc in text, help & commentsMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ib69236fb5d68272f92405512dc231fa75ecccaa6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-26mb/amd/onyx_poc: Add and use APCB configuration dataVarshit Pandya
This patch adds APCB blobs to the mainboard directory and it replaces CB:76445 Also this brings onyx_poc mainboard inline with how APCB are included in other AMD mainboard: commit 95d05d830162 ("mb/google/zork: Add and use APCB configuration data"), commit I352f58e0d39 ("mb/google/ skyrim: Add and use APCB configuration data") and commit I1c34528fa0f ("mb/amd/onyx_poc: Add and use APCB configuration data"). BUG=none TEST=build/boot onyx_poc Change-Id: I1c34528fa0fd15b847c22c995713078c60ac3873 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80204 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-26mb/purism/librem_cnl: Set edk2 boot timeout for Librem MiniMatt DeVillier
As with other devices with only an external display, the Librem mini/ mini-v2 need a few extra seconds (vs an internal panel) for display init in order for the edk2 boot splash to be visible before the default boot target is booted. TEST=build/boot Librem Mini v2 w/edk2 payload, verify splash screen shown / user has time to enter setup menu. Change-Id: I9d2d514719a9918ee58cc63969b3adae44ac1632 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
2024-01-26mb/google/brya: alphabetize model configsNick Vaccaro
Alphabetize the ordering of model configs and selects in Kconfig and Kconfig.name BUG=None BRANCH=None TEST='emerge-brya coreboot' and verify it builds. Change-Id: Id9347421337d451ce72fcf3984489b06f372f70c Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-26mb/google/rex/var/karis: Skip tcc_offset overrideSubrata Banik
This change eliminates the unnecessary override of the tcc_offset chip configuration to 10, as the default rex baseboard now handles this setting correctly. TEST=Successfully built and booted google/karis, confirming tcc_offset remains at 10. Change-Id: Ie40db1431fb0197ee360ad5656878e57f51c855b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-01-26mb/google/rex/var/screebo: Modify TCC_offset to 20Subrata Banik
Follow thermal team request, override tcc_offset to 20. TEST=Build and verified by thermal team using google/screebo. Change-Id: Idc76f9c0054f21f066b779e6404a1c175eb396a0 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-01-25mb/google/rex/variants/deku: update USB-C port configurationTony Huang
This CL update setting according to schematic v0.4. BUG=b:320201111 BRANCH=firmware-rex-15709.B TEST=Built FW image correctly. Change-Id: Ia4570d26ee9fd175ed9099bd057cee3c30c95704 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80156 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eran Mitrani <mitrani@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-01-25mb/hp/snb_ivb_laptops: Add SMBIOS slot informationRiku Viitanen
Looking at photos and service manuals, all the WLAN slots are short (half-height) and WWAN slots long (full-height). Change-Id: I894f8216d1b836fbc41423180177bb8651040fbb Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-25mb/google/brya/var/*: Ensure LCD device has a valid addressMatt DeVillier
Some variants added the generic gfx driver with an LCD device without specifying the address, which is required for the backlight controls to be functional under Windows. Add the address value where missing. Address value used (0x80010400) is same as on other Brya variants which did properly set it, and is taken from the ACPI 6.5 spec section B.4.2, _DOD (display output device enumeration), table B-2: - bit 31 = use the ACPI-defined (vs vendor-defined) bit scheme for bits 15-0 - bit 16 = platform firmware can detect the device - bit 10 = display type is internal/integrated flat panel (aka LCD) TEST=build/boot Win11 on google/brya (osiris), verify ACPI backlight controls functional. Change-Id: Id24e330cfb7c993d12665a704e1ca78e2e38874f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-25mb/google/dedede/var/metaknight:Add fw_config probe for multi codecMorris Hsu
and amplifier Compatible headphone codec "ALC5682I-VS" and speaker amplifier "ALC1015Q-VB" BUG=b:183305590 TEST=ALC5682I-VD and ALC1015Q-VB can work normally Change-Id: I4f212f063a1180d7a1c14769f61b0afef7565cad Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79831 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-25mb/google/fizz: Update OEM name listMatt DeVillier
Endeavour and Karma were missing, leading those devices to have empty SMBIOS mainboard names. Fix by adding the missing entries. TEST=build/boot google/fizz (endeavour), verify SMBIOS name correctly shown via dmidecode. Change-Id: I1d4fb2473d27ff5611f9d2b962aae2d6bf6d1da0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80181 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-25mb/google/brox: Switch EC INT and WAKE GPIOsShelley Chen
There was a mistake in the gpio spreadsheet provided by the HW team and the GPIO assignments for the EC INT and WAKE signals got switched from what it was in the schematics. The correct assignments are: GPP_D0 = EC_PCH_INT_ODL GPP_D1 = EC_PCH_WAKE_ODL BUG=b:311450057,b:300690448 BRANCH=None TEST=emerge-brox coreboot Will try to boot OS image on device and see if there are any ec errors. Change-Id: I02057aeb5d82218dbbe4c939d4feb87a4d3da678 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79886 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24mb/google/brya/var/pujjo: Add i2c device for Parade touch screenleo.chou
Add new i2c address 0x24 of touch IC for Parade touch panel. BUG=b:320731709 Test=emerge-nissa coreboot Change-Id: I51bd89beffd912fc147da11d19f38cb44cbe570a Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-01-24*/mem_parts_used.txt: Change Makefile.inc to Makefile.mkMartin Roth
Now that the files are renamed, make sure all references to Makefile.inc are updated as well. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I09e235eecf0c32c80a41bfcbbd3580cce6555e10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-24mb/lenovo to mb/squared: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I4790adb41cb62c8c8dd44261a2926dfb6350955a Reviewed-on: https://review.coreboot.org/c/coreboot/+/80111 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-01-24mb/hp to mb/kontron: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Icfdadfa6705a64655b38aca25be0818ec26429f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80110 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24mb/google/sarien to zork: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ib8a2ae26ed4380592d15e1a7b2d682639413af01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-01-24mb/google/oak to rex: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I85cda24aa7dec82d23e8a321dac03ec737f4c503 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80108 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24mb/google/gale to nyan_blaze: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I92f8bd7e1c9fc6e4120fb94c2299a266304e19de Reviewed-on: https://review.coreboot.org/c/coreboot/+/80107 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24mb/google/daisy to foster: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I134acc26c0a79d974a6dd0a3b257f961db7e2d86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80106 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-24mb/google/rex/var/rex: Set TCC to 100°CSumeet Pawnikar
Set tcc_offset value to 10 in devicetree for Thermal Control Circuit (TCC) activation feature for rex. BUG=b:270664854 TEST=Build, boot and test on rex with value under sysfs /sys/bus/pci/devices/0000:00:04.0/tcc_offset_degree_celsius Change-Id: I9012984016ab3213102214025d6d8dc07c5d8974 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79992 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Peter Ou <peter.ou@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24mb/google/asurada to cyan: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5855f49984db59d786decad6142e3525b146a573 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80105 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-01-24mb/51nb to mb/gigabyte: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I422cb475723006ca42be93508fb0bf4b1e4e84d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80104 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-23mb/google/brox: Move cnvi to overridetreeShelley Chen
We need to disable the cnvi device when pcie wifi is enabled, so need to use the FW_CONFIG defined in the overridetree for this. BUG=b:311450057,b:300690448,b:319188820 BRANCH=None TEST=This will be tested on the device when received Change-Id: If9e861db37e321fd69c09f9b4aafa2e212f92caa Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79898 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-23mb/google/brox: Enable WLAN on root port 5Shelley Chen
BUG=b:311450057,b:300690448,b:319188820 BRANCH=None TEST=test on device with lspci & make sure can see the Intel Network controller Change-Id: I361bef13ebd073b6fccb729a1960d3832cf2681a Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-01-22mb/google/brya: Create xol variantYH Lin
Create the xol variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:319506033 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_XOL Change-Id: Id60c50b70c9ab53d62ad48cfc15462f2410f9f02 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80145 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-22mb/hp/snb_ivb_laptops: Remove superfluous comments about PCI devicesFelix Singer
Since all devicetrees from hp/snb_ivb_desktops are using the reference names for PCI devices now, remove the equivalent comments documenting their function. Change-Id: I42b680f753fb2ed8bc0ae8b5bfb20ee8a7cf8bdb Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80049 Reviewed-by: Riku Viitanen <riku.viitanen@protonmail.com> Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-22mb/hp/snb_ivb_laptops: Convert remaining PCI numbers into referencesFelix Singer
Change-Id: I58e5dfa57856e80d1a5e4a6fab0b2523301fa8f2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80048 Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Riku Viitanen <riku.viitanen@protonmail.com>
2024-01-22mainboard/Kconfig: add 24MB ROM sizeMaciej Pijanowski
16MB + 8MB flashes are used on some boards, such as Lenovo M920 Change-Id: Iac6e076ed17d7e944cc829ff0cb27ede50c6f7db Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80072 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
2024-01-22mb/google/dedede/var/galtic: Correct name for mem-part K4U6E3S4AA-MGCRDaniel Peng
Repo sync code recently, run command as memtioned in TEST and found the changed for the auto-gen files. Then correct the memory typo from K4UBE3D4AA-MGCR to K4U6E3S4AA-MGCR, and no new for the used hex file. BUG=b:320181366 BRANCH=firmware-dedede-13606.B TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\ part_id_gen.go JSL lp4x \ src/mainboard/google/dedede/variants/galtic/memory/ \ src/mainboard/google/dedede/variants/galtic/memory/\ mem_parts_used.txt" Change-Id: I7c158eb7b4455cde839a335913e6a18895c12b41 Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79976 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-20mb/purism/librem_skl: Fix pcie_rp5 in device tree (WLAN)Jonathon Hall
WLAN has always been pcie_rp5, there is nothing on pcie_rp1. RP5 gets promoted to function 0 (RP1's function) since no earlier functions are enabled. This simplifies later refactoring that will handle the FSP root port enable flags (which were correctly set already) using the device tree enables. Test: Boot librem_13v2 and verify WLAN is enabled. Change-Id: I7a724a01b5f171a16de83ff6122630e2d66557c1 Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-20soc/amd/phoenix/Kconfig: factor out FSP-specific optionsFelix Held
Split the SOC_AMD_PHOENIX Kconfig option into SOC_AMD_PHOENIX_BASE that selects the non-FSP-specific options and SOC_AMD_PHOENIX_FSP that selects both SOC_AMD_PHOENIX_BASE and the FSP-specific options. This will help to separate the FSP-specific from the FSP-agnostic code. The mainboards using this SoC now select SOC_AMD_PHOENIX_FSP instead of SOC_AMD_PHOENIX. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5e95fbfd9d16930ba3e6cc497557d61adba5a6fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/79983 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-20mb/google/brox: enable WIFI_SARShelley Chen
Add get_wifi_sar_cbfs_filename(). This function uses the FW_CONFIG for WIFI to choose the right wifi_sar hex file. Below is the file mapping: wifi_sar_0.hex = wifi6 wifi_sar_1.hex = wifi7 BUG=b:319302319 BRANCH=None TEST=emerge-brox coreboot chromeos-bootimage Change-Id: I212c80412141e7770a512bd8ccf4111963bab395 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80085 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-19mb/hp/snb_ivb_desktops: Remove superfluous comments about PCI devicesFelix Singer
Since all devicetrees from hp/snb_ivb_desktops are using the reference names for PCI devices now, remove the equivalent comments documenting their function. Change-Id: I0974052c6c18f54b588d296c5c5d11e930f0fcd7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80047 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-19mb/hp/snb_ivb_desktops: Convert remaining PCI numbers into referencesFelix Singer
Change-Id: I31e348ba5954bc463f43e769ddb4aed413faf193 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-19mb/lenovo/x230: Remove superfluous comments related to PCI devicesFelix Singer
Since all devicetrees from lenovo/x230 are using the reference names for PCI devices now, remove the equivalent comments documenting their function. Change-Id: Ia06f976ef1439377ff22149044feaa3463d2aeb8 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-19mb/lenovo/t430: Remove superfluous comments related to PCI devicesFelix Singer
Since all devicetrees from lenovo/t430 are using the reference names for PCI devices now, remove the equivalent comments documenting their function. Change-Id: I84f432e89c41a02115715f7f1b56123dd0d81171 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-19mb/lenovo/t530: Remove superfluous comments related to PCI devicesFelix Singer
Since all devicetrees from lenovo/t530 are using the reference names for PCI devices now, remove the equivalent comments documenting their function. Change-Id: I5ba08843506bc22136aea42ac37936a4f5cad5ce Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-19mb/siemens/chili: Use chipset dt reference namesFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous. Change-Id: Ic3a4c85ec6bfdc858f9b6f79b114cf612ad3a153 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80022 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-01-19mb/purism/librem_cnl: Use chipset dt reference namesFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous. Change-Id: I87cec9026bcb621ceb7eae51f65ae35bc31d584a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
2024-01-19mb/purism/librem_l1um_v2: Use chipset dt reference namesFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous. Change-Id: Id592241a1dc33559115800da10a57a5fc10867f9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
2024-01-19mb/protectli/vault_cml: Use chipset dt reference namesFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous. Change-Id: I76ec42fccfa42bbe3943e048968a76eec3584ee8 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2024-01-19mb/dell/snb_ivb_workst: Remove superfluous comments about PCI devicesFelix Singer
Since all devicetrees from dell/snb_ivb_workstation are using the reference names for PCI devices now, remove the equivalent comments documenting their function. Change-Id: Iac70aa25dd324e1ed5fa0bb995eb995ec3545715 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2024-01-19mb/dell/snb_ivb_workst: Convert remaining PCI numbers into referencesFelix Singer
Change-Id: I9c6d931d5d5650eb5818116050f9f599a815c315 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80052 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-19mb/starlabs/starbook/cml: Use chipset dt reference namesFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous. Change-Id: Ia004de6606a1685822d5567123887c60d89e3119 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2024-01-18mb/google/brya: Drop primus4es boardJakub Czapiga
Primus4es board is no longer supported thus drop it from the tree. TEST=Build all Brya boards in CrOS-SDK - Primus4ES not built. No negative impact observed. Change-Id: I0502b2eed6f80d648b422c8d1622d504a6c93822 Signed-off-by: Jakub Czapiga <czapiga@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-18mb/google/dedede/var/pirika: Add initial fw_config configuration settingDaniel Peng
1. Describe the FW_CONFIG probe for the settings for Palutena. - WIFI_SAR_ID_0 for AW Wi-Fi module AW-CM421NF - WIFI_SAR_ID_1 for Intel Wi-Fi module AX211NGW 2. In contrast to the AW Wi-Fi module, the Intel Wi-Fi module needs to load a SAR table in dedede platform. 3. For Palutena project, the SKU ID segment of Palutena is set for "0x350000~0x35FFFF". BUG=b:319792428 BRANCH=firmware-dedede-13606.B TEST=build pass Change-Id: Ic4f38928d24c4398d90df226cfe0788a30075bf2 Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79930 Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
2024-01-18mb/google/nissa/var/craaskov: Add fan performance controlRex Chou
Add 6w and 15w fan performance control. BUG=b:318454915 TEST=emerge-nissa coreboot chromeos-bootimage Thermal team test pass. Change-Id: If21baa2f6f9bcd527cec2bced27c5fb2cd607830 Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79988 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-18mb/google/nissa/var/craaskov: Modify 6W and 15W DPTF parametersRex Chou
1. Modify 6w/15w DPTF parameters based on b:290705146#comment41. 2. 6W MSR power limit_1 power (Watts) increase to 20. 3. 15W MSR power limit_1 power (Watts) increase to 20. BUG=b:290705146 TEST=emerge-nissa coreboot chromeos-bootimage Thermal team test pass. Change-Id: I15fa4b8f7c7088ff56da6493659ae45572913b5a Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-01-18mb/google/brox: Fix user facing camera acronymShelley Chen
I got confused and used UFS (User Facing Side) for the User Facing Camera (UFC) in the FW_CONFIGs. Change references of the camera from UFS --> UFC. BUG=b:300690448 BRANCH=None TEST=None. The camera has not been enabled yet. Change-Id: I4f8240ae51aad1e077f325a9eab5a2a92f1402cb Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79997 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>