soc/intel/xeon_sp/smihandler: Lock SMM_FEATURE_CONTROL on all sockets

Remove hardcoded B:D:F numbers for the first socket and pass the PCI
addresses to be locked within SMM by using the smm_pci_resource_store.

This allows to lock down SMM on all sockets without knowing the actual
bus topology or PCI segment group at compile time where the UBOX devices
reside on.

Tested: SMM is locked on all 4 sockets instead of just one.

Change-Id: Ica694911384005681662d3d7bed354a60bf08911
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80247
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

7 files changed, 50 insertions, 1 deletions

diff --git a/src/mainboard/bytedance/bd_egs/ramstage.c b/src/mainboard/bytedance/bd_egs/ramstage.c
index dd19fc6a48..1e20bacd1c 100644
--- a/src/mainboard/bytedance/bd_egs/ramstage.c
+++ b/src/mainboard/bytedance/bd_egs/ramstage.c
@@ -1,6 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <cpu/x86/smm.h>
 #include <soc/ramstage.h>
+#include <soc/smmrelocate.h>
 #include <soc/gpio.h>
 
 #include "gpio.h"
@@ -23,6 +25,11 @@ void mainboard_override_fsp_gpio(void)
 	gpio_configure_pads(pads, pads_num);
 }
 
+void smm_mainboard_pci_resource_store_init(struct smm_pci_resource_info *slots, size_t size)
+{
+	soc_ubox_store_resources(slots, size);
+}
+
 struct chip_operations mainboard_ops = {
 	.init = mainboard_chip_init,
 };
diff --git a/src/mainboard/ibm/sbp1/ramstage.c b/src/mainboard/ibm/sbp1/ramstage.c
index 78db8c9fc8..d748b1b176 100644
--- a/src/mainboard/ibm/sbp1/ramstage.c
+++ b/src/mainboard/ibm/sbp1/ramstage.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-
+#include <cpu/x86/smm.h>
 #include <soc/ramstage.h>
+#include <soc/smmrelocate.h>
 
 #include "include/spr_sbp1_gpio.h"
 #include <bootstate.h>
@@ -33,4 +34,9 @@ static void finalize_boot(void *unused)
 	gpio_output(GPPC_C17, 0);
 }
 
+void smm_mainboard_pci_resource_store_init(struct smm_pci_resource_info *slots, size_t size)
+{
+	soc_ubox_store_resources(slots, size);
+}
+
 BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL);
diff --git a/src/mainboard/intel/archercity_crb/ramstage.c b/src/mainboard/intel/archercity_crb/ramstage.c
index 38bf576dcd..be3cc90918 100644
--- a/src/mainboard/intel/archercity_crb/ramstage.c
+++ b/src/mainboard/intel/archercity_crb/ramstage.c
@@ -1,3 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <cpu/x86/smm.h>
 #include <soc/ramstage.h>
+#include <soc/smmrelocate.h>
+
+void smm_mainboard_pci_resource_store_init(struct smm_pci_resource_info *slots, size_t size)
+{
+	soc_ubox_store_resources(slots, size);
+}
diff --git a/src/mainboard/intel/cedarisland_crb/ramstage.c b/src/mainboard/intel/cedarisland_crb/ramstage.c
index d2ab2a7b57..ba8807b729 100644
--- a/src/mainboard/intel/cedarisland_crb/ramstage.c
+++ b/src/mainboard/intel/cedarisland_crb/ramstage.c
@@ -1,6 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <cpu/x86/smm.h>
 #include <soc/ramstage.h>
+#include <soc/smmrelocate.h>
+
 #include "include/gpio.h"
 
 void mainboard_silicon_init_params(FSPS_UPD *params)
@@ -8,3 +11,8 @@ void mainboard_silicon_init_params(FSPS_UPD *params)
 	/* configure Lewisburg PCH GPIO controller after FSP-M */
 	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
 }
+
+void smm_mainboard_pci_resource_store_init(struct smm_pci_resource_info *slots, size_t size)
+{
+	soc_ubox_store_resources(slots, size);
+}
diff --git a/src/mainboard/inventec/transformers/ramstage.c b/src/mainboard/inventec/transformers/ramstage.c
index 44539645a8..bc61a90df4 100644
--- a/src/mainboard/inventec/transformers/ramstage.c
+++ b/src/mainboard/inventec/transformers/ramstage.c
@@ -1,6 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <cpu/x86/smm.h>
 #include <soc/ramstage.h>
+#include <soc/smmrelocate.h>
 #include <sprsp_gpio.h>
 #include <intelblocks/cse.h>
 #include <memory_info.h>
@@ -35,3 +37,8 @@ void mainboard_silicon_init_params(FSPS_UPD *params)
     /* configure Emmitsburg PCH GPIO controller after FSP-M */
 	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
 }
+
+void smm_mainboard_pci_resource_store_init(struct smm_pci_resource_info *slots, size_t size)
+{
+	soc_ubox_store_resources(slots, size);
+}
diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c
index c24d004ed0..f846055fc2 100644
--- a/src/mainboard/ocp/deltalake/ramstage.c
+++ b/src/mainboard/ocp/deltalake/ramstage.c
@@ -4,6 +4,7 @@
 #include <commonlib/bsd/helpers.h>
 #include <console/console.h>
 #include <cpu/cpu.h>
+#include <cpu/x86/smm.h>
 #include <cpxsp_dl_gpio.h>
 #include <device/device.h>
 #include <device/pci_def.h>
@@ -16,6 +17,7 @@
 #include <security/intel/txt/txt.h>
 #include <smbios.h>
 #include <soc/ramstage.h>
+#include <soc/smmrelocate.h>
 #include <soc/soc_util.h>
 #include <soc/util.h>
 #include <stdio.h>
@@ -335,6 +337,11 @@ struct chip_operations mainboard_ops = {
 	.final = mainboard_final,
 };
 
+void smm_mainboard_pci_resource_store_init(struct smm_pci_resource_info *slots, size_t size)
+{
+	soc_ubox_store_resources(slots, size);
+}
+
 bool skip_intel_txt_lockdown(void)
 {
 	static bool fetched_vpd = 0;
diff --git a/src/mainboard/ocp/tiogapass/ramstage.c b/src/mainboard/ocp/tiogapass/ramstage.c
index c69322b77a..a07edb80e8 100644
--- a/src/mainboard/ocp/tiogapass/ramstage.c
+++ b/src/mainboard/ocp/tiogapass/ramstage.c
@@ -1,8 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
+#include <cpu/x86/smm.h>
 #include <drivers/ipmi/ipmi_ops.h>
 #include <drivers/ocp/dmi/ocp_dmi.h>
 #include <soc/ramstage.h>
+#include <soc/smmrelocate.h>
 
 extern struct fru_info_str fru_strings;
 
@@ -176,6 +178,11 @@ static void mainboard_final(void *chip_info)
 {
 }
 
+void smm_mainboard_pci_resource_store_init(struct smm_pci_resource_info *slots, size_t size)
+{
+	soc_ubox_store_resources(slots, size);
+}
+
 struct chip_operations mainboard_ops = {
 	.enable_dev = mainboard_enable,
 	.final = mainboard_final,