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On this mainboard there are legacy PCI devices connected behind a
PCIe-2-PCI bridge. Not all clock outputs of this bridge are used. This
patch disables the unused PCI clock outputs on the XIO2001 bridge.
Change-Id: Iedbf0abfa554e0a6ad5b1d1741f4e9934103d171
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63931
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Follow the Kinox_schematic_R01_20220418.pdf to set memory SMBus
addresses to 0x52, 0x50.
BUG=b:231398371
TEST=Build and boot to OS with either 1 or 2 DIMM slots populated.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I32bb4f62a6b8a485ac757a60f5d16adb69109e2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This area is used for storing AP RO verification information.
BRANCH=none
BUG=b:227801913
TEST=build and boot nivviks
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: If5c03aca56e659d61c31613b284a55d0eba0d843
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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This variant uses all three EHL Ethernet GbE-TSN Controller so enable
the TSN GbE driver in order to set the needed MAC addresses. The
required function to retrieve a valid MAC address was already implement
in the common mainboard.c for mc_ehl.
TEST:
- Boot mc_ehl2 into Linux and check MAC addr via 'ip a'
Change-Id: Ia052c44feb606f9e1d31d047f2acc67e3226a895
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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TSN runs in SGMII mode on this mainboard. This requires setting the link
speed to 1 Gbps.
Change-Id: I9f1da971b4de5671d6d38be6dbc50edbbe20d157
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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This mainboard uses all three internal Ethernet GbE-TSN controllers. Two
of them are initialized by the Programmable Services Engine (PSE).
This patch enables the Serial Gigabit Media Independent Interface
(SGMII) mode for GbE PSE0 and GbE PSE1. By setting PCH PSE DMA pins to
host owned, the IO is under control of the IA processor cores through
system software.
TEST:
- Boot mc_ehl2 into Linux and check inet addr via 'ip a'
Change-Id: I74e660548b2c44d5dbdb6023d5a36cfdd7e96f43
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Both option-HDMI and option-DP use the same setting of vbt,
and ABSENT is just physically remove option board from motherboard,
so it just need one vbt, and it don't need the fw_config to decide
which vbt will be return.
BUG=b:231769131
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I1f8cdcbc05ed3bc689d29261e4fd4d700326dce8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Both option-HDMI and option-DP use the same setting of vbt,
and ABSENT is physically remove option board from motherboard,
so set default vbt has option-DP setting and only return it.
BUG=b:231769131
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I440143dabcf04c103f2a4420a7e4afb8ec12ec1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Use the existing definitions from FspUsb.h instead of magic values for
the ComboPhyStaticConfig settings in the mainboard's devicetree.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2707d017909b7516e5d8711c8f4e2914165ed10d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The commentary was wrong, write_protect_state() is only called
in ramstage at the moment, and only if MRC_SETTINGS_PROTECT is
selected.
Implementation of get_gpio() eventually does the MMIO read, so
BOARD_GOOGLE_CYAN was not a special case.
Change-Id: I96ca871110bcf2fc1485bd042ed137d51b822a20
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ic59cccdf0fb88fc71a440170ee40b73dd8736a33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Nivviks uses CNVi WLAN, so disable the PCIe-related GPIOs.
BUG=b:218929856
TEST=Boot to OS on nivviks and check that WLAN still works.
Change-Id: I68f12490b0f09658e1307828b0e4488504f50e61
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Enable either eMMC, NVMe or UFS based on fw_config. NVMe and UFS are
only supported on nirwen, an additional nissa variant based on nivviks
and sharing the nivviks coreboot target.
BUG=b:218929856
TEST=Boot to OS on nivviks to check that eMMC still works. NVMe and UFS
will be tested once nirwen boards are available.
Change-Id: Ibdb122ef35920c962d7bd9f3f238a5d548112282
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Nirwen is an additional nissa reference board which is almost identical
to nivviks, so is reusing the nivviks coreboot variant. However, there
are two GPIO changes, so update the GPIO tables to handle these based on
board_id.
nivviks:
GPP_D6 -> WWAN_EN
GPP_E13 -> NC
nirwen:
GPP_D6 -> SSD_CLKREQ_ODL
GPP_E13 -> WWAN_EN
BUG=b:218929856
TEST=Boot to OS on nivviks
Change-Id: I494ed127714069a8f36d16d11ca4e8a1f3d37827
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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BUG=b:218929856
TEST=Boot to OS on nivviks. Set fw_config in CBI and check that pen
garage is enabled/disabled as expected.
Change-Id: I2c3f5403e0f11443ad3647b8c4ae624f0b88a111
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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BUG=b:218929856
TEST=Boot to OS on nivviks. Change fw_config in CBI and check that WFC
is enabled/disabled as expected.
Change-Id: Iac4bb358d904579376e0810f8c2644b3bde4f1e6
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This patch sets the RComp resistor values to default values needed.
BUG=b:231202733
TEST=Build and boot nivviks and nereid. Verify the Rcomp values are set
to default values from debug FSP log.
[SPEW ] Updating Rcomp Targets:
[SPEW ] RcompTarget[RdOdt]: 48
[SPEW ] RcompTarget[WrDS]: 30
[SPEW ] RcompTarget[WrDSCmd]: 20
[SPEW ] RcompTarget[WrDSCtl]: 20
[SPEW ] RcompTarget[WrDSClk]: 20
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I2c7a54c49e282446ece77ca406951782282a009a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Enable DRIVERS_GENESYSLOGIC_GL9750 support for Crota.
BUG=b:231686917
TEST=USE="project_crota emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: Ie10167e48256a61801b2623ae4500db5e67e73cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change ELAN touchscreen i2c address to 0x16 and change HID to ELAN900C
BUG=b:231684121
TEST=local build and tested with ELAN touch screen
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: Ide005a0681e236c3102090c1c36ab81926849000
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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BUG=b:218929856
TEST=Boot to OS on nivviks. Change fw_config in CBI and check that SD
card is enabled/disabled as expected.
Change-Id: Idcf38343bb290b1eff6a2e440f868b03acba3288
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Ti50 firmware versions below 0.0.15 don't support the firmware_version
register and trying to access it causes I2C errors. Some nissa boards
are still using Ti50 0.0.12, so add a workaround Kconfig to skip reading
the firmware version and select it for nissa. The firmware version is
only read to print it to the console, so it's fine to skip this. This
workaround will be removed once all ODM stocks are updated to 0.0.15 or
higher.
A similar workaround Kconfig was added in CB:63011 then removed in
CB:63158 which added support for separate handling of Cr50 and Ti50.
But we actually still need this workaround until all Ti50 stocks are
upgraded to 0.0.15 or higher.
BUG=b:224650720
TEST=Boot to OS on nereid with Ti50 0.0.14
Change-Id: Ia30d44ac231c42eba3ffb1cb1e6d83bb6593f926
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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With GPIO_DRIVER_LOCK kernel driver can't change to IRQ. Thus, we need
to set it as INT in coreboot to make the IRQ work.
BUG=b:223476974
TEST=evtest work as expected.
Input driver version is 1.0.1
Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100
Input device name: "PRP0001:00"
Supported events:
Event type 0 (EV_SYN)
Event type 5 (EV_SW)
Event code 15 (SW_PEN_INSERTED) state 0
Properties:
Testing ... (interrupt to exit)
Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1
Event: -------------- SYN_REPORT ------------
Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I5f9fdfb2622b4b955da216119e74c6f7d5795d36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Specify the USB PHY settings in the devicetree instead of relying on the
FSP defaults. The USB PHY configuration for Chausie are taken from the
internal UEFI code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8cc38e6e26d53802773fe3c405415de15cca98a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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With this patch, the ThinkLight on the ThinkPad T60 can be controlled
through the OS. This was initially done for the X201 in f63fbdb6:
mb/lenovo/x201: Add support for ThinkLight.
After applying this patch, the light can be controlled like this:
echo on >/proc/acpi/ibm/light
echo off >/proc/acpi/ibm/light
Or through sysfs at /sys/class/leds/tpacpi::thinklight
Change-Id: I47f878533d36857d002d2e2605cc8bc7e1d960c9
Signed-off-by: Stefan Ott <stefan@ott.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Found using:
diff <(git grep -l '#include <cf9_reset.h>' -- src/) <(git grep -l 'RST_CNT\|FULL_RST\|RST_CPU\|SYS_RST\|do_system_reset\|do_full_reset\|cf9_reset_prepare\|system_reset\|full_reset' -- src/) |grep "<"
Change-Id: I093d8412e14ce81b462fb9a7ccb3a2a93ae760a6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
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Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Id4550842a31f89e7eb6c1543512794eeb5e24937
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
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Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ie1d2965b384e5653958f7f8503c62b8a16fa7bc1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
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Change-Id: I8d55fc93f6ec413d0cbcea2f8e0a90a76f1803cd
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
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Floats are not allowed in coreboot.
As the compiler rounded down the value, do so in the code too as this
is a known good value.
Change-Id: I4e180d4cb8e0e1aa68186bfc1daffdc5c339dc64
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Init basic override devicetree based on schematics
BUG=b:224423318
TEST=FW_NAME="osiris" emerge-brya coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ie69957b39b5c299846c64f67fb29207cf858e50e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64199
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update initial gpio configuration for osiris
BUG=b:224423318
TEST=FW_NAME=osiris emerge-brya coreboot
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I014bd7ebf94bf687362f7ee734cadfa83f3bde2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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Commit f89cb241eec introduced a regression where the RcompTarget was
not updated according to the SPD.
Change-Id: I07715224b11937604b107e370d957745b245ddd9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64239
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable MKBP (Matrix Keyboard Protocol) interface for all skyrim family
to use for buttons and switches. Disable TBMC (Tablet Mode Switch
device), as it is not needed anymore.
BUG=b:230682161
TEST=manual test on Skyrim:
Volume Up/Down and Power buttons, Tablet Mode switch
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I79ee2fdbb325491c9e3df5b9cff0c0c1181a7001
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
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This board never made it to production, and development on it has long
since stopped; it is a maintenance burden, therefore drop it from the
tree.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ieb12a95ff56c3437cb88df8ef3f6ae115ad53446
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Replace TPM_GOOGLE_CR50 with TPM_GOOGLE_TI50.
BUG=b:232066387
TEST=emerge-corsola coreboot
BRANCH=none
Change-Id: I0cc787b3104bc47f6f856497bbc0870e0519dc28
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64252
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add Fibcom FM101-GL USB WWAN configuration with the required power
sequence as suggested in Fibocom FM101-GL Hardware Guide V1.0.
BUG=b:227761300
TEST=Build and boot to OS in Skyrim. Ensure that the WWAN module is
enumerated in the output of lsusb.
localhost ~ # lsusb
Bus 004 Device 003: ID 2cb7:01a2 Fibocom Wireless Inc. Fibocom FM101-GL Module
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I39f8e7204e31d9a4d093aacd838a18e6d2f44970
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64004
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In Skyrim, USB-A port and WWAN modules are connected to the SoC USB
ports through an external hub. Update the USB configuration in the
devicetree accordingly. Enable the ACPI driver for external USB hub.
BUG=b:227761300
TEST=Build and boot to OS in Skyrim. Ensure that the hub and USB-A ports
are enumerated correctly in the output of lusub command.
Change-Id: Ibf6a3da8add7361fc50adcf7c62e46df234685dc
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63586
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We found HDMI-DDIA didn't get hot plug detection,so set GPP_E14
as the default value to let HDMI-DDIA get hot plug detection.
BUG=b:231769129
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I1b5cc1465fec519be4bbe5e027be0dc25815f4fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64138
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add related settings for synaptics touchpad.
BUG=b:229938024
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I3b3bb5cec56901dadaaa1c5699781df45c237257
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Enable the max charge feature for cml, as the EC supports it since
Star Labs EC firmware 1.06.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I779a686960b63025fb5f40e826ed117f402a0b2a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64093
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Using CLKREQ 4 and CLKSRC 4
BUG=b:210970640
BRANCH=NONE
TEST=emerge-draco coreboot chromeos-bootimage
Change-Id: Ie0e362013551036a03ef69a98c6f1793e0e75c41
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The first target for the add_intermediate targets is always
$(obj)/coreboot.pre.
Change-Id: Iea2322ca1abd43900f3631b7965f07fed4235ca0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
|
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BUG=b:216594621
BRANCH=brya
TEST=build pass and SAR table be changed according to tablet/ desktop mode
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I62265e8931da48d20cf41e0c91ccb1a5b4bc1167
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Disable all of the TBT devices in devicetree since kinox doesn't support
thunderbolt. The change also need to disable TBT in fitimage
(chrome-internal:4731094).
BUG=b:231654363
TEST=Build and run on DUT.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I944680dd1f41ac6f375015a3a138eb00c41b58a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Correct tcss_usb3_port to meet Moli's schematic design.
BUG=b:220814038
TEST=emerge-brask coreboot
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: Ib8faa4a353d8d617fce7aa70922bf027e6e11b38
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Clang complains about this.
Change-Id: I421d6c5daa373d1537e4ac2243438e7f1f6208d1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63067
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Iba80c4a5960c6fb59f542b33e8e769576ccfed59
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Enable BT offload of NAU88L25B on Moli with fw_config NAU88L25B_I2S.
BUG=b:220814038
TEST=emerge-brask coreboot,
Check BT offload enabled in CPU log and audio works.
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I72d91d2dafffa7d9604b7dd3d697cb3b2b04b152
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Crota360 is using a Cirrus CS42L42 for its audio codec; it requires the
reset pin to be deasserted in ramstage for proper power sequencing.
BUG=b:230074351
BRANCH=none
TEST=build coreboot without error
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: Ica3467fbc8639526bee071d56af854de5e07091e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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With the PMC set to hidden, on certain Operating Systems,
including ZorinOS 16 and Manjaro 21.2.5, it would get stuck
at a black screen when exiting from S3.
With the PMC set to on, this issue no longer occurs.
Signed-off-by: Stephen Edworthy <stephen@starlabs.systems>
Change-Id: I0cf1be7f6919d974614f2196a0eb611cc40abe3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
|
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Currently coreboot will hang on ASPM on pcie_rp 6,
so disable ASPM to let it go into kernel.
BUG=b:231400217
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I79a80d97d168f40e58774e5652967d659daa323c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
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Enable CnviBtAudioOffload UPD from Intel Guideline
BUG=b:230418589
TEST=emerge-byra coreboot and verified pass
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I7ac54156cc4a8d824ed1c549d66fc369698a352c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add an enum for `DdiPortXConfig` devicetree options. Note that setting
these options to zero does not disable the corresponding DDI port, but
instead indicates that no LFP (Local Flat Panel, i.e. internal LCD) is
connected to it.
Change-Id: I9ea10141e51bf29ea44199dcd1b55b63ec771c0a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
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This patch removes unused i2c7 settings. Accroding to EVT schematic,
i2c7 is reserved for AMP but resistors are unstuffing.
BUG=b:229334701
TEST=emerge-brya coreboot chromeos-bootimage && $powerd_dbus_suspend
&& checks EC log and ensures the DUT could enter s0ix.
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: Ifc1e0085064a13149ebc7e70184d1f40462e0fff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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To meet LTE's RF Specific Absorption Rate (SAR) certification, we add a
Semtech Smart Proximity Sensor (P-Sensor) SX9324. P-Sensor connects
EC of I2C 5 bus and GPIO D22, D23, as well as, SoC of GPIO E11, refer
to mainboard schematic.
BUG=b:213549229
BRANCH=dedede
TEST=emerge-dedede coreboot
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: If172d13aa62503547227adf91f049ea50b948888
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63652
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds support for power sequencing of the Nvidia GN3050 for
agah, which uses PCH GPIOs to control the 5 power rails required for
the GPU. The GPU is power sequenced on during mainboard
initialization, then it is enumerated on the PCI bus and its resources
are assigned. This GPU will be used in a sort of "hybrid graphics"
mode, therefore during finalization, since its PCI BARs are saved into
ACPI memory and the GPU is not required upon initial boot, the GPU is
power sequenced off.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I1072be12ef58af5859e2a2d19c4a9c1adc0b0f88
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Crota360 is using a Cirrus CS42L42 for its audio codec; it
requires the reset pin to be deasserted in ramstage for proper
power sequencing.
BUG=b:230074351
BRANCH=none
TEST=build coreboot without error
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: Ie942b3c553823510dfa6f6fb70a7b13881fc4c14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Fix power sequence according to datasheet:GL9750S-OIY04 rev1.24.
BUG=b:229181624
TEST=Build and boot to OS in Skyrim. Ensure that the SD Controller
and SD Card are enumerated fine.
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: Iea729d43d10a3f8353b4fe540146d00975f4d422
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Functions that are intended to override weak ones defined in the
baseboard should not also be declared weak, otherwise how would
the linker know which copy to keep.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ia2ceee77d00a5baa915fd1f306d76e79aa609e65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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|
Based on the schematic bernadino 14 adl-p 20220318.pdf to set
GPP_D16 to enable webcam power
BUG=b:230289857
BRANCH=none
TEST=build and notice log kernel v5.10
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I01c73006d24b00be348655334232bea5eeb312e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add entries to the devicetree override for brya0 and enable the Kconfig
to ensure the Chrome OS EC Mux driver is build tested.
BUG=b:208883648
TEST=None
BRANCH=None
Change-Id: Icf841cd32587f6bd98b15747283b0d331f013532
Signed-off-by: Prashant Malani <pmalani@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Use common ASL defines for POST code handling.
Change-Id: I5b4c11860a8c33e56edaea0f6de378cbaa63a8c5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63989
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move ASL POST code declarations into a common file to avoid redundancy.
Also, provide a dummy implementation when `POST_IO` is not enabled, as
the value of `CONFIG_POST_IO_PORT` can't be used.
Change-Id: I891bd8754f10f16d618e76e1ab88c26164776a50
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
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Align POST code ASL elements with existing code in newer southbridges.
The main differences are that `NoLock` is changed to `Lock`, and that
names have been changed. The lock type change should not be a problem
because the field is only used once in the _PTS method.
Change-Id: I8aa362007ff98e5b42add6c7908a8f7beac2222b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
|
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Change-Id: Ia0550a115d75183cd72e478ae739731001febe22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Per Microsoft's spec for HID over I2C [1], interrupts must be level
triggered. Switch GPIOs and the devicetree config to conform to this.
Touchpad and multitouch gestures were already working, so no behavior
changes are observed in normal use.
[1]: http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
Change-Id: I485e616ae00e10bc3620ff3fa1fc1e903653c5cc
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Kinox keeps 65W barrel jack for Intel Pentium/Celeron SOC. Considering
the dynamic loading of 65W adapter, it can up to 130% with 20ms. Update
power settings to below for preventing blowing out the adapter.
- Psys_Pmax 135W
- PL2 39W
- PL4 72.5W
- Psys_PL2 65W
- Psys_imax_ma 6750ma
- bj_volts_mv 20000mv
For Intel Core processor, Kinox will use 90W barrel jack. Modify default
power settings as below.
- Psys_Pmax 135W
- PL2 55W
- PL4 123W
- Psys_PL2 90W
- Psys_imax_ma 6750ma
- bj_volts_mv 20000mv
BUG=b:213417026, b:222599762
TEST=emerge-brask coreboot
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I6df2a17969067f8242519f7fd4ffd08a682fe3e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hou-hsun Lee <hou-hsun.lee@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Enable EC keyboard backlight for osiris.
BUG=b:224423318
TEST=FW_NAME=osiris emerge-brya coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I501155531bff8c59641e88ea61aab623cb9a1868
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
|
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Agah USB-C port 0 is non-retimer port and it connects to TCSS port 2.
Bit[5:4] is for TCSS Port 2, so re-configure "TcssAuxOri" to 0x10 and "typec_aux_bias_pads" to 2 to correct the port.
BUG=b:210970640
BRANCH=NONE
TEST=emerge-draco coreboot chromeos-bootimage
Change-Id: I2d26777e850187aee0b676de13dff915474fed7b
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
This allows for the option to persist the serial number and other
device-specific information when switching from stock ChromeOS and
upstream coreboot firmware images.
Change-Id: I12711f678259390fe9e31b7ca728344cc2875b0e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
- Fix Goodix hid and hid offset
BUG=b:230415144
BRANCH=brya
TEST=build and boot without error
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I5a5c1cdca0cec15d65fe62a3104652d2d347fd54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
The ITE EC used on Nereid can take a long time to update, and especially
too long to erase. There is a 1 second timeout enforced on the EC erase
command, but Nereid's IT81302 will typically take about 5 seconds to
complete erase, and could take as long as 30.
Since this affects any Nissa variant using an ITE EC and it's nice to
make the entire Nissa project consistent, this change disables early
sync for all Nissa boards.
BUG=b:222987250
TEST=EC software sync is no longer attempted (and thus does not fail) on
Nereid.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change-Id: I55d36479e680c34a8bff65776e7e295e94291342
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
This patch enables V1p05 and Vnn external bypass VRs for Banshee.
BUG=b:207116793
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Idb56890db40f90f163d8dadf5bf7c7335469771a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63860
Reviewed-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch enables TBT PCIe root port 3.
BUG=b:230464233
TEST=emerge-brya coreboot chromeos-bootimage and $lspci -t and
ensure 07.3 is in the list.
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: I118facd45f54c8ed2843a85c0aa61b6571077a5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Read the EEPROM to detect the DDI type.
BUG=b:225139014
TEST=Boot chausie and correctly detect display card type
Change-Id: I3ddd8789e75d5da2ea1e6ce9a81e5ebb2cf3c007
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Update DPTF Policy and temperature sensor values from thermal team.
BRANCH=dedede
BUG=b:204229229
TEST=on beadrix, verified by FW_NAME=beadrix emerge-dedede coreboot.
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: I34c1298dc8412121f8688842bb8d69d7fafa46f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
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Revert CdClock setting and use default value 0xff.
Previous problem was fixed by Jasperlake FSP in version 1.3.09.31,
so we can use the original CdClock setting in baseboard.
BUG=b:206557434
BRANCH=dedede
TEST="Built and verified on magolor platform to confirm FSP solution works"
Cq-Depend: chrome-internal:4662167
Change-Id: I50d65e0caaf8f3f074322cff5bbdc68bdb1bbf78
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add support for the chausie EC. Use EC to configure default board GPIO
settings.
Change-Id: I3e59e17644cddf1a508614f90c20561bde2691fb
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Chausie uses the spi1 pads for eSPI
Change-Id: Iee9b92dd9b4e84764568ec3cc8d1fce731e0d1a7
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63866
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The lowest bound for L2 cache size on Socket P is 512 KiB.
This allows the use of cbfs mcache on all platforms.
This fixes building when some debug options are enabled.
Change-Id: I0d6f7f9151ecd4c9fbbba4ed033dfda8724b6772
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Commit 28e61f1634 "device: Use __pci_0_00_0_config in config_of_soc()"
significantly reduced the size of the bootblock. This makes the space
saving options, required to make to bootblock fit in the 32K SOC
limit, unnecessary.
TESTED: with configs/config.google_octopus_spi_flash_console the .text
size is 0x29c8 bytes which is still well below the 0x8000 SOC limit.
Change-Id: I208211d30cc2805113a16a02cdab957b8c584c92
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This area is used for storing AP RO verification data.
BUG=b:229670703
TEST=emerge-corsola coreboot
TEST=cbfstool /build/corsola/firmware/kingler/coreboot.rom layout
BRANCH=none
Change-Id: Id0a3304920c80987319d8072b8e443c41c1f1c47
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Add the configuration in device tree:
1. Add speaker codec and speaker amp settings
2. Add Elan touchscreen settings
3. Add WFC and usb settings
4 Add Elan Touchpad settings
5. Add WiFi configuration
6. Add LTE settings
BUG=b:229938024
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Iabf7f864082714ef1fecdee984fbebf1f3f0a672
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Fill GPIO table for Craask.
BUG=b:229938024
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I3b85b4b7a68211013f5862d71c8e31ecec41c7b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Add supported memory parts in mem_parts_used.txt, and generate SPD id
for this part.
MT62F1G32D4DR-031 WT:B
MT62F512M32D2DR-031 WT:B
BUG=b:229938024
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I183b74e66786c378cc227ee1e53ea422986b672a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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The unit of dram speed is MT/s so append it on variable name.
BUG=b:229549930
BRANCH=none
TEST=build coreboot without error
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I83c780440613050c0202f95d5f64991b61d9c280
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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- enable CPU PCIe VGPIO for PEG60
- enable GPP_C3/ GPP_C4 native function
- set unused GPIO to NC
BUG=b:229584785
BRANCH=none
TEST=build and boot into kernel v5.10
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I5d4ef92623ce6b0a36e6df23b232b35b498ce964
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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- Fix eMMC reset/ enable GPIO pins.
- Fix clk_req and clk_src
BUG=b:229437061
BRANCH=none
TEST=build and boot without error
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: Id16e292ec7557d1780516a267bd752014d98e463
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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When using LPDDR5 on a Type-C PCB, the Intel ADL-P PDG (Rev. 2.0.1)
page 121 recommends a maximum DRAM speed of 4800 MT/s.
BUG=b:229549930
BRANCH=none
TEST=build and pass memory training
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I38f0006d478702afb382d30338f20b46641964ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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BUG=b:229547171
BRANCH=none
TEST=pass memory training with error
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: If6acf8cb9474f816374743fd1e800da46958993d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Camera LED flicker 3 times or so as sensor is being probed
during kernel boot.
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips
initial probe during kernel boot preventing camera LED flicker.
Corrects that by explicitly sequencing the reset GPIO and power GPIO
BUG=b:219644184
TEST=Build and boot on vell, observe whether camera LED flickers
Change-Id: I846ec4cb5c4527f5664699b31d0d561d390d938c
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63441
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set native function (SD_AUX_RESET_L), and drive it high.
BUG=b:229181624
TEST=Build and boot to OS in Skyrim. Ensure that the SD Controller
and SD Card are enumerated fine.
02:00.0 SD Host controller: Genesys Logic, Inc GL9750 (rev 01)
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I03d88d90acc03cdebcb1e83ed2e799dda8b5b735
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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We need to include the SMM handler to enable SCI events when ACPI is
enabled.
With this enabled we now see we have EC timeout problems while in SMI:
[SPEW ] SMI# #1
[WARN ] SMIx88 => 0x800
[DEBUG] Chrome EC: Set SMI mask to 0x0000000000000000
[DEBUG] Chrome EC: UHEPI supported
[ERROR] Timeout waiting for EC QUERY_EVENT!
[DEBUG] Clearing pending EC events. Error code EC_RES_UNAVAILABLE(9) is expected.
[ERROR] EC returned error result code 1
[DEBUG] Chrome EC: Set SCI mask to 0x00000000186601fb
We still need to debug that. I suspect we have problems reading from
the ACPI IO decodes 0x62 or 0x66.
BUG=none
TEST=Verify SMI handler runs
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ida0fcd634e620274e124a8669836f3974e0a2bf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
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* Use GPE 24 since it doesn't conflict with any existing GEVENTS.
* Remove IRQ 12 mapping since it's not used.
* Unmask IRQ1 in PM registers.
* Use the new SMITYPE_ESPI_SCI_B SCI.
BUG=b:227282870
TEST=Build and boot to OS in Skyrim.
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7e9816d67500365ed1d2ee39ef184a1f60321ca1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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CONFIG_ONBOARD_SAMSUNG_MEM is not used anymore.
Remove CONFIG_ONBOARD_SAMSUNG_MEM.
This patch was intended to be part of CB:59754, but was not included in
the latest patchset.
BUG = N/A
TEST = Boot Facebook FBG1701 Rev 1.0 - 1.4
Change-Id: Id351bcafe005cc1b3319d7186ece2b5b9a7f49ac
Signed-off-by: Frans Hendriks <fhendriks.eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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There is a firewire chip TSB43AB22A mounted on the PCI bridge.
Add its definition to the device tree and mention it in the comment.
Change-Id: Iaa702b1efc15818ade2b1cd15aa6d415c3850e4b
Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Some devices/settings doesn't have helpful description in comments.
Update comments to describe the physical device on the board.
Change-Id: I479f41d71342104e74f862cf37b967963bc54877
Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The current configuration is masking off IRQ 1 and IRQ 12 to the PIC.
This for some reason causes problems when using level triggered
interrupts. This change updates the PIRQ_MISC0 value to match what
skyrim is doing. This will enable level interrupts to work correctly.
BUG=b:218874489, b:160595155
TEST=Boot zork and verify keyboard still works. Boot with patch train
and verify keyboard works as expected.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I46b1fd68915c6f7aa4c34cdba57d24425752bc38
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Add various verstage init functions to prepare for enable PSP verstage.
BUG=None
TEST=Build Skyrim BIOS image with PSP verstage enabled.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I0d0dba05d4d083e2c6860078676e59cf8f487c87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Change-Id: I088e514271b785e59907b0271eb89727ae1e7c05
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
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