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authorCasper Chang <casper_chang@wistron.corp-partner.google.com>2022-05-04 10:43:48 +0800
committerTim Wawrzynczak <twawrzynczak@chromium.org>2022-05-11 14:34:25 +0000
commit8f6fd3264823cbf4b5e9093c4b847d9b72d00eb4 (patch)
tree7e1ef1f2bce63274521052eb06295c71f3643f4a /src/mainboard
parent4beeb90813e24dc81a93872b7b86ffa5797539c0 (diff)
mb/google/brask/variants/moli: correct tcss_usb3 port
Correct tcss_usb3_port to meet Moli's schematic design. BUG=b:220814038 TEST=emerge-brask coreboot Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: Ib8faa4a353d8d617fce7aa70922bf027e6e11b38 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/brya/variants/moli/overridetree.cb4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/brya/variants/moli/overridetree.cb b/src/mainboard/google/brya/variants/moli/overridetree.cb
index e23107936e..24169c4d6e 100644
--- a/src/mainboard/google/brya/variants/moli/overridetree.cb
+++ b/src/mainboard/google/brya/variants/moli/overridetree.cb
@@ -144,7 +144,7 @@ chip soc/intel/alderlake
end
chip drivers/intel/pmc_mux/conn
use usb2_port3 as usb2_port
- use tcss_usb3_port2 as usb3_port
+ use tcss_usb3_port3 as usb3_port
device generic 1 alias conn1 on end
end
end
@@ -163,7 +163,7 @@ chip soc/intel/alderlake
register "desc" = ""USB3 Type-C Port C2 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, RIGHT, ACPI_PLD_GROUP(2, 1))"
- device ref tcss_usb3_port2 on end
+ device ref tcss_usb3_port3 on end
end
end
end