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Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I714867d455c4e0d01d6cb1cb9dc64669fb41100c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add variant specific cmos files, which avoid options like "FastCharge"
existing in platforms that don't support such options.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I04264cf72d47ef719acfd144d8bf9acb0ceccc11
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add variant specific cmos files, which avoid options like "Thunderbolt"
existing in platforms that don't support such options.
This change also removes entries that were never used, including:
* smi_handler
* usb_always_on
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I359e5c5bbf29eb474f2d3bc42a8e80afc0a5d38a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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To support an RPL SKU on brya0, brya0 must use the FSP for RPL.
Select SOC_INTEL_RAPTORLAKE for brya0 so that it will use the RPL
FSP headers for brya0.
BUG=b:248126749
BRANCH=firmware-brya-14505.B
TEST=cherry-pick Cq-Depends, then "emerge-brya intel-rplfsp
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage",
flash and boot brya0 to kernel.
Cq-Depend: chromium:3893035, chrome-internal:4983198
Change-Id: I2dd84757532d734ad97b74ba960537d937fb313e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
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Add a new THERMAL FW_CONFIG bitfield for describing power consumption
category of SoC.
BUG=b:250089101
TEST="emerge-brya coreboot chromeos-bootimage", flash and boot brya0
and skolas to kernel.
Change-Id: Iba3bd87abd4c112ceff4bbe51a7cf9eae3a694f2
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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1) Make the skolas FW_CONFIG field defintions compatible with the
brya0 FW_CONFIG field definitions to support skolas being a SKU of
brya0, and in sync with the config.star definitions for the FW_CONFIG
field for brya0 and skolas.
- brya0 specific changes:
1) remove WFC_MIPI_OVTI5675 definition (was 1)
2) redefine WFC_MIPI_OVTI8856 from 2 to 1
3) define new WFC_MIPI_KBAE350 camera type as 2
- skolas specific changes:
1) remove WFC_MIPI_OVTI5675 definition (was 1)
2) redefine WFC_MIPI_OVTI8856 from 2 to 1
3) define new WFC_MIPI_KBAE350 camera type as 2
2) Add support back in for UFC_MIPI_OVTI5675 in brya0 now that FW_CONFIG
defines are fixed.
BUG=b:248126749
TEST="emerge-brya coreboot chromeos-bootimage", flash brya0 and
verify it boots successfully to kernel and that WFC, UFC, and audio
works on skolas and brya0.
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Change-Id: I3be26e0a05f4dc08e5dc3f6ef7b71bdd8fd4f859
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
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Add the RPL CPU power limits to brya0's power limit table to support
both the brya0 ADL sku and the new RPL sku.
BUG=b:248126749
TEST="emerge-brya coreboot chromeos-bootimage", flash skolas with
image-brya0.serial.bin and verify skolas boots successfully to kernel.
Change-Id: I2ac067f98f1ff8f86cff0ed0e15010f454d9c91c
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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The delayed return of certain fetch instruction from memory to
the UFS causes the OCP fabric to timeout on the transaction
and become non-responsive.
As recommended by the SoC and IP teams,program the
OCP fabric register to avoid the timeout in the OCP fabric.
This patch adds the following changes
1. Program the OCP fabric registers in the PS0 routine.
2. Move the ssdt contents of UFS to dsdt asl code to avoid
duplication of UFS device creation
BUG=b:240222922
TEST=Build and boot Nirwen UFS board, observe no system hang
during Chrome PLT test.
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I949a4538ea5c5c378a4e8ff7bb88546db1412df2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Select the config to separate the AMDFW binary from the verified boot
section.
BUG=b:203597980
TEST=Build Skyrim BIOS image and boot to OS with PSP verstage passing
the hash table and PSP verifying the binaries against the hash table.
Observe boot time improvement of ~120 ms while operating SPI bus at 66
MHz with PSP verstage enabled.
Before this patch series:
508:finished loading body 1,978,053,432 (201,518)
After this patch series:
508:finished loading body 7,948,797,849 (83,460)
Change-Id: I78ec6d28b4c5fc40bdade47489d58180a54dee4d
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
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ChromeOS requires a custom SPL table. Update Kconfig to point to the
ChromeOS version of the SPL resident in the blobs directory.
Bug=b:245727030
Test=Boots
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I70dcb19983c970283ee887b78a18c0668e83d4b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67928
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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MSI PRO Z690-A WIFI DDR4 and MSI PRO Z690-A DDR4 are basically the
same boards, except the latter has no WiFi populated. Check the CNVi
WiFi presence and return correct SMBIOS product name string.
TEST=Check SMBIOS product name on both WiFi and non-WiFi variants in
Linux.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I5fedbce413dfb6a589a406d1e34e3e114ca6a40f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68078
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adjust the Makefile to look for SPD source Makefile. The current
SPD guard isn't set up correctly and is attempting to build the
APCB with SPD when SPD isn't present.
BUG=b:249988439
TEST=util/abuild/abuild -x -t GOOGLE_MORTHAL --verbose
util/abuild/abuild -x -t GOOGLE_SKYRIM --verbose
util/abuild/abuild -x -t GOOGLE_WINTERHOLD --verbose
Change-Id: I9cf13acb1188309ea6a1e6bdacc37d80b01f70a8
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68018
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This pin was originally set as output in error. This should be
a input to behave like GPP_E16 on the older variants.
BUG=b:239721380
TEST=build
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: Ic0f793ff52adb425ae5378b88d2837bb9e58edd2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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The DPTF parameters were verified by the thermal team.
BUG=b:249446156
TEST=emerge-nissa coreboot chromeos-bootimage
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: Ic7e0c73815dd02b97d89f94fab09a241b6279830
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Create the lisbon variant of the brask reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:246657849
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_LISBON
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: Ia31752765657054b28ea16b046b63c38a72f95bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
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De-duplicate common initialization code (self-test and device
identification) and put it in a new ipmi_if.c unit, which is
supposed to work with any underlying IPMI interface.
Change-Id: Ia99da6fb63adb7bf556d3d6f7964b34831be8a2f
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
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Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I4721d24aecd53c51c66c7d448b7c331d50a09712
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ibc257c2306351614669bd25ac83c24475f80fc6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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This is a vboot feature, not a ChromeOS one, and unless selected by
vboot, compilation will fail in the non-ChromeOS + vboot build case.
TEST=build/boot skyrim w/vboot, w/o ChromeOS
Change-Id: If9a5343907457bf3319f045262fdddf7eae2f1cb
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67995
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is a vboot feature, not a ChromeOS one, and unless selected by
vboot, compilation will fail in the non-ChromeOS + vboot build case.
TEST=build/boot guybrush w/vboot, w/o ChromeOS
Change-Id: I3108bcc8dfeacd99c9f5d36bd915d590292fef00
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67994
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This area relates to storing of AP RO verification information.
CONFIG_VBOOT_GSCVD is enabled by default for TPM_GOOGLE_TI50 and
guybrush is using TPM_GOOGLE_CR50.
Signed PSP verstage has the FMAP embedded. Since CB:67376 shifted the
RO section up by 8K, they were misaligned. Hence marking this area as
unused instead of removing the same to work around ChromeOS
infrastructure shortcoming.
Signed-off-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
Change-Id: Id852e5b5c1f777992a96a75143757f4df8d975b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67901
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It turns out that one can use Kconfig options to specify values for
devicetree options, as long as the resulting expression is a compile
time constant. Use this to configure SaGv for Atlas: enable it by
default, but allow SaGv to be disabled manually for convenience when
testing. Enabling SaGv makes MRC train the RAM multiple times, which
takes a significant amount of time.
For further info on SAGV on ADL, please refer to Intel Doc 655258
(Alder Lake Datasheet) section 5.1.3.2.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Change-Id: I3c6ac25d414122c408f2348d12dba8dce909e567
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable DPTC and No Battery Mode for Skyrim. This allows Skyrim to boot
without a battery or with a critically low battery.
DPTC remains disabled for the Winterhold and Morthal variants until it
can be tested on those boards.
BRANCH=none
BUG=b:217911928
TEST=Boot skyrim with low & no battery
Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: Icc4084476916cc8e142908d8e58baf7124568b8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67211
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change the TPM I2C freqeuncy to 1 MHz for nivviks and nereid, and in
the baseboard. Other nissa devices will be changed after verification.
This saves 11 ms of boot time on nivviks and nereid.
400 kHz:
504:finished TPM initialization 272,304 (35,730)
...
512:finished TPM PCR extend 526,250 (23,729)
513:starting locking TPM 526,250 (0)
514:finished locking TPM 535,106 (8,855)
6:end of verified boot 543,927 (8,821)
1 MHz:
504:finished TPM initialization 266,293 (30,747)
...
512:finished TPM PCR extend 513,711 (20,108)
513:starting locking TPM 513,711 (0)
514:finished locking TPM 521,311 (7,599)
6:end of verified boot 528,893 (7,581)
BUG=b:249201598
TEST=On nivviks and nereid, all timing requirements in the spec are met.
Frequencies:
nivviks - 972.01 kHz
nereid - 968.99 kHz
Change-Id: I9dd783527d4215ed7d79d69853a1f321ea2d8a28
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Disable the external 1.05v VR in S0 as a fix for the
display flicker issue in ADL-N.
Please refer the Doc with ID 742988 for more details.
BUG=b:248249033, b:245970842
TEST=Verified that the display flicker issue is fixed.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: If9f40e6c37e80caceb726a8e5f4d4b14dc479858
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67654
Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Disable the external 1.05v VR in S0 as a fix for the
Display flicker issue in ADL-N.
Please refer the Doc with ID 742988 for more details.
BUG=b:248249033, b:245970842
TEST=Verified that the display flicker issue is fixed.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Iaa53bfd99a550b2cffcdaee640ee3a429e93aef7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Commit c7204b5a4 [mb/google/guybrush: Enable backlight in the OS]
disabled the GPIO for the display backlight in favor of using ACPI
to enable it, but this breaks display output for payloads which do
not/can not enable the backlight GPIO themselves (edk2, grub, SeaBIOS).
Re-enable the GPIO for display backlight so that payloads other than
depthcharge work properly.
TEST=build/boot google/dewatt with Tianocore payload, verify payload
display visible.
Change-Id: I2519d779954ed89486045aa7de0b18f1c31a4374
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ie564d080955097b416943e772de6c62708ce5764
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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use is_enabled_cpu() on cycles over device list to check
whether the current device is enabled cpu.
TEST: compile test and qemu run successfully with coreinfo
payload
Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com>
Change-Id: If64bd18f006b6f5fecef4f606c1df7d3a4d42883
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67797
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This patch de-selects EC software sync config and enable early
EC Software Sync.
BUG=b:248775521
TEST=Able to perform EC sync on Google/Rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6bf8018e8a3fd06bb98c82a27d12883fc8d3a5db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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Rename so table more indicative of when GPIOs are set, and so it can
be used for more than just setting PCIe GPIOs.
Rename the getter function to match.
Change-Id: I285602209072247895c2cb0830f3faf675328757
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Rename variant_base_gpio_table() to baseboard_gpio_table(), since the
GPIO table comes from the baseboard, and is overridden by a separate
table from the variant.
Drop the __weak qualifier as this function is not overridden.
Change-Id: Icebf7e11736929389227063039575a4c5ecf3840
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This patch adds ACPI configurations of 8MP YHUX and 2MP CJFKF28-1
as world- and user-facing cameras of Rex.
BUG=b:246413264
TEST=Verified world- and user-facing cameras using Chrome Camera App on
Google/rex device.
Signed-off-by: Daniel Kang <daniel.h.kang@intel.com>
Change-Id: Iaaa16e491a66500606b3a9eb1d87f396641778e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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According intel Doc#634254 and Doc#608715
PS2/PS1 cross point = 5
PS1/PS0 cross point = 10
PS2 cutoff = 1.4*(PS2/PS1 cross point) = 7
1.3 is better magnification, it obtain by test
PS1 cutoff = 1.3*(PS1/PS0 cross point) = 13
BUG=b:241850120
BRANCH=brya
TEST='FW_NAME=vell emerge-brya coreboot'
Change-Id: I83e9682004e2c3644ad4a5565e6ab85be48ba22f
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Xivu uses PCIE WLAN, so disable the CNVi WLAN/BT.
BUG=b:247120749
TEST=Boot to OS on xivu and check that WLAN/BT still works.
Change-Id: I968d383278bd50268d899cff82067ceb7c3ba5ed
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Ben Kao <ben.kao@intel.com>
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Rename variant_base_gpio_table() to baseboard_gpio_table(), since the
GPIO table comes from the baseboard, and is overridden by a separate
table from the variant.
Drop the __weak qualifier as this function is not overridden.
Change-Id: I17db734784ce96cdf5e0486dc2ad057d73bfb15f
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Rather than duplicating the entire set of GPIOs from the baseboard, use
the variant_override_gpio_table() method like all other octopus
variants do.
TEST=build/boot ampton, dump GPIOs and verify unchanged.
Change-Id: I36aa25bbee7c21a51d9fdd40405f492082455d9c
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67803
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add support for the following two new memory parts to support a new
SKU that has two memory options that brya0 does not have:
MT53E2G32D4NQ-046 WT:C
MT53E512M32D1NP-046 WT:B
BUG=b:248126749
TEST="emerge-brya coreboot chromeos-bootimage", flash a skolas with
an image-brya0.serial.bin and verify it boots successfully to kernel.
Change-Id: I28667918e5a183339febdc054465effeac8bddbe
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67879
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Rename variant_base_gpio_table() to baseboard_gpio_table(), since the
GPIO table comes from the baseboard, and is overridden by a separate
table from the variant.
Drop the __weak qualifier as this function is not overridden.
Change-Id: I11814016d654bc2c2e6d24b3d18fb30d5b843fe9
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Rename variant_base_gpio_table() to baseboard_gpio_table(), since the
GPIO table comes from the baseboard, and is overridden by a separate
table from the variant.
Drop the __weak qualifier as this function is not overridden.
Change-Id: Id1e1a67608454466dc65bf4c4985cf4eba84c97d
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Rename variant_base_gpio_table() to baseboard_gpio_table(), since the
GPIO table comes from the baseboard, and is overridden by a separate
table from the variant.
Drop the __weak qualifier as this function is not overridden.
Change-Id: Ib8439e664defeafd2d08cffb74c997ab69230231
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Rename variant_base_gpio_table() to baseboard_gpio_table(), since the
GPIO table comes from the baseboard, and is overridden by a separate
table from the variant.
Drop the __weak qualifier as this function is not overridden.
Change-Id: Iaa3c9404919fd6c43596d7b27cfab43a1a5b0b21
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This patch selects the SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES to allocate
TBT/USB4 root port resources for PCIe tunneling.
BUG=b:248328015
TEST=Built image and verified TBT/USB4 tunneling functions on Rex.
Change-Id: I69f4d26bb7b3d74dbda068add284a69f1bbeff40
Signed-off-by: zhaojohn <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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In order that GPP_H13 not use the GPIO override programming from its
baseboard (brya), explicitly program GPP_H13 to a output HIGH instead
of relying on the 20K pullup from the baseboard.
BUG=b:240617195
TEST=SSD still functional
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iddedebe2d5cfc0123932b14980d1268bcb147703
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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The next rev of this board will move the dGPU PEXVDD enable pin from
GPP_E10 to GPP_F12. This patch handles both the old and newer revisions
by using an ACPI Name to hold the GPIO # for PEXVDD enable. It also
cleans up the GPIO handling a little bit between board revs.
BUG=b:242752623
TEST=dGPU is functional and power sequencing tests still pass on board
rev 2
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Icc7968777f86ab07561b0a861b7d22ec714d1c34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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On Banshee, when the privacy switch is toggled the camera is
disconnected. Which means that we will never be able to tell the user
that the privacy switch is enabled when the camera is on, making the
virtual control unusable.
Remove the description.
BUG=b:248219472
BRANCH=firmware-brya-14505.B
TEST=none
Change-Id: I1a241bd889c0c1aae039510a0620748b2f7a6806
Signed-off-by: Ricardo Ribalda <ribalda@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Modify GXTP7863 generic.irq to generic.irq_gpio.
BUG=b:245082617
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: Iaf6cc6010132d5b33b06909ceb1069115a911b48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This reverts commit 1a8eb6c02103727431ac1ea23f4f507e49f3cde7.
Reason for revert: migrating to the 32MB AP Firmware hence, need to
revert this CL.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibea1ad0cff008f9391cbda9e51899557b1e9c979
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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'Mendocino' was an embargoed name and could previously not be used.
Update references for consistency with the correct naming convention.
BUG=b:245727030
TEST=builds and boots to kernel
Cq-Depend: chrome-internal:4878294
Cq-Depend: chromium:3763392
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ic0248a872dfc92486658aa9bd92bed755dbf59d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67750
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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BIOS_ERR is inappropriate since the init message is informational.
Use BIOS_INFO instead.
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I6fc15291a6d177a1b9e258d08e165224e5e10b32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67733
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
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EN_PP3300_EMMC has be changed to GPP_A21 for DP++ and it based on Moli GPIO Table_20220803.xlsx, so update enable_gpio for emmc_rtd3 by board_ver.
BUG=b:241370405
TEST=emerge-brask coreboot
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I129706861fd1fcf061371ce94352331ef44359d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Add the gma-mainboard.ads for display output definition and enable the
libgfxinit usage in mainboard Kconfig.
Change-Id: I7e7a44736a8136b5320821e744134c7d64c7f1b4
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67683
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently the `pch_pirq_init()` function in lpc_lib.c will program
PIRQ IRQs for all PCI devices discovered during enumeration. This
may not be correct for all devices, and causes strange behavior
with the Nvidia dGPU; it will start out with IRQ 11 and then after
a suspend/resume cycle, it will get programmed back to 16, so the
Linux kernel must be doing some IRQ sanitization at some point.
To fix this anomaly, explicitly program the IRQ to 16 (which we
know is what IRQ it will eventually take).
BUG=b:243972575
TEST=`lspci -vvv -s1:00.0|grep IRQ` shows IRQ 16 is programmed
at boot and stays consistent after suspend/resume.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I66ca3701c4c2fe5359621023b1fd45f8afd3b745
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67746
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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According to Nvidia, the GC6 flag (DFEN) should not get cleared after
a successful GC6 entry; the kernel driver will not re-inform ACPI
that the exit should be GC6 exit as well.
BUG=b:243888246
BRANCH=brya
TEST=tested by Nvidia
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I220795928d03f269de48278ea0ab57de7253fad5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67745
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The hatch and puff baseboards have diverged enough to where it makes
more sense to split them into separate boards. Copy the mb/google/hatch
directory into a new dir 'puff' and strip out all boards and items
related to the hatch baseboard. Remove all puff-related items from the
original hatch directory. Clean up and alphabetize Kconfig selections.
Test: build and boot akemi hatch variant and wyvern puff variant.
Change-Id: I8c7350f3afcff3ddefc6fa14054a3f9257568cd3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62970
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable early initialization of the PTN3460 DP-to-LVDS bridge on this
board in order to allow showing the bootsplash screen at coreboot
runtime.
Change-Id: Ib1b727cef5fb8bea2d6d6c9896ad0107caeea51a
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67682
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All cherry boards (tomato, dojo) share the same SKU ID encoding, in the
sense that a device has NVMe storage if and only if the BIT(1) of SKU ID
is set (otherwise eMMC). Therefore, instead of hard coding the list of
NVMe (PCIe) SKU IDs, we check the BIT(1) to decide whether to initialize
PCIe.
In addition, in preparation for UFS devices coming in the future,
reserve BIT(3) (which is unset for all of current SKUs) for them.
BUG=b:237953117, b:233327674
TEST=emerge-cherry coreboot
BRANCH=cherry
Change-Id: I9b30338645a87f29f96a249808b90f1ec16f82df
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Set tcc_offset value to 1℃ in devicetree for Thermal Control Circuit
(TCC) activation feature. This value is suggested by Thermal team.
BUG=b:246913963
TEST=USE="project_crota project_brya" emerge-brya coreboot
Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: Ie2f60bed34fbd6fa3624be60138511a22b199a8d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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This reverts commit d6695626631a86d9613ea7c34ff0e898fbfa443c.
Reason for revert: Was submitted out-of-order and with an unresolved
TODO in the commit message.
Change-Id: Id5a8770226afbfcdf63d451157e4586b6cdd5189
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67284
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Previously, the Bluetooth interface worked when port 9 was enabled.
Now, it works with port 5 enabled, which matches the schematic.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If783e60c8120adcd6522676cb3343ed46bf39d78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
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This patch makes dedede EC wake up AP from s0ix when the state of
charge drops to low_battery_shutdown_percent.
Demonstrated as follows:
1. Boot OS.
2. Run powerd_dbus_suspend.
3. On EC, run battfake 4.
4. System resumes.
BUG=b:244253629
TEST=Verified on dedede
Change-Id: I39234d2b9e739383b5f96be49077f8c9831fa0fa
Signed-off-by: Ivan Chen <yulunchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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On ADLRVP with LP5 memory, MRC team recommends enabling ECT(Early
Command Training) to avoid hang during boot process.
BRANCH=firmware-brya-14505.B
TEST=Booted to OS on ADLRVP with LP5 memory.
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Change-Id: I2472707825bbbdd8e5c12a714e0d40ea0b458838
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
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Skolas board is based on Raptor Lake SoC, not Alder Lake. The code
change sets CPU power limit values as performance configuration based
on various Raptor Lake SoC SKUs as per the document #686872.
BUG=b:242869605
BRANCH=None
TEST=Built and tested on skolas board
Change-Id: Ieb3ca4ff77039412ef56da49e1b438f5e0b9db02
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
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Enable ddc on DDI_PORT_2 for support DP++.
BUG=b:240382609
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I475e3c0278cfa92ab40ad84f6da580b4cded9933
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add a variant specific S0ix hook to fill the SSDT table to disable and
enable camera during suspend and resume respectively.
BUG=b:206911455
TEST=Build Boten BIOS image. Ensure that camera is disabled during
suspend and enabled during resume.
Change-Id: I3229b22b8d8651bf2d9df25b10ce6749efde7cf6
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
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Add FM350GL 5G WWAN support using drivers/wwan/fm and additional PM
features from RTD3.
BUG=b:244077118
TEST=check cbmem -c
\_SB.PCI0.RP06: Enable RTD3 for PCI: 00:1c.5 (Intel PCIe Runtime D3)
\_SB.PCI0.RP06: Enable WWAN for PCI: 00:1c.5 (Fibocom FM-350-GL)
check PXSX Device is generated in ssdt.
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Change-Id: I6114c589769d2eca882cf1a5255cf4c5937121a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add new ram_id:3 (0011) for memory part K3LKCKC0BM-MGCP.
DRAM Part Name ID to assign
K3LKCKC0BM-MGCP 3 (0011)
BUG=b:247039096
TEST=Use part_id_gen to generate related settings and
emerge-nissa coreboot
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I78d2e501b9d8d801a3d149002f638125bf4275f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Builds are failing on upstream master branch because there is no
board_info.txt for the Intel Meteor Lake RVP mainboard; this patch
adds a basic one so the tree will build.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I3356ad65132dc4aaebd5e7d959a2bdb9ab1316b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67711
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
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Modify config settings based on new module KBAE350 spec
BUG=b:245640845
BRANCH=None
TEST=Build and boot on skolas
Signed-off-by: AlanKY Lee <alanky_lee@compal.corp-partner.google.com>
Change-Id: I8a9bee9bb79bda4e3f1d259716844b42a7fce397
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jimmy Su <jimmy.su@intel.corp-partner.google.com>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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This adds 32MB flashmap descriptor as below:
Descriptor Region: 0x0 - 0x3fff (~16KB)
Intel EC Region: 0x4000 - 0x83fff (~512KB)
ME Region: 0x84000 - 0x8fffff (~8.5MB)
BIOS Region: 0x900000 - 0x01ffffff (~23MB)
BUG=b:224325352
TEST=util/abuild/abuild -p none -t intel/mtlrvp -a -c max
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: Ifb572efe56eb7400b8328ba797892738f5927158
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66098
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adjust the EEPROM layout to account for two new fields: board part
number and product part number. In addition, put them in a Type 11
SMBIOS table (OEM Strings).
TODO: This currently stores the "raw" part numbers, should we add a
prefix to the SMBIOS strings?
Change-Id: I85fb9dc75f231004ccce2a55ebd9d7a4867fcb93
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67276
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the Low/No Battery Mode DPTC values for Skyrim.
These values were generated by AMD.
BRANCH=none
BUG=b:217911928
TEST=Build skyrim
Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: I5f277761cb7379b4344492f95010d8d5ddd689fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67693
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the Normal Mode DPTC values for Skyrim.
These values were generated by AMD.
BRANCH=none
BUG=b:217911928
TEST=Build skyrim
Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: I1e1f55b941f3e70aad33d55a90fb012eac3ba12d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67690
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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ELAN6918 Power Sequencing seems not perfectly matching
with the previous platforms and setting GPP_C06 to high prior
to the power sequencing is actually makes it work.
Ideally Power Sequencing should be as below for ELAN6918 (in ACPI)
`POWER enabled -> RESET deasserted -> Report EN enabled`
But below sequence is only working currently:
`Report EN enabled (ramstage) -> POWER enabled (ACPI) -> RESET
deasserted (ACPI)`
BUG=b:247029304
TEST=Verified ELAN touch panel is working as expected after booting
Google/rex device to ChromeOS.
Change-Id: Ideaeb0faa882b8e603534bbface51ea76923d436
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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The brya4es variant is no longer needed, removing code for brya4es.
BUG=b:246611270
TEST=None
Change-Id: I9b222f89fe766c63158518713be19d7959451721
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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Since there are no legacy devices on the variant mc_apl7 do not wait
for them on mc_apl7.
Change-Id: Ia4e6c0fb495a347be51bd6604a1d9b73098fb7b6
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67684
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable nau8825 ADCOUT to make I2S signal meet spec.
BUG=b:234789689
TEST=I2S waveform can meet spec timing.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I7ea472ac4e4add4e790b9b3fbb6becd40665eb1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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TEST=Able to build and boot the Google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iae5317b24856ef2cbd2f36cc28f645826536c21a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
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Moving the config value SOC_AMD_COMMON_BLOCK_ACPI_DPTC to
soc/amd/picasso/Kconfig and conditionally enabling it for only Morphius
boards makes the value dptc_tablet_mode_enable redundant.
This CL removes dptc_tablet_mode_enable so DPTC is controlled entirely
with the Kconfig value SOC_AMD_COMMON_BLOCK_ACPI_DPTC. This means DPTC
is only included for boards that actually enable it.
BRANCH=none
BUG=b:217911928
TEST=Build zork
Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: Ic54a9bb491234088be8184bec8b09e2e31ffa298
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ie5fc0a8230cdcc24ad1d2d94cc6d019ff10aac48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
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BIOS_ERR is inappropriate since the message is informational.
Use BIOS_INFO instead.
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I91be3f47ae93c8262e430a06cacec3d2c29ebd58
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Move enabling SOC_AMD_COMMON_BLOCK_ACPI_DPTC from
soc/amd/picasso/Kconfig to mainboard/google/zork/Kconfig and
conditionally enable it only for Morphius boards.
This reduces which boards/variants have DPTC enabled to only those that
actually use it.
BRANCH=none
BUG=b:217911928
TEST=Build zork
Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: Iddebcf5dbadae135c8110e2afd9ad76ef7dcc09d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67637
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This file isn't correct, since the Stoneyridge SoC doesn't have a legacy
PCI bridge on bus 0 bridge 0x14 function 4. Google/Kahlee doesn't select
HAVE_PIRQ_TABLE, so it's likely safe to also not select it for this
board.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibaf470b9ff7823019772d43af98ebc47af395728
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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This file is neither included in the build nor correct, since the
Stoneyridge SoC doesn't have a legacy PCI bridge on bus 0 bridge 0x14
function 4.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0daed891984faed9fbc36f0215edfc56e0ae14a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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As of commit 2cf52d80a6ec ("mb/*/{device,override}tree: Set touchpads to
use detect (vs probed) flag") all touchpads in the tree have been
switched from using the 'probed' flag to 'detect.' Winterhold was added
in between the time that patch was pushed and merged, so switch these
instances over too.
Change-Id: I34e1265ecd6409f720ae486926c5078f626fc693
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67487
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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That's 3 years of development, including adapting to new, shiny,
Cascade of Attention-Deficit Teenagers[0] induced incompatible
assembler syntaxes.
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
[0] https://web.archive.org/web/20220824045741/https://www.jwz.org/doc/cadt.html
Change-Id: I8606700149ca74e93b85d78546a29df2916d39b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Turn off the LAN power which is controlled by GPP_A10 in S0ix states.
For an USB device, the S0ix hook is needed for the on/off operationas
to take place.
BUG=b:245426120
BRANCH=firmware-dedede-13606.B
TEST=emerge-shotzo coreboot
check LAN LED off in S0ix states
check LAN function ok after suspending 500 loops
check SSDT table has MS0X entry
Scope (\_SB)
{
Method (MS0X, 1, Serialized)
{
If ((Arg0 == One))
{
\_SB.PCI0.CTXS (0x41)
}
Else
{
\_SB.PCI0.STXS (0x41)
}
}
}
Change-Id: I3fcab4a73239b4f006839c0c81e9b4cc74047b77
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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To improve boot time, raise little CPU from 500MHz to 2GHz at romstage
(before DRAM calibration).
FW logs:
Check CPU freq: 1999968 KHz, cci: 1600012 KHz
TEST=cpu freq and cci freq run correctly.
BUG=b:244251006
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Ic1bed53669baa15f797c9a952455376a39d29cf3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67544
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since mono_time is now 64-bit, the utility functions interfacing with
mono_time should also be 64-bit so precision isn't lost.
Fixed build errors related to printing the now int64_t result of
stopwatch_duration_[m|u]secs in various places.
BUG=b:237082996
BRANCH=All
TEST=Boot dewatt
Change-Id: I169588f5e14285557f2d03270f58f4c07c0154d5
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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BUG=b:232573696
TEST=Able to verify audio playback on Google/Rex with this change.
Change-Id: Ia8dfc79e7e4d27828726145156c870733d716899
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66919
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:245426120
BRANCH=firmware-dedede-13606.B
TEST=emerge-dedede coreboot
check SSDT table has MS0X entry
Scope (\_SB)
{
Method (MS0X, 1, Serialized)
{
If ((Arg0 == One)) {}
Else
{
}
}
}
Change-Id: Id01089531503e62231c5ab19e4cd8056198b9acb
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Add the 'detect' flag to the Elan touchpad, so coreboot can determine
which touchpad type is present at runtime and generate the correct
ACPI entry for it (the Synaptics touchpad already has the flag).
Test: build/boot google/nami, verify touchpad works under Linux/Windows
Change-Id: I437d1d470552d55496dfe611f441331127c64250
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Tidy up the layout to remove unnecessary sizes. This change also makes
the flash start at 0x0 and increases the size of the FMAP to 0x1000.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I46663003857eb50271c6ad1da6c4e56c8f4bb6c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
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Enable S3 support as Prodrive doesn't need s0ix for now.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I7625c8ac860e1afc60c94b3c51e996531a1f2b15
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67414
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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The current HWIDs for ADL RVP are reported as invalid by Chrome on
ChromeOS; fix it by generating new valid HWIDs with the following
commands:
```
./util/chromeos/gen_test_hwid.sh ADLRVPM
./util/chromeos/gen_test_hwid.sh ADLRVPN
./util/chromeos/gen_test_hwid.sh ADLRVPP
```
BUG=b:243899466
Change-Id: Iad6f47e67c2d35363b042aabec8b3317d5bfc111
Signed-off-by: Victor Ding <victording@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67532
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Problem: OTA is triggering warmboot, where DDR is
in self-refresh mode. Due to which DDR training
is not going well.
Change: Verify reboot type in case of OTA. If it is warmboot, will
force for cold boot inorder to trigger DDR training
BUG=b:236990316
TEST=Validated on qualcomm sc7180 development board.
Test observation: Cold boot is triggered forcefully,
if current reboot is warmboot in case of OTA
Signed-off-by: Venkat Thogaru <quic_thogaru@quicinc.com>
Change-Id: I908370662292d9f768d1ac89452775178e07fc78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67406
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable Kconfig options for ASPM.
TEST=Verify ASPM is enabled with `lspci -vvv`, `suspend_stress_test -c
10` passed all 10 times
BUG=b:243771794
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I54071d9c9607da4561d745d152924d56904c0fee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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Update ASPM configuration, disabling ASPM for the SSD due to s0i3
issues. Bug b:245550573 created to track the SSD issue.
TEST=Boot to OS and verify suspend via `suspend_stress_test -c 10`
BUG=b:243771794
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I45a290c8ceddd39f65c6fe1390e3a753cad99899
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
|
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Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: If6cdf02c56778da67b56afbb71f9f01107f23d2e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I4ccdd370d3e9aef938fae4c4690ec0bf4c53c500
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
