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authorKarthikeyan Ramasubramanian <kramasub@google.com>2022-08-25 17:05:23 -0600
committerKarthik Ramasubramanian <kramasub@google.com>2022-10-04 15:35:26 +0000
commitd49c3f278eb77faff098dceb5e7767b53950cd5d (patch)
tree6d1c6fab2731d79c1a3ec371c3a3db6c38162188 /src/mainboard
parent49332fe85696575c4f9b6ee52508e61f7159bb4c (diff)
mb/google/skyrim: Enable amdfw separation
Select the config to separate the AMDFW binary from the verified boot section. BUG=b:203597980 TEST=Build Skyrim BIOS image and boot to OS with PSP verstage passing the hash table and PSP verifying the binaries against the hash table. Observe boot time improvement of ~120 ms while operating SPI bus at 66 MHz with PSP verstage enabled. Before this patch series: 508:finished loading body 1,978,053,432 (201,518) After this patch series: 508:finished loading body 7,948,797,849 (83,460) Change-Id: I78ec6d28b4c5fc40bdade47489d58180a54dee4d Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Tim Van Patten <timvp@google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/skyrim/Kconfig1
-rw-r--r--src/mainboard/google/skyrim/chromeos.fmd2
2 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig
index 72079e86ed..87cf6e43a5 100644
--- a/src/mainboard/google/skyrim/Kconfig
+++ b/src/mainboard/google/skyrim/Kconfig
@@ -97,6 +97,7 @@ config VBOOT
config VBOOT_STARTS_BEFORE_BOOTBLOCK
bool "Enable PSP_verstage"
default y if VBOOT
+ select SEPARATE_SIGNED_PSPFW
config VBOOT_STARTS_IN_BOOTBLOCK
bool
diff --git a/src/mainboard/google/skyrim/chromeos.fmd b/src/mainboard/google/skyrim/chromeos.fmd
index 3be90a44fe..670ac16a73 100644
--- a/src/mainboard/google/skyrim/chromeos.fmd
+++ b/src/mainboard/google/skyrim/chromeos.fmd
@@ -4,11 +4,13 @@ FLASH@0xFF000000 16M {
RW_SECTION_A 3M {
VBLOCK_A 8K
FW_MAIN_A(CBFS)
+ SIGNED_AMDFW_A 1536K
RW_FWID_A 256
}
RW_SECTION_B 3M {
VBLOCK_B 8K
FW_MAIN_B(CBFS)
+ SIGNED_AMDFW_B 1536K
RW_FWID_B 256
}
RW_ELOG(PRESERVE) 4K