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2022-05-28mb/google/brya/var/mithrax: Update typeC EC mux portJohn Su
We need to put USB setting in mux order. BUG=b:234103724 TEST=Type C mux configuration is correct. Wrong: added type-c port0 info to cbmem: usb2:2 usb3:2 sbu:0 data:0 added type-c port1 info to cbmem: usb2:3 usb3:3 sbu:0 data:0 Correct: added type-c port0 info to cbmem: usb2:3 usb3:3 sbu:0 data:0 added type-c port1 info to cbmem: usb2:2 usb3:2 sbu:0 data:0 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I4f8dbee35159960d17107e23fcde825a38c7de4e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-28mb/starlabs/labtop: Add LabTop Mk IIISean Rhodes
Tested using MrChromeBox's `uefipayload_202107` branch: * Windows 10 * Ubuntu 20.04 * MX Linux 19.4 * Manjaro 21 No known issues. https://starlabs.systems/pages/labtop-mk-iii-specification Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ia52566e06f50c0abcfb657044538db8e92564c36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Ben McMillen <ben@starlabs.systems>
2022-05-28mb/google/brya/var/volmar: Correct _PLD valuesWon Chung
This patch is to denote the correct value of ACPI _PLD for USB ports. +----------------+ | | | Screen | | | +----------------+ C0 | | C1 | MLB DB | A0 | | +----------------+ BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Ibd36fb961de9e9af9da1fd885eeb958c833d38bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/64618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-28mb/google/brya/var/taniks: Correct _PLD valuesWon Chung
This patch is to denote the correct value of ACPI _PLD for USB ports. +----------------+ | | | Screen | | | +----------------+ C0 | | C1 A | MLB DB | A | | +----------------+ BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Ia66c6fafe08110b8d8f9a138a2516ae03f8e1809 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-28mb/google/brya/var/{taeko, taeko4es}: Correct _PLD valuesWon Chung
This patch is to denote the correct value of ACPI _PLD for USB ports. +----------------+ | | | Screen | | | +----------------+ C0 | | C1 A | MLB DB | A | | +----------------+ BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Icd56c650a03c5db6e1e68e4ca4c9f0c068a7a430 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-28mb/google/brya/var/{primus, primus4es}: Correct _PLD valuesWon Chung
This patch is to denote the correct value of ACPI _PLD for USB ports. +----------------+ | | | Screen | | | +----------------+ C2 | | A0 C0 | MLB DB | A | | +----------------+ BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Ia493fd28c362d2c0c343c2d121f6611cfd8f7f6c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-28mb/google/brya/var/kano: Correct _PLD valuesWon Chung
This patch is to denote the correct value of ACPI _PLD for USB ports. +----------------+ | | | Screen | | | +----------------+ C0 | | C1 | | A0 | | +----------------+ BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: I840b0f363a1ff304b310505efdaba2ac1cd10472 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-28mb/google/brya/var/felwinter: Correct _PLD valuesWon Chung
This patch is to denote the correct value of ACPI _PLD for USB ports. +----------------+ | | | Screen | | | +----------------+ C2 | | C1 | MLB DB | A0 | | +----------------+ BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Ie4f96e3636a8b519923fdba7f9bd07d7a3e1d7ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/64613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-28mb/google/brya/var/{anahera, anahera4es}: Correct _PLD valuesWon Chung
This patch is to denote the correct value of ACPI _PLD for USB ports. +----------------+ | | | Screen | | | +----------------+ A | | A C0 | MLB DB | C2 | | +----------------+ BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Ia1e95aba2f7d02131b0b0cdd6c7211a23e355084 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-28mb/google/brya/var/{brya0, brya4es}: Correct _PLD valuesWon Chung
This patch is to denote the correct value of ACPI _PLD for USB ports. +----------------+ | | | Screen | | | +----------------+ C2 | | A0 C0 | MLB DB | C1 | | +----------------+ BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: I68fb940825bfcf7c77ca3015372025e47e7fcc41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-28mb/google/brya/var/nissa: set tcc_offset value to 10Sumeet Pawnikar
Set tcc_offset value to 10 in devicetree for Thermal Control Circuit (TCC) activation feature as mentioned in doc #572349. BUG=b:229804441 BRANCH=None TEST=Build FW and test on Nivviks board Change-Id: Ie9533936eccbabcc9a873adcb622bb490928c9e3 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-28mb/google/skyrim: Update Kconfig to use Ti50Jon Murphy
Skyrim uses the Ti50 GSC and the config should be updated to reflect that. BUG=b:233750667 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I5d4af19ab2dda35ab687a0659898d79b08c4de97 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-28mb/starlabs/lite: Add Bluetooth USB interfaceSean Rhodes
Enable the USB port that is used by the Bluetooth interface on the CNVI. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I2a330618c5f1c5fd5e3147cb6307c157b28070ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/64545 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-28mb/starlabs/lite: Remove webcam USB port from devicetreeSean Rhodes
Remove the Webcam USB port form the devicetree and handle it solely in devtree, which will enable or disable it based on the CMOS option. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9c89c7103aca5c3d42215122e9d94c83947b6fee Reviewed-on: https://review.coreboot.org/c/coreboot/+/64544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-28mb/starlite/lite: Configure tcc_offset based on power_profile settingsSean Rhodes
Set tcc_offset value based on the power_profile value, ranging from 5 to 15 degrees. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Id30bec9c095517884a7361226aed703b370f2207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-05-28vendorcode/amd/agesa/fam16kb: Fix improper use of .dataArthur Heymans
AGESA has a lot of code in the .data section which is for initialized data, that in fact should be .rodata. This adds the 'CONST' keyword everywhere it is needed. TEST: See in the .elf file (e.g. using readelf) that there is nothing in .data section. Change-Id: Ie8817434ee0bc6c195eabe090f195512c0043ae5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2022-05-28vendorcode/amd/agesa/f15tn: Fix all improper use of .dataArthur Heymans
AGESA has a lot of code in the .data section which is for initialized data, that in fact should be .rodata. This adds the 'CONST' keyword everywhere it is needed. TEST: See in the .elf file (e.g. using readelf) that there is nothing in .data section. Change-Id: I9593c24f764319f66a64715d91175f64edf10608 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2022-05-28mb/google/brya/var/vell: Set empty on USB2_9/USB32_1Shon
The baseboard uses port USB2 #9, and USB3 #1, but vell does not, therefore set the port configuration to EMPTY. Change-Id: I0d03b967fd2a051205ad5807f0bd8916bad7c036 Signed-off-by: Shon <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-28mb/starlabs/lite/{glk/glkr}: Disable PMC PCI deviceSean Rhodes
The PMC is accessed via sideband registers, so the PCI device is not needed. Disabling it solves a bug where the laptop cannot be powered on without the charger connected. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I78f4aa4567dfc154ef5cb21f8746265259cd53e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64451 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-28mb/starlabs/lite/{glk/glkr}: Disable DPTF deviceSean Rhodes
DPTF is not used, so disable the corresponding PCI device. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9e4a3bada13dcabc1af3e1e5b3c215939f8239fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/64449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-05-28mb/starlabs/lite/{glk/glkr}: Remove subsystem device IDSean Rhodes
Remove the subsystem device ID for HDA devices, so that the correct Intel [8086:xxxx] is used. This was an old workaround for Windows that is no longer required with a new driver. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I63d6a4b0f19d400d683cab5dacca787d6c6a0fdc Reviewed-on: https://review.coreboot.org/c/coreboot/+/64448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-05-28mb/starlabs/lite/{glk/glkr}: Decrease S3 assertion time to 28 msSean Rhodes
Set S3 assertion time to 28000us as this is sufficient time for rails to discharge. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4a14e7b30bb1fc4c0c1d3ff2f75069863458487f Reviewed-on: https://review.coreboot.org/c/coreboot/+/64447 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-28mb/starlabs/lite/glkr: Correct OverCurrent PinSean Rhodes
The USB ports use both OC0 and OC1. Whilst they work perfectly with OC_SKIP, set them to the correct pins. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If173b443d9770083d76519b854b513d8e47b9e71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-28mb/starlabs/lite/glk: Correct OverCurrent PinSean Rhodes
The OC pin was set to 0, which isn't connected. All USB ports are connected to OC1. This solves a strange issue where the Lite can't be powered on without the charger connected. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I700ddde291f0e4be6e3787e2da13f6d3ece736b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-28mb/google/brask/variants/moli: correct empty tcss portRaihow Shi
Correct empty tcss port to meet Moli's schematic design. BUG=b:233834605 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Id16744655010e246c8ca8d1050f71a6c6c63d2a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-28mb/google/brya/var/banshee: Enable SaGvFrank Wu
Enable SaGv support for Banshee BUG=b:233930777, b:233703655 BRANCH=firmware-brya-14505.B TEST=FW_NAME=banshee emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I22810f422e3f1d6dd1f64d93e6d7aff5593ff739 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2022-05-26soc/intel/tigerlake: Hook up FSP hyper-threading setting to option APIFelix Singer
Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting from the FSP to the option API so that related mainboards don't have to do that. Unless otherwise configured (e.g. the CMOS setting or overriden by the mainboard code), the value from the Kconfig setting `FSP_HYPERTHREADING` is used. Also, remove related code from the mainboard starlabs/laptop/tgl, since it is obsolete now. Change-Id: I49bbd4a776b4e6c55cb373bbf88a3ca076342e3e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-05-26soc/intel/cannonlake: Hook up FSP hyper-threading setting to option APIFelix Singer
Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting from the FSP to the option API so that related mainboards don't have to do that. Unless otherwise configured (e.g. the CMOS setting or overriden by the mainboard code), the value from the Kconfig setting `FSP_HYPERTHREADING` is used. Also, remove related code from the following mainboards, since it is obsolete now. * siemens/chili * starlabs/laptop/cml Change-Id: I173b87da5ce76549672c50ba30204cd77be8b82f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-05-25mb/google/brask/variants/moli: enable USBA port 4Raihow Shi
Moli has USBA port4 but Brask didn't use the port4, so enable USBA port4 in moli. BUG=b:232656163 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I5308e3102ea9f0718802596a235c0a5cc42e30bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/64370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-05-25mb/google/brya/var/mithrax: Add WiFi SAR table for mithraxJohn Su
Add WiFi SAR table for mithrax. BUG=b:231491014 TEST=emerge-brya chromeos-config chromeos-config-bsp-private coreboot-private-files-baseboard-brya coreboot chromeos-bootimage and checked SAR table can load by WiFi driver. Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I847debd7c817225b5b1777c798a14ef10aee3471 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-05-25mb/google/guybrush: Remove unused GPIO tableJon Murphy
On Guybrush, the power and lid switches are managed by the EC and coreboot and the AP have no control over them within this context. Remove unused GPIO's to prevent coreboot warnings about resampling at boot. BUG=b:233771033 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I1c68fce817a2a98ce0e8f1d9771d6c630dd5e88a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-05-25mb/google/skyrim: Update DDI descriptor for HDMIJon Murphy
The HDMI port was specified as a display port. Update to allow for testing of 4k streaming. BUG=b:229771029 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ib4dc8a5c6110630cea768f81e34fd7b0a5a62657 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-05-25mb/google/skyrim: Remove unused GPIO tableJon Murphy
On Skyrim, the power and lid switches are managed by the EC and coreboot and the AP have no control over them within this context. Remove unused GPIO's to prevent coreboot warnings about resampling at boot. BUG=b:233771163 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ie369bb7d430bd0dd1f1c1f41bf543a9b18e34db1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64644 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-25mb/google/guybrush: Remove unused sleep GPIO tableJon Murphy
On Guybrush, there wasn't a need for a sleep GPIO table. Remove the TODO and filler table and function to reduce unnecessary function calls/overhead. Missed changes to variant.h in initial commit(already merged) BUG=b:232952508 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Idba1a9eeea5ea5f5922281668ec17c4f065a654d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64643 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-25mb/google/brya/var/taeko: Modify DPA value to 100 for taekoleo.chou
In order to meet the OEM's acoustic specifications, the pre-wake randomization time (DPA) is set to 100. BUG=b:232892200 TEST=build FW and checked DPA value by fsp log. Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I65e3fef581ee06fa049e831f246da1328a08518c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-25mb/google/brya: Replace space with tabSubrata Banik
Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3dfc5862fdcc663d9e0adbfda30c940d43b49b4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-05-25mb/google/kukui: Add LPDDR4X MT53E2G32D4NQ-046 WT:C supportKevin Chiu
Separate and add LPDDR4X MT53E2G32D4NQ-046 WT:C support for burnet/esche ID#1: MICRON - MT53E2G32D4NQ-046 WT:C BUG=b:225121354 BRANCH=none TEST=1. emerge-jacuzzi coreboot 2. power on test ok Change-Id: If720d7bcf185c5c0149a82125ec068fc75e5b3cd Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64069 Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-25mb/google/nissa/craask: Change pen garage wake to EV_ACT_ANYTyler Wang
Follow google stylus spec. The Stylus-Present GPIO MUST be a wake pin that interrupts the system in active operation when the stylus is removed or inserted. BUG=b:229938024 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Id6ee977fbda3118229677aa76e5394f5592c3da8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-05-24mb/google/skyrim/baseboard/devicetree: enable S0ixFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia6c5b3f83b66a2d54611ada3cb97ddda4b655d00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64606 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-24mb/amd/chausie,majolica: don't select HAVE_ACPI_RESUMEFelix Held
The Chausie and Majolica boards use S0ix which is mutually exclusive with S3, so don't select HAVE_ACPI_RESUME. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1d1bf33ad017dfbf908e0a195949998668c8e137 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64605 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-24mb/google/brya: Set eMMC dll tuning parameters for NissaUsha P
Add support for MB level dll tuning. This patch sets the eMMC dll tuning parameters to default values needed. There was issue observed on some eMMC devices which failed to boot in HS400 mode.EV team suggested the intermediate eMMC dll tuning parameters that needs to be set. We observed these values helped to fix the issue. While we get the verified default values set from FSP directly, adding it here to use it as the custom dll values needed. BUG=b:230403441 TEST=Build and boot nivviks board. Verify the eMMC dll parameters are overridden. [INFO ] usha: After override dll_params [INFO ] usha: emmc_tx_cmd_cntl=505 [INFO ] usha: emmc_tx_data_cntl1=909 [INFO ] usha: emmc_tx_data_cntl2=1c2a2828 [INFO ] usha: emmc_rx_cmd_data_cntl1=1c1b1d3c [INFO ] usha: emmc_rx_cmd_data_cntl2=10049 [INFO ] usha: emmc_rx_strobe_cntl=11515 Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I27771b663ce9808e5a5ef4b36c136ad78f924376 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-05-24mb/google/brya/var/kinox: Set the physical location of each USB portDtrain Hsu
Set custom_pld of each USB port (both Type A and C) with actual physical location values. BUG=b:214025396 TEST=Build and boot to Chrome OS Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ic84b9aae1501e36c2794382aabcf8225eef7783b Reviewed-on: https://review.coreboot.org/c/coreboot/+/64594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Won Chung <wonchung@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-24mb/google/brask/variants/moli: Remove stop pin declaration for LANRaihow Shi
Remove the stop pin declaration for LAN. Confirmed with LAN vendor, 8111K do not need to implement stop pin. It caused S0ix fail. BUG=b:231400227 TEST=Build and suspend_stress_test -c 5 pass Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Iae33068c4622f91d5cebb867e4b10f3834ce8bd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-24mb/google/brask/variants/moli: add fw_config for usb retimerRaihow Shi
add USBC0_RETIMER into 2, 3 bits for usb retimer. BUG=b:232486478 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Idaf2e53387476d344d2c838a6e762f5a4c582989 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-05-24mb/google/brya/var/kinox: Update the DPTF parametersDtrain Hsu
Follow the Thermal_paramters_list-0520.xlsx to modify DPTF baseline PL1 values. 1. Modify baseline PL1 min_power from 15000 to 12000. 2. Modify baseline PL1 max_power from 17000 to 25000. BUG=b:231380286 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ibd3098ee6bbf964cffddfcc9a4600cb7d81162d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64595 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Ricky Chang <rickytlchang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-24mb/google/brya/variants/nivviks: Add DPTF passive and critical policies for ↵Vidya Gopalakrishnan
Nivviks Add DPTF passive and critical policies for ADL-N Nivviks design. Temperature threshold for triggering Passive Policy is set to 75C and Critical Policy is set to 85C respectively for TSR0/1. BUG=b:224884901 BRANCH=None TEST=Build FW and test on Nivviks board. Verified thermal throttling successfully when participant reaches temp threshold as per Passive Policy. Also, verified system shutdown when Temperature of participants are reaching threshold as per Critical policy. Change-Id: I5c9b9e8c2489c7da501ca136e2aa6fbc764bf400 Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64466 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-24mb/google/brya/baseboard/nissa: Enable DPTF for Nissa variantsVidya Gopalakrishnan
BUG=b:224884901 BRANCH=None TEST=Build FW and test on Nivviks board Change-Id: I3f5e8dd3d2ff517e27b0b08a0173f094bc6043bd Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-05-24mb/intel/ehlcrb: Adjust TSN GBE settings in devicetreeLean Sheng Tan
Set PCH TSN link speed to 1 Gbps and enable MultiVC for all TSN ports. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I8d43c3ba8f02645c8ad2993f76e610d838b0151a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Praveen HP <praveen.hodagatta.pranesh@intel.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-05-24mb/google/brya: Create kuldax variantDavid Wu
Create the kuldax variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:233380254 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_KULDAX Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I95c04768bbed8657d2858bcd66fc041f56910b8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-05-24mb/google/brya/var/volmar: Add wifi sar tableRen Kuo
1. Add wifi sar table for volmar 2. Set EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG BUG=b:233319626 TEST=emerge-brya coreboot-private-files-baseboard-brya coreboot chromeos-bootimage Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: I09069bbc3a41b66ec9a88cfede46acc067209b01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2022-05-24mainboard/google/corsola: Fix incorrect timestamps in the eventlogYidi Lin
Timestamp '2000-00-00 00:00:00' is considered as the invalid format. Enable RTC to fix incorrect timestamp format in the eventlog. BUG=b:232035991 TEST=check the timestamp field in /var/log/eventlog.txt Change-Id: I8d9822075377734ef4a609ddeee79385fe7af0f0 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
2022-05-23mb/siemens/mc_ehl: Disable RAPLUwe Poeche
Disable RAPL for all mainboards based on mc_ehl for stable real time mode of CPUs. Test: Boot mc_ehl1 with this patch and ensure the bits in the MCBAR register are cleared. Change-Id: Ie58a4b6444d5be088ac2b25ff0a2f5cd33120ace Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-22mb/google/guybrush: Remove TODO for ESPI functionsJon Murphy
The feature request was moved to Skyrim in the interest of time and effort. The bug was updated to reflect this, and the comment should be removed from the monkey island code base BUG=b:232952508 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Id4ca43692aa56b6dba2f7acc1f924b30c1e966ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/64558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-22mb/google/guybrush: Remove unused sleep GPIO tableJon Murphy
On Guybrush, there wasn't a need for a sleep GPIO table. Remove the TODO and filler table and function to reduce unnecessary function calls/overhead. BUG=b:232952508 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ic51ee4845d663acf34f050f7b3abf57a7c247c88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-21mb/gogle/skyrim/devicetree: enable display HDA deviceFelix Held
The HD audio controller of the GPU on bus A device 0 function 1 wasn't enabled, so it didn't get resources assigned. Enable it to fix this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib9a4129ce594c5dd59f70e855fef5f2c04ebb9c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64554 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-21mb/gogle/skyrim/devicetree: enable audio coprocessor deviceFelix Held
The ACP device on bus A device 0 function 5 wasn't enabled, so it didn't get resources assigned. Enable the ACP device to fix this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifc9376314213e9d624756519f703d508411cb1bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/64553 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-21mb/gogle/skyrim/devicetree: enable crypto deviceFelix Held
The crypro device on bus A device 0 function 2 wasn't enabled, so it didn't get resources assigned resulting in this the Linux kernel error: [ 38.582036] pci 0000:04:00.2: attach allowed to drvr ccp [internal device] [ 38.582064] ccp 0000:04:00.2: enabling device (0000 -> 0002) [ 38.582175] ccp 0000:04:00.2: ioremap failed [ 38.582178] ccp 0000:04:00.2: initialization failed [ 38.582181] ccp: probe of 0000:04:00.2 failed with error -12 Enable the crypto device to fix this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia812df6e59f3767dcbaa908fa620b62619590f85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64552 Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-21mb/siemens/mc_ehl2: Invert PHY IRQ from falling edge to rising edgeMario Scheithauer
There are three external Marvell PHY 88E1512 on this mainboard. The PHY IRQ comes with a falling edge but the EHL MAC side needs a rising edge signal. For that reason, we need an inversion of the IRQ polarity. Change-Id: Id3caf582b4434b046779f5733e6ad9b57528ce35 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-21mb/google/nissa: Change pen garage wake to EV_ACT_ANYEric Lai
Follow google stylus spec. The Stylus-Present GPIO MUST be a wake pin that interrupts the system in active operation when the stylus is removed or inserted. BUG=b:233159811 TEST=EC wake event work as expected. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Icf609c647e19914684a93c89022f2cd4888a67ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/64538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-05-21mb/google/brya/var/craask: Generate SPD ID for supported memory partTyler Wang
Add supported memory parts in mem_parts_used.txt, and generate SPD id for this part. H9JCNNNBK3MLYR-N6E BUG=b:229938024 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Ibb111cddc00a0d066ef9792d974a6e4ad263cc99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-05-21mb/starlabs/lite/glk: Correct indendation in devicetreeSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I780e2765059ad7473fe5f33c50dd0d8a561151fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/64390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-05-21mb/google/nissa/var/craask: Disable pen garage and WFC based on fw_configTyler Wang
BUG=b:229938024 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Ib5770f02a6d524417be6723f7f70aa80d9452f62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-05-21mb/google/nissa/var/craask: Switch LTE-related GPIOs settings based on fw_configTyler Wang
If the LTE USB DB is connected, enable LTE-related settings. Otherwise, disable LTE-related settings. BUG=b:229938024, b:229048361, b:229040345 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I37719cee48370a04534067aa64a3aa77e453948a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-05-20mb/google/brya/var/crota: Enable SaGvTerry Chen
Enable SaGv support for crota BUG=b:229600878 TEST=FW_NAME=crota emerge-brya coreboot Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: Ibc06ef19e9fbbc91ef650a4ac060ce2b7c5c25d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-05-20mb/google/dedede/beadrix: Update FW_CONFIG probe for daughter board LTETeddy Shih
To make sure daughter board LTE existing, we update probe to DB ports value of FW_CONFIG field, (https://partnerissuetracker.corp.google.com/issues/226910787#comment11) as well as, refer to Google Henry and Ivan comments (https://partnerissuetracker.corp.google.com/issues/226910787#comment14) BRANCH=dedede BUG=b:226910787 TEST=on beadrix, verified by FW_NAME=beadrix emerge-dedede coreboot. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I9ab4412b614ec665fbafc998756b805591982b65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivan Chen <yulunchen@google.com> Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-20mb/google/nissa: Configure the external V1p05/Vnn/VnnSx rails for NereidV Sowmya
This patch configures external V1p05/Vnn/VnnSx rails for Nereid to achieve the better power savings. * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3, S4, S5 , S0 states. * Set the supported voltage states. * Set the voltage for v1p05 and vnn. * Set the ICC max for v1p05 and vnn. Kit: 646929 - ADL N Platform Design Guide BUG=b:223102016 TEST=Verified all the UPD values are updated with these configs. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I1df4ea10798354f41fe9cce0f8c478930517207c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-05-20mb/google/nissa: Configure the external V1p05/Vnn/VnnSx rails for NivviksV Sowmya
This patch configures external V1p05/Vnn/VnnSx rails for Nivviks to achieve the better power savings. * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3, S4, S5 , S0 states. * Set the supported voltage states. * Set the voltage for v1p05 and vnn. * Set the ICC max for v1p05 and vnn. Kit: 646929 - ADL N Platform Design Guide BUG=b:223102016 TEST=Verified all the UPD values are updated with these configs. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: If8da0dfe3059087526f74042be3c8b7e4a7ece82 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-05-20mb/intel/adlrvp: Configure the external V1p05/Vnn/VnnSx railsV Sowmya
This patch configures external V1p05/Vnn/VnnSx rails for adlrvp-n to achieve the better power savings. * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3, S4, S5 , S0 states. * Set the supported voltage states. * Set the voltage for v1p05 and vnn. * Set the ICC max for v1p05 and vnn. Kit: 646929 - ADL N Platform Design Guide BUG=b:223102016 TEST=Verified all the UPD values are updated with these configs. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I06298eb1aec07eae34420c5736e912c707fefbc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-05-20mb/google/brya: Disable PCH USB2 phy power gating for primusCasper Chang
The patch disables PCH USB2 Phy power gating to prevent possible display flicker issue for primus board. Please refer Intel doc#723158 for more information. BUG=b:221461379 TEST=Verify the build for primus board Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I4d7d52bdeafe8b1b55822b5c8d040c94ce1f3878 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-20mb/google/brya/acpi: Add support for NBCI _DSM subfunctionTim Wawrzynczak
The Nvidia GPU supports another function named NBCI (NoteBook Common Interface), which has some subfunctions which are required for the Nvidia kernel driver to consume. The specification for this function comes from the Nvidia GN20 Software Design Guide. BUG=b:214581763 TEST=build Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I19eb9417923d297a084d6f5329682e91cd506a9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-20mb/google/brya/var/agah: Select INCLUDE_NVIDIA_GPU_ASLTim Wawrzynczak
The agah variant will include an Nvidia GN20 series GPU, therefore select the INCLUDE_NVIDIA_GPU_ASL Kconfig to include the respective ASL code into the DSDT. BUG=b:214581763 TEST=build patch train Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Icc718d01506ccb4dd42841239e96926f4ddaa9c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-20mb/google/brya: Add PEG and initial Nvidia dGPU ASL supportTim Wawrzynczak
Some brya variants will use a GN20 series Nvidia GPU, which requires quite a bit of ACPI support code to be written for it. This patch lands a decent bit of the initial code for it on the brya platform, including: 1) PEG RTD3 methods 2) DGPU power operations (RTD3 and GCOFF, NVJT _DSM and other Methods) 3) NVOP _DSM method There will be more support to come later, this is all written to specifications from the Nvidia Software Design Guide for GN20. BUG=b:214581763 TEST=build patch train Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ifce1610210e9636e87dda4b55c8287334adfcc42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-05-20mb/siemens/mc_ehl2: Quick fix for PSE TSN phy interface typeLean Sheng Tan
Based on quick fix on this commit 7b0fe59be (soc/intel/ehl: Fix logical bug for PseTsnGbePhyInterfaceType), disable PSE TSN SGMII as the original intention is to set the PSE TSN phy interface as RGMII. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Id2e05b19f156621a945110791038bc0d19a0aad0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-05-20mb/google/skyrim: Expose SKU and board ID to Chrome OSAmanda Huang
Select EC_GOOGLE_CHROMEEC_SKUID and EC_GOOGLE_CHROMEEC_BOARDID to provide common routine for reading skudid and boardid from Chrome EC. BUG=b:229052726 TEST=emerge-skyrim coreboot chromeos-bootimage Check the corresponding directory gets mounted to /run/chromeos-config/v1 Change-Id: I6aff02d29d44e95cd9b9e9485593c81f0d4a4b0e Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-05-20mb/google/brya/variants/crota: Configure audio codec IRQ typeTerry Chen
The audio codec used by crota has a level-sensitive interrupt, therefore configure the GPIO pad as level-sensitive. BUG=b:230418589 TEST=emerge-brya coreboot and verified pass Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I588c21e44b9bb17cd5a48bf5f22465ec328496e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-20mb/google/skyrim/var/skyrim: Add better descriptors for USB endpointsJon Murphy
Fix descriptors for USB ports to align with their function and placement with respect to the schematics. BUG=N/A TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: If57bebf9bffd4616c437ec655b64cab3298ac08e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-20CBMEM: Change declarations for initialization hooksKyösti Mälkki
There are efforts to have bootflows that do not follow a traditional bootblock-romstage-postcar-ramstage model. As part of that CBMEM initialisation hooks will need to move from romstage to bootblock. The interface towards platforms and drivers will change to use one of CBMEM_CREATION_HOOK() or CBMEM_READY_HOOK(). Former will only be called in the first stage with CBMEM available. Change-Id: Ie24bf4e818ca69f539196c3a814f3c52d4103d7e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-19mb/google/brya/var/kinox: Remove stop pin declaration for LANDtrain Hsu
Remove the stop pin declaration for LAN. Confirmed with LAN vendor, 8111K do not need to implement stop pin. It caused S0ix fail. BUG=b:232327947 TEST=Build and suspend_stress_test -c 5 pass Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I9bdaa28cd879c1ea7de2de8afb25761df39bcfc8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-19mb/google/nissa: Rework LTE GPIO configurationReka Norman
Currently, the LTE pins are enabled in gpio.c, then disabled in fw_config.c if LTE is not present. However, since there's a short delay between mainboard_init() and fw_config_handle(), this means that when LTE is not present GPP_H19 (SOC_I2C_SUB_INT_ODL, used for the SAR sensor) will be floating for a short period of time. Rework the GPIO config so that the LTE pins are disabled in the baseboard, then enabled in fw_config.c for variants using LTE. However, this doesn't work for WWAN_EN and WWAN_RST_L since they need to be enabled in bootblock. So these are instead enabled in the variant gpio.c, then disabled in fw_config.c if LTE is not present. BUG=None TEST=LTE still works on nivviks Change-Id: I9d8cbdff5a0dc9bdee87ee0971bc170409d925a2 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-05-19mb/google/dedede/beadrix: Update PCIe and SATA pins for Realtek RTL8822CE ↵Teddy Shih
suspend To make sure Realtek RTL8822CE suspend stress test smoothly, we remove 1c.7 as wireless LAN (WLAN) connects the signal PCIE_4 and it will map to 1c.7. refer to Intel Simon comment (https://partnerissuetracker.corp.google.com/issues/230386474#comment12), as well as, remove redundant 17.0 and 1c.6 that both are described by baseboard/devicetree.cb BRANCH=dedede BUG=b:230386474 TEST=on beadrix, verified by Realtek RTL8822CE can run suspend stress test properly. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: Ib418eed57f07afaa6b397b42a057808eab142f7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivan Chen <yulunchen@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2022-05-18mb/google/brya/var/crota: Add reset and enable delay time for rtd3-coldTerry Chen
This CL adds the delay time into the RTD3 sequence, which will turn off the eMMC controller (a true D3cold state) during the RTD3 sequence. We checked power on sequence requires enable pin prior to reset pin delay of 50ms and add delay of 20ms to meet the sequence on various eMMC SKUs. Based on BH799BB_Preliminary_DS_R079_20201124.pdf in chapter 7.2. BUG=b:231291431 TEST=USE="project_crota" emerge-brya coreboot chromeos-bootimage Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: Id9bed46e801602f3f327753053ec6a1ceb0656e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-05-18mb/google/nissa: Change EC wake interrupt to IRQEric Lai
EC wake event doesn't work. Nissa has a separate EC wake pin. SCI only is not handled by EC, so we need to set dual route to wake the system. BUG=b:229142661 TEST=EC wake event work as expected. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ide1f4a2494bb0a64b11ab4c5135fc43d2a635f74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-05-18intel/common/block: Provide RAPL and min clock ratio switches in commonUwe Poeche
There are two APL specific config switches for RAPL and min. cpu clock (APL_SKIP_SET_POWER_LIMITS, APL_SET_MIN_CLOCK_RATIO). These switches could be used in future in other CPU platforms. Move them to common code instead of having them just for one SOC. Test: Make sure that the clock ratio (MSR 0x198) and the RAPL settings (MSR0x610) do not change with this patch applied on mc_apl{1,4,5} mainboard. Change-Id: I3d63d1b9b6c96586a3c20bf8c1d8001b1d7c4bed Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-17mainboard/**/devicetree.cb: Fix typoAngel Pons
repalcement ---> replacement Change-Id: I486170e89f75fa7c01c7322bb8db783fd4f61931 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64404 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-17soc/intel/elkhartlake: Enable SMBus depending on dev stateAngel Pons
Program the `SmbusEnable` FSP UPD according to the SMBus PCI device's state in the devicetree. This avoids having to manually make sure the SMBus PCI device and the `SmbusEnable` setting are in sync. Change-Id: I275a981f914a55dc57a75e7d436912ff0255a293 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64402 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-17mb/google/brya/var/mithrax: update overridetree and KconfigJohn Su
1. Update override devicetree based on schematics. 2. Update Kconfig based on schematics. BUG=b:229191897 TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Ia28ae16f609fda6d90558e69b2d41139dbe533fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/64329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-05-17mb/google/brya/var/mithrax: Generate RAM ID and SPD fileJohn Su
Add the support RAM parts for mithrax. Here is the ram part number list: DRAM Part Name ID to assign K4U6E3S4AA-MGCR 0 (0000) K4UBE3D4AA-MGCR 1 (0001) H9HCNNNBKMMLXR-NEE 0 (0000) MT53E1G32D2NP-046 WT:A 2 (0010) MT53E1G32D2NP-046 WT:B 1 (0001) BUG=b:229191897 BRANCH=None TEST=emerge-brya coreboot Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I2d19721a44f0176365a81da30d2f49b68a14df7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-05-17mb/google/brya/var/mithrax: update gpio settingsJohn Su
Configure GPIOs according to schematics BUG=b:229191897 TEST=emerge-brya coreboot Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I31a1e02b2fa3d2075efbf488cd611b6c5a88500f Reviewed-on: https://review.coreboot.org/c/coreboot/+/64289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-05-17soc/intel/skylake: Hook up FSP hyper-threading setting to option APIFelix Singer
Hook up the hyper-threading setting from the FSP to the option API so that related mainboards don't have to do that. Unless otherwise configured (e.g. the CMOS setting or overriden by the mainboard code), the value from the Kconfig setting `FSP_HYPERTHREADING` is used. Also, remove related code from the mainboard kontron/bsl6, since it is obsolete now. Change-Id: I1023d1b94acb63f30455c56b394b68059deaaa16 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-05-17mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridgeMario Scheithauer
On this mainboard there are legacy PCI devices connected behind a PCIe-2-PCI bridge. Not all clock outputs of this bridge are used. This patch disables the unused PCI clock outputs on the XIO2001 bridge. Change-Id: Iedbf0abfa554e0a6ad5b1d1741f4e9934103d171 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63931 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-17mb/google/brya/var/kinox: Set memory SMBus addresses to 0x52, 0x50Dtrain Hsu
Follow the Kinox_schematic_R01_20220418.pdf to set memory SMBus addresses to 0x52, 0x50. BUG=b:231398371 TEST=Build and boot to OS with either 1 or 2 DIMM slots populated. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I32bb4f62a6b8a485ac757a60f5d16adb69109e2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/64333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-17mb/google/nissa: add RO_GSCVD section to WP_ROKangheui Won
This area is used for storing AP RO verification information. BRANCH=none BUG=b:227801913 TEST=build and boot nivviks Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: If5c03aca56e659d61c31613b284a55d0eba0d843 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-05-16mb/siemens/mc_ehl2: Enable TSN GbE driverMario Scheithauer
This variant uses all three EHL Ethernet GbE-TSN Controller so enable the TSN GbE driver in order to set the needed MAC addresses. The required function to retrieve a valid MAC address was already implement in the common mainboard.c for mc_ehl. TEST: - Boot mc_ehl2 into Linux and check MAC addr via 'ip a' Change-Id: Ia052c44feb606f9e1d31d047f2acc67e3226a895 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-16mb/siemens/mc_ehl2: Set PCH TSN link speed to 1 Gbps in devicetreeMario Scheithauer
TSN runs in SGMII mode on this mainboard. This requires setting the link speed to 1 Gbps. Change-Id: I9f1da971b4de5671d6d38be6dbc50edbbe20d157 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-16mb/siemens/mc_ehl2: Adjust PSE TSN settings in devicetreeMario Scheithauer
This mainboard uses all three internal Ethernet GbE-TSN controllers. Two of them are initialized by the Programmable Services Engine (PSE). This patch enables the Serial Gigabit Media Independent Interface (SGMII) mode for GbE PSE0 and GbE PSE1. By setting PCH PSE DMA pins to host owned, the IO is under control of the IA processor cores through system software. TEST: - Boot mc_ehl2 into Linux and check inet addr via 'ip a' Change-Id: I74e660548b2c44d5dbdb6023d5a36cfdd7e96f43 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-16mb/google/brask/variants/moli: remove DB_OPT from overridetreeRaihow Shi
Both option-HDMI and option-DP use the same setting of vbt, and ABSENT is just physically remove option board from motherboard, so it just need one vbt, and it don't need the fw_config to decide which vbt will be return. BUG=b:231769131 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I1f8cdcbc05ed3bc689d29261e4fd4d700326dce8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16mb/google/brask/variants/moli: return the default VBTRaihow Shi
Both option-HDMI and option-DP use the same setting of vbt, and ABSENT is physically remove option board from motherboard, so set default vbt has option-DP setting and only return it. BUG=b:231769131 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I440143dabcf04c103f2a4420a7e4afb8ec12ec1c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16mb/google/guybrush/devicetree: use defines for ComboPhyStaticConfigFelix Held
Use the existing definitions from FspUsb.h instead of magic values for the ComboPhyStaticConfig settings in the mainboard's devicetree. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2707d017909b7516e5d8711c8f4e2914165ed10d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-16google/cyan: Clean up write_protect_state()Kyösti Mälkki
The commentary was wrong, write_protect_state() is only called in ramstage at the moment, and only if MRC_SETTINGS_PROTECT is selected. Implementation of get_gpio() eventually does the MMIO read, so BOARD_GOOGLE_CYAN was not a special case. Change-Id: I96ca871110bcf2fc1485bd042ed137d51b822a20 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-05-16mb/google/brya: Consistently put void before __weak attributeTim Wawrzynczak
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ic59cccdf0fb88fc71a440170ee40b73dd8736a33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>