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2020-03-25superio/nuvoton/nct5104d: add chip config option to reset GPIOsMichał Żygowski
Define a chip option to explicitly soft reset all enabled GPIOs to default state. TEST=boot FreeBSD 11.2 on PC Engines apu1, change GPIO configuration using nctgpio module and check whether GPIOs are reset after reboot Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Iae4205574800138402cbc95f4948167265a80d15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-25mb/facebook/monolith: Configure COMB to 0x3e8Wim Vervoorn
The 2nd COM port's base address defaults to 0x2f8. Current software for this system expects the port at 0x3e8. Configure COMB to use 0x3e8 instead of 0x2f8. BUG=N/A TEST=tested on facebook monolith Change-Id: Ibb462bad5f0594e0b5c8dea6e02cd42d58d999ab Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-25mb/intel/jasperlake_rvp: Update FMAP for jslrvpMeera Ravindranath
Remove unused SMM_STORE space and use it for RW_LEGACY area BUG=None TEST=None Change-Id: I5724b860271025e8cb8b320ecbd33352ef779660 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-03-25mb/google/dedede: Update EC_MKBP_INT_L configurationKarthikeyan Ramasubramanian
The concerned GPIO is configured as an open drain at the Embedded Controller side without an external pull-up. This causes leakage in the PP3300_A rail. So configure the GPIO to have a weak internal pull-up at the SoC side. BUG=b:151680590 TEST=Build the mainboard. Ensure that there are no leakages in the PP3300_A rail. Change-Id: I5553cf40adb92edc0fecab5c875ec8d72063ba7b Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-25mb/intel/jasperlake_rvp: Add config check for lid switchMaulik V Vaghela
We should only define function to get lid switch and recovery mode switches when CHROMEEC_SWITCHES is not available. Correct this to avoid compilation issues BUG=None BRANCH=None TEST=jslrvp code compilation is fine Change-Id: I2445d40da1540c9d8c8c5fc845a4f38a5abf983e Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39585 Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-25mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVPRonak Kanabar
Add memory initialization parameters for Jasper Lake RVP boards Jasper Lake RVP supports two variants, one with memory LPDDR4 and another with DDR4 Based on board id, mainboard will pass correct memory parameters to the fsp. BUG=None BRANCH=None TEST=Check compilation for Jasper Lake RVP and check memory training passes. Change-Id: Idc92363a2148990df16c2068c7986013d015f604 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39195 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-25acpi: correct the processor devices scopeMichał Żygowski
The ACPI Spec 2.0 states, that Processor declarations should be made within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated and is removed here. Additionally add processor scope patching for P-State SSDT created by AGESA, becasue AGESA creates the tables with processors in \_PR scope. TEST=boot Debian Linux on PC Engines apu2, check dmesg that there are no errors, decompile ACPI tables with acpica to check whether the processor scope is correct and if IASL does not complain on wrong checksum, run FWTS Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I35f112e9f9f15f06ddb83b4192f082f9e51a969c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39698 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-25mb/ocp/tiogapass: Enable IPMI KCSJohnny Lin
A bigger than zero value of bmc_boot_timeout must be set for KCS ipmi_get_bmc_self_test_result() to run, otherwise the self test result will be error and won't write SMBIOS type 38 table. Here we set 60 seconds as the maximal self test timeout. Tested=Check if the BMC IPMI response data and SMBIOS type 38 on OCP Tioga Pass are correct or not. Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: I3678973736a675ed22b5bc9da20a2ca947220f4b Reviewed-on: https://review.coreboot.org/c/coreboot/+/38995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-03-25mb/pcengines/*/devicetree: remove non-existing NCT5104d LDN 0xeMichał Żygowski
Nuvoton NCT5104d has no LDN 0xe according to its datasheet. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I0d34218d88b779b08c380d2396ff9ab9253597fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/38851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-03-25mb/pcengines/apu2: enable PCIe power management featuresMichał Żygowski
Enable ASPM L0s and L1, Common Clock and Clock Power Management for all PCIe ports. TEST=boot Debian linux and check new PCIe capabilities appear in lspci Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I0a4c83731742f31ab8ef1d326e800dfdc2abb1b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-25mb/pcengines/apu2: add reset logic for PCIe slotsMichał Żygowski
PC Engines apu2 had many problems with PCIe cards detection. The cards were inconsistently detected when booted from G3, S5 or after a reboot. AGESA can reset PCIe slots using GPIO via callback. Use it to reset the slots that support using GPIO as reset signal. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I8ff7db6ff85cce45b84729be905e6c895a24f6f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-24drivers/intel/gma: Ditch `link_frequency_270_mhz` settingNico Huber
The `link_frequency_270_mhz` setting was originally used by the native graphics init code for Sandy/Ivy Bridge, which is long gone. The value of this information (which board had it set) is questionable. The only board that had an LVDS panel and set it to 0 was the ThinkPad L520, where native graphics init was never reported to work. Also, the native graphics init only used it for calculations, but never confi- gured the hardware to use a specific frequency. A look into the docu- mentation also doesn't reveal any straps that could be used to confi- gure it. Change-Id: Ieceaa13e4529096a8ba9036479fd84969faebd14 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39763 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-24drivers/intel/gma/acpi: Reduce display switching stubsNico Huber
_DCS, _DGS and _DSS are required by specification. However, we never implemented them properly, and no OS driver com- plained yet. So we stub them out and keep the traditional behavior in case an OS driver checks for their existence. The old implementations also only returned static values as there never was any write to their GNVS variables. The TRAP() that was called in one place is actually implemented by some ThinkPad's SMI handler as docking event. However, as the call precedes these SMI handlers in coreboot history, it's most likely an accident. Change-Id: Ib0b9fcdd58df254d3b2290900e3bc206a7abd92d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-03-24mb/google/hatch: Give first NIC in Puff idx 1 for vpdEdward O'Callaghan
The format for VPD has changed s.t. the first NIC should always have a zero concat to the end. drivers/net supports this with the workaround of setting the idx to 1. The longer term fix is to adjust all the respective boards to shift back by one and adjust drivers/net friends to remove the 'special casing' of idx == 0. Background: https://chromeos.google.com/partner/dlm/docs/factory/vpd.html#field-ethernet_macn BUG=b:152157720 BRANCH=none TEST=none Change-Id: I510428c555b92398a5199b346dffb85d38495d74 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-23mb/pcengines/apu2/mptable.c: add GNB IOAPIC to MP TableMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I385339761b3e1b5dcadb67b8ca29b1518c2db408 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-23acpi: Change Processor ACPI Name (Intel only)Christian Walter
The ACPI Spec 2.0 states, that Processor declarations should be made within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated and is removed here for Intel CPUs only. Tested on: * X11SSH (Kabylake) * CFL Platform * Asus P8Z77-V LX2 and Windows 10 FWTS does not return FAIL anymore on ACPI tests Tested-by: Angel Pons <th3fanbus@gmail.com> Change-Id: Ib101ed718f90f9056d2ecbc31b13b749ed1fc438 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-23mb/gigabyte/ga-h61m-ds2v: Fix PCIe port numbersAngel Pons
A certain somebody (that would be me) forgot how to count, it seems. Change-Id: Iac0ac5827ca242c465a2e8be92a823c8fc9b2935 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39741 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-23mb/gigabyte/ga-h61ma-d3v: Correct PCIe port setupAngel Pons
Coalescing is not needed, as all PCIe ports are used. Change-Id: Icf31f6672e0a54d119a6537da1b52c42f9cee823 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39740 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-23mb/gigabyte/ga-h61m-*/devicetree.cb: Add missing IRQAngel Pons
IRQ 0x70 was not declared for device 2e.7, and coreboot whined about it. Change-Id: If40aa390722cf253169003129b31f20543fde5dd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39739 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-23mb/gigabyte/ga-h61ma-d3v: Correct subsystem IDAngel Pons
Linux does not handle either value in any special way, though. Change-Id: I833cb94e65b9ddfb79edbcdd0216c70740aa4a16 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-23src/mb/google/volteer: Add camera ACPI configurationDaniel Kang
Add camera ACPI configuration for Ripto/Volteer BUG=None BRANCH=None TEST=Build and boot Ripto or Volteer. Start camera app and able to capture images. Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Change-Id: I2b47ccd989192273a29f09bf097e12e357929334 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-03-23mb/google/volteer: Enable PD_MCU devicePrashant Malani
This is required for PD notifications on the cros_ec driver. BUG=b:150649744 TEST=Boot volteer with this patch and verify that PD notifier events are being generated. Signed-off-by: Prashant Malani <pmalani@chromium.org> Change-Id: I2e72320b025a3dfa7412181586cb142a4503eda5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-23mb/pcengines/apu1/mainboard.c: Add SMBIOS type 16 and 17 entriesMichał Żygowski
Use information provided by AGESA to fill the SMBIOS memory tables. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Id73de7c2b23c6eb71722f1c78dbf0d246f429c63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-23mb/tglrvp: Update Audio AIC settings for Tiger LakeSrinidhi N Kaushik
Update Audio AIC UPD settings and gpio pad configs for Tiger Lake. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I45935b79f6fa4ad66238eead9258a4f15feec508 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-03-23src/mb/intel/tglrvp: Fix board config flag for TGL-UP4 camera ACPIDaniel Kang
Camera ACPI had an incorrect board config flag for TGL-UP4. BUG=None BRANCH=None TEST=Build and boot TGLRVP-UP3 or UP4. Start camera app and able to capture images. Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Change-Id: Ided0e146a9240169d3f1f27a86218ac1a942b899 Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-03-23mb/google/dedede: Update SPD index for waddledeeKarthikeyan Ramasubramanian
Micron memory part uses SPD Index 0. BUG=b:152005386 TEST=Build the mainboard. Change-Id: I990a95b13d636148f0f922fd5c6d4e489d35ed2c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-23src: capitalize 'APIC'Elyes HAOUAS
Change-Id: I487fb53bb2b011d214f002fc200ade2f128a4cc6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-20mb/google/dedede Add Audio support for waddledooAamir Bohra
1. Configure Audio GPIOs. 2. Set i2c4 configuration. 3. Update PCH HDA configuration TEST=Verify codecs gets listed with aplay -l command. Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Signed-off-by: Yong Zhi <yong.zhi@intel.com> Change-Id: Ic0516c7a8fee79ce17343a7f42895d6ef534fec9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-03-20drivers/generic/max98357a: Allow custom _HID from configAamir Bohra
Add HID field in max98357a_config and allow mainboards to set it. Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: I22d2d078a9a4eb6ab330da8439737ff5133086d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39286 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-20mb/**/gma-mainboard.ads: Use SPDX for GPL-2.0-onlyAngel Pons
Change-Id: I005bf205142d4d8c5e12378f33d2100d278fa174 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-03-20mb/**/gma-mainboard.ads: Use SPDX for GPL-2.0-or-laterAngel Pons
Change-Id: I78f06b54a6a03d565cf86f1d7bdf37965c3f6ad0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-03-20mb/**/gma-mainboard.ads: Remove copyright statementsAngel Pons
They are already in AUTHORS. Change-Id: I315c0c57babfa239e3d7c501a4183b8996999e6e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-03-20mb/google/nightfury: Update overridetree.cbSeunghwan Kim
Updating devicetree to enable ELAN touchpad and ELAN touchscreen on nightfury BUG=none BRANCH=firmware-hatch-12672.B TEST=built and verified touchpad and touchscreen worked Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Change-Id: Ieba6558ce3897ce2f95f51ed667465d84b4ab189 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-03-20mb/hp/z220: Fix VGA graphics initPatrick Rudolph
The VGA port has the DDC on port B. Select the correct Kconfig and fix graphics init failing on VGA. Tested on HP Z220, libgfxinit reports success and SeaBIOS is displayed on the connected VGA monitor. Change-Id: Ie5ec1a2d4606a21e1dc4217ff6fefe5ee35ac543 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-19mb/asrock/b85m_pro4: Add new mainboardAngel Pons
This is a µATX mainboard with a LGA1150 socket and four DDR3 DIMM slots. Working: - All four DIMM slots - Serial port to emit spam - Some USB ports - Integrated graphics (libgfxinit) - HDMI and DVI - Intel GbE - All PCIe ports - Both PCI ports behind the ASM1083 PCI bridge - At least one SATA port - RAM initialization with MRC binary - Flashing with flashrom - S3 suspend/resume - Rear audio output - VBT - SeaBIOS to boot Arch Linux Not working: - PS/2 keyboard (detected as mouse) Untested: - The other audio jacks - S/PDIF - VGA - EHCI debug - Front USB headers - Non-Linux OSes - TPM header - Parallel port Change-Id: I10a16dfc56f2aa88648c8aaaba4feab40c491504 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36770 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-18src/mainboard/g/octopus: Enables GMM in the devicetree for octopusFranklin He
Adds GMM into the baseboard of Octopus For GLK, PCI device 3 is GMM according to Document#: 569262(Glk EDS Vol-1 rev2-7) Related to Gerrit review 39579 BUG=b:151115705 BRANCH=None TEST=Flashed final image on Chromebook Change-Id: I75b4a835c18c5eeb542b7f7b89deea45a31e47bd Signed-off-by: Franklin He <franklinh@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-18mb/google/dedede: Support integratred BT enumerationAamir Bohra
The integrated BT is routed via USB2 port 8, add USB configuration to support integrated BT enumeration. Change-Id: I46d8c92ba57cd72a91ee15ef4d11f07824c29e9a Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-03-18mainboard/[g-p]*: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I426518e8e18de1c8efcfb7ecb0835df3e257dca1 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39608 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-18mainboard/google: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I09cc279b1f75952bb397de2c3f2b299255163685 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-03-18mainboard/[^a-p]*: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I18e513cefc373b1cd70d31d1159928cc948a8476 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-03-18mainboard/[a-f]*: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I57fc98788bb47df16d6aedd0f0701e9991801743 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-03-17src/mb/intel/tglrvp: Update camera ACPI configurationDaniel Kang
* Change power sequence to make it closer to ov8856 sensor data sheet version 2 * Handle different PWREN GPIO pins for up3 and up4 * Add link frequencies definitions to sensor side * Clean up format BUG=None BRANCH=None TEST=Build and boot TGLRVP U or Y. Start camera app and able to capture images. Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Change-Id: Ic11a36f1f82fe425c1a5796847ce020007064403 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39529 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-17src/soc/intel/tigerlake: Fix incorrect use of Field objects in ASLRizwan Qureshi
Method RAOW is assuming that the first argument is a Field object and writing to it expecting the register to get updated. However, the callers are passing in the value of the Field object instead. This eventually is resulting the IMGCLK not getting enable/disabled on the platform. Fix this by sending the exact address of the register to be updated. Also MCCT was setting the clock frequency in both case i.e, Clock Enable and Disable. Split the MCCT method in two, MCON and MCOF to fix the sequencing like below MCON: Set frequency Enable clock MCOF: Disable clock Also, make use of MCON and MCOF methods for camera clock control in tglrvp. This is to avoid the buildbot marking the patch unstable. BUG=None BRANCH=None TEST=Build and Boot waddledoo board and verified that IMGCLKOUT for world facing camera is enabled/disabled and able to capture images. Build and Boot Tiger Lake RVP board and verified that IMGCLKOUT for world facing camera is enabled/disabled and able to capture images. Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Change-Id: I8b886255d5f38819502ae1f4af0851b5a0922b22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39498 Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-17mb/google/octopus: Add custom SAR values for Foob360Peichao Wang
Foob360 would prefer to use different SAR values. Since Foob360 sku id is 9. BUG=b:149362272 BRANCH=octopus TEST=build Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I8cc5d73629990f19d2c1044debdba4990c54d07e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com>
2020-03-17mb/purism: remove duplicate ACPI power buttonMatt DeVillier
These platforms use the standard fixed function power button and do not need a second power button device declared or the kernel will end up with two devices reporting the same event. Same change was applied to all google mainboards in CB:27272 which contains more detail. Change-Id: I17c85e43493530d04f4fa13f33bec6d027cb3147 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39577 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-17mb/google/dedede: Add waddledee variantKarthikeyan Ramasubramanian
Add initial support for waddledee variant board. BUG=b:151576904 TEST=Build the mainboard and variant board. Change-Id: I20d41fbbb78c7fd2f964a97ffebbc9c3bbfb1c5c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-16mb/intel/tglrvp: Enable ISH driver and register firmware nameli feng
BRANCH=none BUG=b:145946347 TEST=boot to OS with TGL RVP UP3, then copied ISH firmware to host file system /lib/firmware/intel/tglrvp_ish.bin check "dmesg |grep ish", it shows: ish-loader: ISH firmware intel/tglrvp_ish.bin loaded cros_ec_ishtp: Chrome EC device registered Those means shim loader in coreboot has loaded ISH firmware, and firmware is running successfully. Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Signed-off-by: li feng <li1.feng@intel.com> Change-Id: I1ee8050aef6ec0828f16ef2695b5347278caa820 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39481 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16mb/51nb/x210: correct battery ACPIMatt DeVillier
The X210 EC reports battery values in broken mAh. These have to be adjusted by 10000 * DGVO, as documented in https://github.com/torvalds/linux/blob/master/drivers/acpi/battery.c. Taken from https://github.com/harrykipper/coreboot, commits 2f68f138adb25605e5715896636cf33f6de5bd95 c1c72cc43708a6647f263a767c39cf3072908e20 Change-Id: Ie097272443b18b16c3937034f874d3b5a6bdd62a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39142 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16mb/51nb/x210: update devicetreeMatt DeVillier
- Add USB ports for SD card reader, fingerprint reader, and internal port. - Enable PcieRpClkReqSupport on NVMe root port, correct values for ClkReq/ClkSrc. - Improve comment for M.2-2230 USB port (BT) Parts derived from x210_test branch of HarryKipper's repo: https://github.com/harrykipper/coreboot Change-Id: Ib64629ada4726e5edc080608f71a51f56a9b747c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-16mb/51nb/x210: add libgfxinit supportMatt DeVillier
Derived from x210_test branch of HarryKipper's repo: https://github.com/harrykipper/coreboot Test: build/boot x210, test eDP, MiniDP, VGA outputs Change-Id: Ie2b79b236a458ebd243c992d6e615e41930eeb50 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-16mb/51nb: Add support for the 51nb X210Matthew Garrett
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes: * EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different All hardware appears to work as expected, although the SD reader is untested. Signed-off-by: Matthew Garrett <mjg59@google.com> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-15mb/google/kahlee/nuwani: support new Elan touch panel for NuwaniTommie
This is new Elan touch screen IC, which includes touch panel and USI pen. BUG=b:151514167 TEST=build bios and verify touch screen works fine Signed-off-by: Tommie Lin <tong.lin@bitland.corp-partner.google.com> Change-Id: I98801b8c31812637f71d7eaaa0f12b47901dc47a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-03-15nb/intel/nehalem: Rename to ironlakeAngel Pons
The code is for Arrandale CPUs, whose System Agent is Ironlake. This change simply replaces `nehalem` with `ironlake` and `NEHALEM` with `IRONLAKE`. The remaining `Nehalem` cases are handled later, as changing some of them would impact the resulting binary. Tested with BUILD_TIMELESS=1 without adding the configuration options into the binary, and packardbell/ms2290 does not change. Change-Id: I8eb96eeb5e69f49150d47793b33e87b650c64acc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38941 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15mb/asus/p8z77-m_pro: Use uppercase for *PRO*Paul Menzel
Consistently use the official uppercase spelling. Change-Id: I2e2d62389d1b965f4a391080a10e7f97fa787d14 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39350 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15mb/intel/tglrvp: Enable CNVi in devicetree for Tiger Lake UP3Srinidhi N Kaushik
Enable CNVi in devicetree and add gpio pad configs for CNVi BUG=none BRANCH=none TEST=Build and boot tglrvp Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I71146960e0d53dae87946a0365dac6f224a72391 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39464 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15mb/google/hatch: Create palkia variantKane Chen
Add Palkia as a variant of Hatch. BUG=b:150254194 BRANCH=none TEST=none Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I6a303d9fc2be9ea358ad66cd648738187c974193 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38860 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15mb/google/volteer: Use generic SPD filesNick Vaccaro
Volteer uses 4 bits (hardware straps) to indicate what memory configuration the board is populated with (i.e. which SPD file to use for the populated memory). This allows for only 16 different SPDs for supporting Volteer and all future variants of Volteer. Currently, each memory chip needs its own SPD file, so we can only support 16 different memory chip options for Volteer and all of its variants. Generic SPD files are just SPD files that have been stripped down to contain only fields that are important for the memory controller (strips out items like vendor info, for example). Using generic SPD files allows for more than 16 different memory options given it's no longer a 1-to-1 mapping as similar memory modules from different vendors can share the same generic SPD file. BUG=b:147857288 TEST="emerge-volteer coreboot chromeos-bootimage", flash ripto and verify ripto boots to kernel and "cat /proc/meminfo" reports 8GB of memory. Change-Id: I17bd4f4a00b4e3bbaf845d6d321962c11569a186 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39423 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-14mb/google/dedede: Configure WLANKarthikeyan Ramasubramanian
Turn on CNVi device. Turn on PCIe Root port that hosts WLAN device. Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used for WLAN - both CNVi and M.2. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I9bb8e57cdb688bc544929c94af380b9ef1d936a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-14mb/google/dedede: Add BT Disable GPIO configurationKarthikeyan Ramasubramanian
Disable the BT module in bootblock and enable it in ramstage. This allows for loading the BT firmware during reboot. TEST=Build and boot the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I0406a68ffcab2675a1aedb212cb7c8508a5b61fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/39446 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-14mb/google/drallion: Enable GEO SAREric Lai
Enable GEO SAR function. BUG=b:150347463 BRANCH=drallion TEST=NA Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Iace9aa0245840328aa13920512747ca7f60e85dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/39467 Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-14mb/intel/tglrvp: Update GPIO settingWonkyu Kim
Update GPIO reset type from PLTRST to DEEP. DEEP setting is more conservative for S3/S4/S5. Detail information is bug. BUG=b:151305120 TEST=Build and boot to OS Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ie7d08560ea2ef3623bbd4734b30c80e707869c7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/39476 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-13mb/google/volteer: Enable Audio DSP UPDSrinidhi N Kaushik
Provide settings for configuring the link between HD-Audio controller and display unit for purposes of HDMI/DP Audio playback. BUG=b:144708516, b:148385924 TEST=none Change-Id: I225faac68729b28be65b4d8f1f83769a874f84ff Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39356 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-13mb/google/hatch/Kconfig: Disable VBOOT_EARLY_EC_SYNC on PuffEdward O'Callaghan
Early ec sync needs to be disabled for EFS2 to function. BUG=b:151115320 BRANCH=none TEST=none Change-Id: I384d072d9614a5cd30837f7cdfb777ad5e4f6b19 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-03-12mb/google/dedede: Enable trackpad supportPandya, Varshit B
1. Configure trackpad interrupt GPIO. 2. Set i2c0 configuration. 3. Add trackpad ACPI support. TEST= Verify trackpad working. Verify I2C SCL frequency below 400Khz on trackpad operation. Change-Id: I52c578aef591f5be90fb709bab4c8342ea9729e6 Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-03-12mb/google/hatch: Create nightfury variantraymondchung
Create new variant and build for nightfury. BUG=b:149226871 TEST=FW_NAME="nightfury" emerge-hatch coreboot chromeos-bootimage Change-Id: If08692f4a2d216c57499098cc0e35abd708d99d4 Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2020-03-12mb/google/volteer: configure L1Substate for PCIeWonkyu Kim
Limit PcieL1Substate for RP9, RP11 for ES1 NVMe warm reboot workaround. Reference: #613582 Tiger Lake PCH-LP Sightings Report issue id #1409566330 BUG=none BRANCH=none TEST= boot to OS and check warm reboot with NVMe Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ie85bf71c43427e326ef2ba674da4566f8f51495a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-03-11mb/google/dedede: Add ACPI configuration for USB portsKarthikeyan Ramasubramanian
Enable USB ACPI driver. Add ACPI configuration for all the USB ports. Since one of the USB ports is used for Bluetooth configure the reset_gpio used by that port. TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I3e7b8f00102c96dcc295601359d3ecfbcd1bea00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-03-11mb/intel/tglrvp: Enable Hybrid storage modeWonkyu Kim
BUG=b:148604250 BRANCH=none TEST=Build and test booting TGLRVP form NVMe and Optane Check PCIe lane configuration Show all the NVMe devices lspci -d ::0108 Show all the NVMe devices and be really verbose lspci -vvvd ::0108 Print PCIe lane capabilities and configurations for all the NVMe devices. lspci -vvvd ::0108 | grep -e x[124] Print all the PCIe information of the device ae:00.0 lspci -vvvs ae: Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I5fc8fa0897ad006de9ebe20115bf3033e1e1b499 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
2020-03-11mb/google/dedede: Add SPD hex file for Samsung memory partMeera Ravindranath
BUG=b:150154457 BRANCH=none TEST=Build dedede, flash and boot to kernel. Change-Id: I7248861efd1edd5a0df0e17d39a47c168cab100e Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39348 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-11mb/google/drallion/variants/drallion: Set PCH Thermal Trip point to 77°CSumeet Pawnikar
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown when S0ix is enabled. BUG=None BRANCH=None TEST=Verified Thermal Device(B0: D18: F0) TSPM offset 0x1c [LTT (8:0)] value is 0xFE on Drallion. Change-Id: I146068d8019859be1c27e2a8174dfe7909d42d0a Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2020-03-11mb/google/hatch: Add LP_4G_2133 SPDraymondchung
Add LPDDR3 4GB 2133MHz SPD file. BUG=b:149226871 TEST=Build and check cbfs has the spd.bin Change-Id: I1598774a87eecc76082286540beadaa3c26eda69 Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39271 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Philip Chen <philipchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-11mb/google/volteer: Enable pcie rp11 for optaneVenkata Krishna Nimmagadda
Optane memory module shows up as 2 NVMe devices in x2 config - NVMe storage device and NVMe Optane memory. Storage device uses rp9 and optane memory uses rp11. This patch enables rp11. Please note that these two share clk related pins. Configuring pciecontroller3 to be set from 2x2. This will by done by auto detecting optane memory: enabling HybridStorageMode. BUG=b:148604250 BRANCH=chromeos TEST='Build, boot and look for two NVMe devices with lspci on Volteer' Cq-Depend: chrome-internal:2501837 Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com> Change-Id: I5430829b496ed275e2e3bda3c0bf21c3d2132628 Reviewed-on: https://chrome-internal-review.googlesource.com/c/chromeos/third_party/coreboot-intel-private/jsl-tgl/+/2424428 Tested-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39420 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-11mb/google/volteer: Disable WWAN PCIeAlex Levin
Disable WWAN PCIe to allow WWAN enumerate as USB on Volteer. BUG=b:146226689 BRANCH=none TEST=lsusb shows WWAN device Change-Id: I04e49e3ec989d20ea3469fce06051c475b0ed0c8 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-11mb/intel/tglrvp: sync up variant folders with latest up3Wonkyu Kim
During intial UP4 patch, below UP3 patches merged which should be applied for UP4. https://review.coreboot.org/c/coreboot/+/39201 https://review.coreboot.org/c/coreboot/+/39229 Merge these patches to UP4 BUG=none BRANCH=none TEST=Build TGL UP4 Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I7b24cb2b0d03309cf67c6c21ddc2031a054f6110 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
2020-03-11mb/biostar/am1ml: Remove old reference to olivehillplusElyes HAOUAS
Change-Id: I219fb2c12bb865288364f6e48b1e3d64c14bc036 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-11mb/asus/am1i-a: Remove old reference to olivehillplusElyes HAOUAS
Change-Id: Idfb8c834ae63226546a4e2860d9b206ba0288718 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-11mb/amd/olivehillplus: Drop unmaintained ROMCC boardElyes HAOUAS
Remove unmaintained and unsupported old ROMCC board. This board wasn't hooked up for build. Change-Id: Ie79637c992874bd06009ed9b3e9f470b44e749b7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39064 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-11mb/amd/bettong: Drop unmaintained ROMCC boardElyes HAOUAS
Remove unmaintained and unsupported old ROMCC board. This board wasn't hooked up for build. Change-Id: I1bce09ba5041a6636f900de611846467653f35a9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-11mb/amd/db-ft3b-lc: Drop unmaintained ROMCC boardElyes HAOUAS
Remove unmaintained and unsupported old ROMCC board. This board wasn't hooked up for build. Change-Id: Ib4a95c650cc4d1cddc2ba530c12ce448a1943b34 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-11mb/amd/lamar: Drop unmaintained ROMCC boardElyes HAOUAS
Remove unmaintained and unsupported old ROMCC board. This board wasn't hooked up for build. Change-Id: Iaa812dc66ddc14c24263a68e73115502ba5e2417 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-11mb/google/puff: Enable cros_ec_keyb deviceKangheui Won
This is required to transmit button information from EC to kernel. BUG=b:150830342 BRANCH=None TEST=firmware_ECPowerButton test passes on puff Change-Id: I10ba9d55e8997ce2412deb0613cfcaa8f24f271d Signed-off-by: Kangheui Won <khwon@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-03-10mb/intel/{saddlebrook,kunimitsu}: Add macro for SaGv configPraveen Hodagatta Pranesh
Change-Id: Ia31da9997ba46c15cd385bf55e009cf299848b64 Signed-off-by: Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36423 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-10src: Remove unneeded 'include <arch/cache.h>'Elyes HAOUAS
Change-Id: I6374bc2d397800d574c7a0cc44079c09394a0673 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37984 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-10soc/intel/xeon-sp,mb/ocp/tiogapass: Don't fake binariesNico Huber
If we don't pretend to have binaries, there is no need to add fake ones. This also fixes building the default config. Change-Id: I8f933f24a734a9ce3d82ef57f7f234ee4dfa86e9 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39383 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-10mb/libretrend/lt1000: Add Libretrend LT1000 mainboardMichał Żygowski
Change-Id: I32fc8a7d3177ba379d04ad8b87adefcfca2b0fab Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-03-10mb/protectli/vault_kbl: Add FW6 supportMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I03e8e8db5d827fe113280f2a6376d364edf42870 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-03-10mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generationSrinidhi N Kaushik
This change uses drivers/intel/wifi chip for CNVi device and adds dynamic SSDT entires for CNVi also export wake gpio for CNVi BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check for SSDT entries for CNVi Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Icdbffa0c29c9e0849a6a99f8592b6f35c0bb3207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39315 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-10mb/google/volteer: set TcssXhciEn to 1Brandon Breitenstein
BUG=144874778 TEST=Built with Volteer recipe and verified USB functionality Change-Id: I6cbdbd8a4f65a0fe19e3fb8d7b60b8b849f104e7 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-09mb/google/dedede: Add PCIe Root Port ConfigurationKarthikeyan Ramasubramanian
Add configuration for all the PCIe Root ports and Clock Source. Configure the Root Ports as disabled and clock sources as not used. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I0a1ad7e056907e454a93f51c84e1d99f08b7bdef Reviewed-on: https://review.coreboot.org/c/coreboot/+/39166 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09mb/google/dedede: Configure EDP_HPD GPIOKarthikeyan Ramasubramanian
This enables display for use by payload. TEST=Build and boot the mainboard. Ensure that the screens displayed by payload are visible. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I5fcd70623b15ae39954242605e75b2c5ce02ff14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-09mb/google/dedede: Configure EC <-> AP GPIOsKarthikeyan Ramasubramanian
BUG=b:150869661 TEST=Build and boot the mainboard. Trigger apreset from EC console. Trigger reboot from AP console. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I0d6dd0b4264c11f7ee0ef436cc819b0bb92974f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39325 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09mb/google/dedede: Add GPIO listKarthikeyan Ramasubramanian
Leave all the GPIOs in not connected state so that they can be configured depending on the use-case. This is done to park the GPIOs in a known safe state. This will also help to ensure that the required GPIOs are configured when the concerned use-cases are enabled. Below GPIOs are configured in Native Function 1 and are required for boot-up. * VCCIN_AUX_VID0 * VCCIN_AUX_VID1 * AP_SLP_S0_L * PLT_RST_L * CPU_C10_GATE_L * GPDs BUG=None TEST=Build and boot the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I5293536f66a6b08c9c2d2a6281684755a0c0b1b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39114 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09mb/google/volteer: Enable FPMCU on volteerAlex Levin
BUG=b:147500717 TEST=none Change-Id: I32fa27b399127dbf8608e0556c77431d2dad652d Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-09mb/google/volteer: change two gpio settingsNick Vaccaro
- declare the FPMCU interrupt to be level-triggered - change EC_PCH_WAKE_ODL gpio to native function mode - corrected spelling of a signal name in a comment BUG=b:144933687, b:148179954 BRANCH=none TEST=none Change-Id: I62da900d0b71139e55b52d06ec09ca25106f73cd Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-09mb/protectli/vault: Add FW2B and FW4B Braswell based boards supportMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I553fd3a89299314a855f055014ca7645100e12e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-03-09mb/asus/p5g41t-m_lx: Do not set BSEL GPIOs in devicetreeAngel Pons
This mainboard has the FSB BSEL straps wired to SuperIO GPIOs. They are set up in romstage, so it makes no sense to clobber the registers with garbage in ramstage. Tested, my Asus P5G41T-M LX still boots and it does not need a full reset on almost every reboot. Change-Id: I6ea498119df44243ec42e3cb5c2903de32a17373 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39384 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09mb/asus/p5g41t-m_lx: Correct GPIO directionAngel Pons
Not all GPIO4 pins on the SuperIO are configured as outputs. Change-Id: Idf6350551a91c4c1a25a83e3fb9b1a6722a81c36 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-09mb/asus/p5qpl-am: Do not set BSEL GPIOs in devicetreeAngel Pons
This mainboard has the FSB BSEL straps wired to SuperIO GPIOs. They are set up in romstage, so it makes no sense to rewrite their values in ramstage. Tested, my Asus P5QPL-AM still boots. Change-Id: Ic47f96d12420ebcc70ab5cea940c4c09620c03ca Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-093rdparty/libgfxinit: Update submodule pointerNico Huber
Changes allow to use the integrated panel logic (power sequen- cing and backlight control) for more connectors. The Kconfigs GFX_GMA_PANEL_1_PORT and GFX_GMA_PANEL_2_PORT can now be set to any port, e.g. config GFX_GMA_PANEL_1_PORT default "DP3" Now that the panel logic is not tied to the `Internal` port choice anymore, we can properly split it into `LVDS` and `eDP`. This also adds Comet Lake PCI IDs which should still work the same as Kaby and Coffee Lake. Change-Id: I78b1b458ca00714dcbe7753a7beb4fb05d69986b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38921 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09mb/intel/tglrvp: Add memory config for Tiger Lake UP4Srinidhi N Kaushik
Add LPDDR4 memory configuration for Tiger Lake UP4 platform which includes 1. DQ/DQs Mapping 2. Board id Support 3. SPD indexing BUG=none BRANCH=none TEST= Build TGL UP4 successfully Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ibbd7036919c1a91ef12049d2af657f0a3597b57e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39365 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>