| Age | Commit message (Collapse) | Author |
|---|
|
The board's PCIe port descriptors have the PCIe engine disabled, so
update the devicetree accordingly.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic97a54c3cc762a36752d6b9f21467428912a9edd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68379
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9a429c0fd23eb3b52a19a974b22079d675e3506a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68318
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Since commit 60e9114c6210 ("include/device: ensure valid link/bus is
passed to mp_cpu_bus_init"), no dummy LAPIC device is required under the
CPU cluster device. Since the CPU cluster device is already present in
the Stoneyridge chipset devicetree, drop the whole CPU cluster part from
the mainboard's devicetrees.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8918c14be25ac9756926a9c6a2806a3dceced42a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68317
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
When using a Merlin Falcon APU, explicitly enable the PCIe root port at
B0D3F1. B0D3F0 is only a dummy PCI device function, but needs to also be
enabled in order for the actually used function to be usable. Prairie
Falcon doesn't have and PCI device 3 on bus 0, so remove D3F0 from the
common mainboard devicetree.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I01f9b9ac2a9ebd5899a093d97eb5b2d76d309f66
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68315
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enable the correct PCIe root ports in the devicetree so that the
configuration matches the PCIe port descriptors in
src/mainboard/amd/padmelon/bootblock/OemCustomize.c.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Idb00a65adcf2059d7432a8df08654bb0ba965e24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68314
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
PCI devices that aren't present in the devicetree will be treated as
enabled. Since the chipset devicetree that will be added in a follow-up
patch disables this device by default, explicitly enable the IOMMU
device on the Stoneyridge mainboards that don't disable it to keep the
same behavior.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4a2cdd00abe8309244829dc633dd8a9ca0038dfa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68313
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Since the devicetree files are passed to util/sconfig without being
processed by the C preprocessor, using #if in the devicetree won't give
the behavior that might be expected. Instead sconfig treats the #if as a
comment, but still processes all other lines. To get the intended
behavior, replace the C preprocessor usage in the devicetree by moving
the APU-specific parts to override devicetrees that get selected
according to the selected APU type.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iddd317b27a838849fa40c0fb77d942609104cf04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68312
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is no longer needed so remove it.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I82841c2114ceb5e7a46ce228fce63d24822098d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68084
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I80f3d2c90c58daa62651f6fd635c043b1ce38b84
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Switch from gpio_configure_pads() to gpio_configure_pads_with_override()
so variants can override romstage GPIO defaults. Rename baseboard
function and add an weak empty override function to be used by variants.
Will be used for touchscreen power sequencing in a follow-on commit.
Change-Id: I45586237919cd07a171beac57f3510e26338f67f
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Create the zombie variant of the herobrine reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:249180463
BRANCH=None
TEST=util/abuild/abuild -p none -t google/herobrine -x -a
make sure the build includes GOOGLE_ZOMBIE
Signed-off-by: Maulik Vaghela <maulikvaghela@google.com>
Change-Id: Ifecf0a6323b20012defbf14bd16ce2f1f41f4714
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
|
|
This change updates scl_lcnt, scl_hcnt, sda_hold value for I2C5.
BUG=b:249031186
BRANCH=brya
TEST=TP function is normal from EE check.
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I5e756b7d7e14cace24ef2dfbb323c840c867ae1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
|
|
HP Z220 series has PCI slot(s) but Interrupt Routing Table in ACPI
used to be missing, so one is added.
Note that the values within the added one are obtained from my own SFF
variant. If other variants have different values, please add them in a
manner similar to mb/gigabyte/ga-b75m-d3h/acpi/pci.asl.
Test result:
Log lines like
pci 0000:00:1e.0: can't derive routing for PCI INT A
ath9k 0000:04:00.0: PCI INT A: no GSI
disappeared from dmesg.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I8522b25ac46db2054302c8f2418927c722b157e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68334
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I66f99a5afbdd2b847a916a470a5def9a6d3999bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68335
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Strings in C are highly cursed. Use `snprintf()` to minimize the
potential of running into undefined behavior in the future.
Change-Id: I3caef25bc7676ac84bb1c40efe6d16f50f8f4d26
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68323
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
|
|
The `eeprom_read_serial()` function could return a non-NULL terminated
string if the serial in EEPROM has `HERMES_SN_PN_LENGTH` (32) non-NULL
characters. Make this impossible by adding an additional character for
a NULL byte in the static buffer, which always gets set to 0 (NULL).
Change-Id: I306fe1b6dd3836156afca786e352d2a7dca0d77c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68322
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
|
|
Configure PMC mux in devicetree.
Tested on StarBook Mk V with Ubuntu 22.04.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I297d5446e43357d97357f345668cf40dcd28502d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68083
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
Enable the P2SB so that the SPI is discoverable by the OS.
Change-Id: I49802f93a97a18ecc10f48d213619855728e1290
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67029
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Ie9655406c7afe7a22f131d35633a697c5bbde4e3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Fixes brightness controls on Windows 10.
Change-Id: I33ac1b5a17c95dbb1b166c38fcd639cdac439724
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
|
|
Windows hardware tests require this field not be "Reserved".
The System76 EC firmware does not report the wake type, so it is not
possible to know if the system was powered on from the power switch or
Wake-on-LAN. In the case WoL is used, this will report the wrong value.
Change-Id: I4653c6bce2a5f0a88281fc810df5646e44f90674
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
|
|
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I2da15db3d7fba4396c74800e531476c108cafe17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67421
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enable SRAM in devicetree so that resources are allocated properly
for it.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1d7ee4f950b31f2be6fb7bd107b5fe54785ed81a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67420
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enable the P2SB so that the SPI is discoverable by the OS.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ied7a6ea706e6da86182c109ab4813fa3fcebb1f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67419
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BRANCH=none
BUG=b:234776154
TEST=build and boot Nirwen UFS, copy ISH firmware to host
file system /lib/firmware/intel/adln_ish.bin
check "dmesg |grep ish", it should show:
ish-loader: ISH firmware intel/adlnrvp_ish.bin loaded
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I89782b0b7dde1fca0130472a38628e72dfd5c26c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
|
|
First of all, make sure that `get_board_settings()` never returns NULL.
If there's a problem, return predefined values for board settings.
If the board settings definition differs between coreboot and the BMC,
the CRC will not match. Allow coreboot to use the BMC settings provided
by older BMC firmware revisions which have less settings, if the CRC of
the first N bytes matches the expected CRC.
TEST=Boot coreboot master with BMC FW R04.05, observe board settings
being honored even though coreboot's definition has an extra option.
Change-Id: I0f009b21ef0850a2af6edef1818c770171358314
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67381
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch enables PD Sync for Rex.
BUG=b:248775521
TEST=Able to boot Google/Rex with PD sync enabled.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I749b5dea481c7546579e97f923f143dd17f831d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67819
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
|
|
Add a new zydron variant, which is a variant of brya's skolas
baseboard. currently copy the variant file from kano.
BUG=b:250787251
TEST=build pass
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I49a41678568daef80b7cd1e3ed60ce4763034f9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68130
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
birman is the reference board for the morgana SoC. It needs to be
updated to match the actual board design as well.
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I4b16854c954949217a76c3d4f04ddc4001f64337
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68196
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Create the frostflow variant of the skyrim reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:240970782
BRANCH=None
TEST=util/abuild/abuild -p none -t google/skyrim -x -a
make sure the build includes GOOGLE_FROSTFLOW
Signed-off-by: Chao Gui <chaogui@google.com>
Change-Id: I937e6562094968824e73bfa20390b3ec8b24dfa0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Write the value for reset cause registers to the EEPROM for debugging.
Change-Id: I827f38731fd868aac72103957e01aac8263f1cd3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67483
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Adjust the EEPROM layout to account for two new fields: board part
number and product part number. In addition, put them in a Type 11
SMBIOS table (OEM Strings). Also, rename a macro to better reflect
its purpose.
Change-Id: I26c17ab37859c3306fe72c3f0cdc1d3787b48157
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67759
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enable DRIVERS_GENESYSLOGIC_GL9750 for lisbon
BUG=b:246657849
TEST=FW_NAME=lisbon emerge-brask coreboot
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I74cd634700b2de16ae471e0a738b67a14fd82a50
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68168
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add the `eeprom_read_serial()` function to read serials from the EEPROM.
Note that there's only one buffer now: this means only one serial can be
accessed at the same time, and the buffer needs to be cleared so that it
does not contain old data from other serials. Given that the serials are
copied one at a time into SMBIOS tables, having one shared buffer is not
a problem.
Change-Id: I5c9781e4e599043be756514cfd6dd86dedcf580c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67275
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The PCH's SGPIO pads are connected to a buffer chip that is powered from
the always-on +3V3_AUX rail. For some cursed reason, when the SGPIO pads
stay configured as SGPIO when a Poseidon system shuts down, voltage from
the +3V3_AUX-powered buffer chip will leak into the +5V rail through the
SATA backplane. Just pulling the SGPIO pads low before the system powers
off stops the +5V rail from being cross-powered.
This issue has only been observed in S5, but it's very likely other
sleep states are affected as well. Thus, always pull the SGPIO pins
low before entering ACPI S3 or deeper because the power supply will
turn off in these states as well.
TEST=Obtain a Poseidon system, verify that the +5V rail is cross-powered
after going to S5. We measured 0.17V on our system, but voltages as
high as 0.6V were measured on other systems. Verify that unplugging
the SGPIO cable going to the SATA backplane results in the +5V rail
voltage dropping to 0V, which indicates that the voltage leakage is
exclusively coming from the SGPIO and SATA backplane. Finally, make
sure that the +5V rail voltage drops to 0V after going into ACPI S5
with this patch applied and the SGPIO cable connected.
Change-Id: Ic872903d5fcdd1c17e02b4c06d5ba29889fbc27d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
|
The intention of predefining driver strength is to avoid that the OS
SD-Card driver changes this setting.
Change-Id: I02fdac94462da1cd77f8dc972faf16f28d94c946
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
Change the TPM I2C freqeuncy to 1 MHz for pujjo.
BUG=b:249953707
TEST=On pujjo, all timing requirements in the spec are met.
Frequencies:
pujjo - 987.80 kHz
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: If99b5022a9b67e9c63c440a1e398d56bb2c467e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
|
|
Update parameters for all I2C devices.
After applied this patch, the measured the I2C frequency meets spec
BUG=b:249953708
TEST=FW_NAME=yaviks emerge-nissa coreboot
flash and measure the all I2C devices
1. I2C0 (TPM): 980.6 Khz
2. I2C1 (TouchScreen); 392.6 Khz
3. I2C3 （Audio): 394.9 Khz
4. I2C5 (Touchpad): 391.6 Khz
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I33c2891f17bc3c572bbfcbf30bbbdef9eb850ce7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
|
|
Add configuration to bump up the SPI flash bus speed from 66 MHz to 100
MHz starting the board version where required schematics update is done.
BUG=b:245949155
TEST=Build and boot to OS in Skyrim with 100 MHz SPI bus speed. Perform
warm and cold reboot cycles for 100 iterations each. Observe that the
boot time improved by ~115 ms compared to 66 MHz SPI flash bus speed.
At 66 MHz:
508:finished loading body 538,319 (83,806)
11:start of bootblock 1,196,809 (624,777)
14:finished loading romstage 1,236,905 (39,163)
970:loading FSP-M 1,237,056 (37)
15:starting LZMA decompress (ignore for x86) 1,237,073 (17)
16:finished LZMA decompress (ignore for x86) 1,358,937 (121,864)
8:starting to load ramstage 2,010,304 (0)
15:starting LZMA decompress (ignore for x86) 2,010,312 (8)
16:finished LZMA decompress (ignore for x86) 2,067,181 (56,869)
971:loading FSP-S 2,078,232 (7,999)
17:starting LZ4 decompress (ignore for x86) 2,078,253 (21)
18:finished LZ4 decompress (ignore for x86) 2,084,297 (6,044)
90:starting to load payload 2,316,933 (5)
15:starting LZMA decompress (ignore for x86) 2,316,947 (14)
16:finished LZMA decompress (ignore for x86) 2,339,819 (22,872)
Total Time: 2,464,338
At 100 MHz:
508:finished loading body 515,118 (59,364)
11:start of bootblock 1,115,043 (566,110)
14:finished loading romstage 1,146,713 (29,697)
970:loading FSP-M 1,146,865 (38)
15:starting LZMA decompress (ignore for x86) 1,146,881 (16)
16:finished LZMA decompress (ignore for x86) 1,249,351 (102,470)
8:starting to load ramstage 1,900,568 (1)
15:starting LZMA decompress (ignore for x86) 1,900,576 (8)
16:finished LZMA decompress (ignore for x86) 1,956,337 (55,761)
971:loading FSP-S 1,967,357 (7,930)
17:starting LZ4 decompress (ignore for x86) 1,967,377 (20)
18:finished LZ4 decompress (ignore for x86) 1,972,925 (5,548)
90:starting to load payload 2,205,300 (6)
15:starting LZMA decompress (ignore for x86) 2,205,313 (13)
16:finished LZMA decompress (ignore for x86) 2,227,087 (21,774)
Total Time: 2,349,804
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I5e8db22151fbc2db1f9e81b3644338348160736d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
|
|
use function to check if pci device is on a particular bus
number.
TEST: compiled and qemu run successfully
Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com>
Change-Id: I4a3e96381c29056de71953ea2c39cd540f3df191
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68103
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change updates scl_lcnt, scl_hcnt, sda_hold value for I2C5 to
follow I2C specification.
I2C_TCHPAD_SCL high period time is from 0.53 us to 0.6952 us.
I2C_TCHPAD_SDA hold time is from 0.13 us to 0.4623 us.
BUG=b:249031186
BRANCH=brya
TEST=EE check OK with test FW and TP function is normal.
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I5977f0dbba8924cc8a1c72c36358d6ba6f2de940
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67920
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
|
|
Configure eMMC DLL tuning values for Pujjo board.
BUG=b:241854926
TEST=Use the value to boot on Pujjo successfully.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Ic36c817fa546741e394668297ca43db3a45ee105
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68095
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
An optional dGPU can be connected to the second PEG bridge:
-[0000:00]-+-00.0 Intel Corporation Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller
+-01.0-[01]--
+-01.1-[02]----00.0 NVIDIA Corporation GK208M [GeForce GT 730M]
It's possible that the 01.0 bridge is never populated, but we have to
leave it on anyway so 01.1 can be enumerated.
Change-Id: Ieab7a7bf3b31b4ee9d9f12b5d827d866c87356e1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Given the embedded nature, the Halo SKU, SO-DIMMs and 1 DIMM per
channel, `mobile` seems to come closest.
Change-Id: Ia27f1e4dec0a0d06be3d8c08bfe82becd41a2149
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
BUG=b:250470706
TEST=Boot to OS on pujjo and check that stylus GPIO are
configured based on fw_config.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I4218748cb06426a918d89f688599c652062ac78c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68075
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
SMMSTOREv2 requires 64k min size, 64k alignment.
TEST=build skyrim with SMMSTOREv2 enabled
Change-Id: I3501b6036df9ee1049a92e26a7b72e53b4604f60
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
SMMSTOREv2 requires 64k min size, 64k alignment.
TEST=build guybrush with SMMSTOREv2 enabled
Change-Id: I78cb873a5634c659067367260cc7063fbd60d77a
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I714867d455c4e0d01d6cb1cb9dc64669fb41100c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Add variant specific cmos files, which avoid options like "FastCharge"
existing in platforms that don't support such options.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I04264cf72d47ef719acfd144d8bf9acb0ceccc11
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Add variant specific cmos files, which avoid options like "Thunderbolt"
existing in platforms that don't support such options.
This change also removes entries that were never used, including:
* smi_handler
* usb_always_on
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I359e5c5bbf29eb474f2d3bc42a8e80afc0a5d38a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
To support an RPL SKU on brya0, brya0 must use the FSP for RPL.
Select SOC_INTEL_RAPTORLAKE for brya0 so that it will use the RPL
FSP headers for brya0.
BUG=b:248126749
BRANCH=firmware-brya-14505.B
TEST=cherry-pick Cq-Depends, then "emerge-brya intel-rplfsp
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage",
flash and boot brya0 to kernel.
Cq-Depend: chromium:3893035, chrome-internal:4983198
Change-Id: I2dd84757532d734ad97b74ba960537d937fb313e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
|
|
Add a new THERMAL FW_CONFIG bitfield for describing power consumption
category of SoC.
BUG=b:250089101
TEST="emerge-brya coreboot chromeos-bootimage", flash and boot brya0
and skolas to kernel.
Change-Id: Iba3bd87abd4c112ceff4bbe51a7cf9eae3a694f2
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
|
|
1) Make the skolas FW_CONFIG field defintions compatible with the
brya0 FW_CONFIG field definitions to support skolas being a SKU of
brya0, and in sync with the config.star definitions for the FW_CONFIG
field for brya0 and skolas.
- brya0 specific changes:
1) remove WFC_MIPI_OVTI5675 definition (was 1)
2) redefine WFC_MIPI_OVTI8856 from 2 to 1
3) define new WFC_MIPI_KBAE350 camera type as 2
- skolas specific changes:
1) remove WFC_MIPI_OVTI5675 definition (was 1)
2) redefine WFC_MIPI_OVTI8856 from 2 to 1
3) define new WFC_MIPI_KBAE350 camera type as 2
2) Add support back in for UFC_MIPI_OVTI5675 in brya0 now that FW_CONFIG
defines are fixed.
BUG=b:248126749
TEST="emerge-brya coreboot chromeos-bootimage", flash brya0 and
verify it boots successfully to kernel and that WFC, UFC, and audio
works on skolas and brya0.
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Change-Id: I3be26e0a05f4dc08e5dc3f6ef7b71bdd8fd4f859
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
|
|
Add the RPL CPU power limits to brya0's power limit table to support
both the brya0 ADL sku and the new RPL sku.
BUG=b:248126749
TEST="emerge-brya coreboot chromeos-bootimage", flash skolas with
image-brya0.serial.bin and verify skolas boots successfully to kernel.
Change-Id: I2ac067f98f1ff8f86cff0ed0e15010f454d9c91c
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
The delayed return of certain fetch instruction from memory to
the UFS causes the OCP fabric to timeout on the transaction
and become non-responsive.
As recommended by the SoC and IP teams,program the
OCP fabric register to avoid the timeout in the OCP fabric.
This patch adds the following changes
1. Program the OCP fabric registers in the PS0 routine.
2. Move the ssdt contents of UFS to dsdt asl code to avoid
duplication of UFS device creation
BUG=b:240222922
TEST=Build and boot Nirwen UFS board, observe no system hang
during Chrome PLT test.
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I949a4538ea5c5c378a4e8ff7bb88546db1412df2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Select the config to separate the AMDFW binary from the verified boot
section.
BUG=b:203597980
TEST=Build Skyrim BIOS image and boot to OS with PSP verstage passing
the hash table and PSP verifying the binaries against the hash table.
Observe boot time improvement of ~120 ms while operating SPI bus at 66
MHz with PSP verstage enabled.
Before this patch series:
508:finished loading body 1,978,053,432 (201,518)
After this patch series:
508:finished loading body 7,948,797,849 (83,460)
Change-Id: I78ec6d28b4c5fc40bdade47489d58180a54dee4d
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
|
|
ChromeOS requires a custom SPL table. Update Kconfig to point to the
ChromeOS version of the SPL resident in the blobs directory.
Bug=b:245727030
Test=Boots
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I70dcb19983c970283ee887b78a18c0668e83d4b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67928
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
MSI PRO Z690-A WIFI DDR4 and MSI PRO Z690-A DDR4 are basically the
same boards, except the latter has no WiFi populated. Check the CNVi
WiFi presence and return correct SMBIOS product name string.
TEST=Check SMBIOS product name on both WiFi and non-WiFi variants in
Linux.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I5fedbce413dfb6a589a406d1e34e3e114ca6a40f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68078
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Adjust the Makefile to look for SPD source Makefile. The current
SPD guard isn't set up correctly and is attempting to build the
APCB with SPD when SPD isn't present.
BUG=b:249988439
TEST=util/abuild/abuild -x -t GOOGLE_MORTHAL --verbose
util/abuild/abuild -x -t GOOGLE_SKYRIM --verbose
util/abuild/abuild -x -t GOOGLE_WINTERHOLD --verbose
Change-Id: I9cf13acb1188309ea6a1e6bdacc37d80b01f70a8
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68018
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This pin was originally set as output in error. This should be
a input to behave like GPP_E16 on the older variants.
BUG=b:239721380
TEST=build
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: Ic0f793ff52adb425ae5378b88d2837bb9e58edd2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
|
The DPTF parameters were verified by the thermal team.
BUG=b:249446156
TEST=emerge-nissa coreboot chromeos-bootimage
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: Ic7e0c73815dd02b97d89f94fab09a241b6279830
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
|
|
Create the lisbon variant of the brask reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:246657849
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_LISBON
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: Ia31752765657054b28ea16b046b63c38a72f95bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
|
|
De-duplicate common initialization code (self-test and device
identification) and put it in a new ipmi_if.c unit, which is
supposed to work with any underlying IPMI interface.
Change-Id: Ia99da6fb63adb7bf556d3d6f7964b34831be8a2f
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
|
|
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I4721d24aecd53c51c66c7d448b7c331d50a09712
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ibc257c2306351614669bd25ac83c24475f80fc6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
This is a vboot feature, not a ChromeOS one, and unless selected by
vboot, compilation will fail in the non-ChromeOS + vboot build case.
TEST=build/boot skyrim w/vboot, w/o ChromeOS
Change-Id: If9a5343907457bf3319f045262fdddf7eae2f1cb
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67995
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This is a vboot feature, not a ChromeOS one, and unless selected by
vboot, compilation will fail in the non-ChromeOS + vboot build case.
TEST=build/boot guybrush w/vboot, w/o ChromeOS
Change-Id: I3108bcc8dfeacd99c9f5d36bd915d590292fef00
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67994
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This area relates to storing of AP RO verification information.
CONFIG_VBOOT_GSCVD is enabled by default for TPM_GOOGLE_TI50 and
guybrush is using TPM_GOOGLE_CR50.
Signed PSP verstage has the FMAP embedded. Since CB:67376 shifted the
RO section up by 8K, they were misaligned. Hence marking this area as
unused instead of removing the same to work around ChromeOS
infrastructure shortcoming.
Signed-off-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
Change-Id: Id852e5b5c1f777992a96a75143757f4df8d975b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67901
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
It turns out that one can use Kconfig options to specify values for
devicetree options, as long as the resulting expression is a compile
time constant. Use this to configure SaGv for Atlas: enable it by
default, but allow SaGv to be disabled manually for convenience when
testing. Enabling SaGv makes MRC train the RAM multiple times, which
takes a significant amount of time.
For further info on SAGV on ADL, please refer to Intel Doc 655258
(Alder Lake Datasheet) section 5.1.3.2.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Change-Id: I3c6ac25d414122c408f2348d12dba8dce909e567
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enable DPTC and No Battery Mode for Skyrim. This allows Skyrim to boot
without a battery or with a critically low battery.
DPTC remains disabled for the Winterhold and Morthal variants until it
can be tested on those boards.
BRANCH=none
BUG=b:217911928
TEST=Boot skyrim with low & no battery
Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: Icc4084476916cc8e142908d8e58baf7124568b8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67211
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change the TPM I2C freqeuncy to 1 MHz for nivviks and nereid, and in
the baseboard. Other nissa devices will be changed after verification.
This saves 11 ms of boot time on nivviks and nereid.
400 kHz:
504:finished TPM initialization 272,304 (35,730)
...
512:finished TPM PCR extend 526,250 (23,729)
513:starting locking TPM 526,250 (0)
514:finished locking TPM 535,106 (8,855)
6:end of verified boot 543,927 (8,821)
1 MHz:
504:finished TPM initialization 266,293 (30,747)
...
512:finished TPM PCR extend 513,711 (20,108)
513:starting locking TPM 513,711 (0)
514:finished locking TPM 521,311 (7,599)
6:end of verified boot 528,893 (7,581)
BUG=b:249201598
TEST=On nivviks and nereid, all timing requirements in the spec are met.
Frequencies:
nivviks - 972.01 kHz
nereid - 968.99 kHz
Change-Id: I9dd783527d4215ed7d79d69853a1f321ea2d8a28
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
Disable the external 1.05v VR in S0 as a fix for the
display flicker issue in ADL-N.
Please refer the Doc with ID 742988 for more details.
BUG=b:248249033, b:245970842
TEST=Verified that the display flicker issue is fixed.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: If9f40e6c37e80caceb726a8e5f4d4b14dc479858
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67654
Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
Disable the external 1.05v VR in S0 as a fix for the
Display flicker issue in ADL-N.
Please refer the Doc with ID 742988 for more details.
BUG=b:248249033, b:245970842
TEST=Verified that the display flicker issue is fixed.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Iaa53bfd99a550b2cffcdaee640ee3a429e93aef7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Commit c7204b5a4 [mb/google/guybrush: Enable backlight in the OS]
disabled the GPIO for the display backlight in favor of using ACPI
to enable it, but this breaks display output for payloads which do
not/can not enable the backlight GPIO themselves (edk2, grub, SeaBIOS).
Re-enable the GPIO for display backlight so that payloads other than
depthcharge work properly.
TEST=build/boot google/dewatt with Tianocore payload, verify payload
display visible.
Change-Id: I2519d779954ed89486045aa7de0b18f1c31a4374
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ie564d080955097b416943e772de6c62708ce5764
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
use is_enabled_cpu() on cycles over device list to check
whether the current device is enabled cpu.
TEST: compile test and qemu run successfully with coreinfo
payload
Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com>
Change-Id: If64bd18f006b6f5fecef4f606c1df7d3a4d42883
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67797
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
This patch de-selects EC software sync config and enable early
EC Software Sync.
BUG=b:248775521
TEST=Able to perform EC sync on Google/Rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6bf8018e8a3fd06bb98c82a27d12883fc8d3a5db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
|
|
Rename so table more indicative of when GPIOs are set, and so it can
be used for more than just setting PCIe GPIOs.
Rename the getter function to match.
Change-Id: I285602209072247895c2cb0830f3faf675328757
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Rename variant_base_gpio_table() to baseboard_gpio_table(), since the
GPIO table comes from the baseboard, and is overridden by a separate
table from the variant.
Drop the __weak qualifier as this function is not overridden.
Change-Id: Icebf7e11736929389227063039575a4c5ecf3840
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
This patch adds ACPI configurations of 8MP YHUX and 2MP CJFKF28-1
as world- and user-facing cameras of Rex.
BUG=b:246413264
TEST=Verified world- and user-facing cameras using Chrome Camera App on
Google/rex device.
Signed-off-by: Daniel Kang <daniel.h.kang@intel.com>
Change-Id: Iaaa16e491a66500606b3a9eb1d87f396641778e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
|
|
According intel Doc#634254 and Doc#608715
PS2/PS1 cross point = 5
PS1/PS0 cross point = 10
PS2 cutoff = 1.4*(PS2/PS1 cross point) = 7
1.3 is better magnification, it obtain by test
PS1 cutoff = 1.3*(PS1/PS0 cross point) = 13
BUG=b:241850120
BRANCH=brya
TEST='FW_NAME=vell emerge-brya coreboot'
Change-Id: I83e9682004e2c3644ad4a5565e6ab85be48ba22f
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
Xivu uses PCIE WLAN, so disable the CNVi WLAN/BT.
BUG=b:247120749
TEST=Boot to OS on xivu and check that WLAN/BT still works.
Change-Id: I968d383278bd50268d899cff82067ceb7c3ba5ed
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Ben Kao <ben.kao@intel.com>
|
|
Rename variant_base_gpio_table() to baseboard_gpio_table(), since the
GPIO table comes from the baseboard, and is overridden by a separate
table from the variant.
Drop the __weak qualifier as this function is not overridden.
Change-Id: I17db734784ce96cdf5e0486dc2ad057d73bfb15f
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Rather than duplicating the entire set of GPIOs from the baseboard, use
the variant_override_gpio_table() method like all other octopus
variants do.
TEST=build/boot ampton, dump GPIOs and verify unchanged.
Change-Id: I36aa25bbee7c21a51d9fdd40405f492082455d9c
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67803
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add support for the following two new memory parts to support a new
SKU that has two memory options that brya0 does not have:
MT53E2G32D4NQ-046 WT:C
MT53E512M32D1NP-046 WT:B
BUG=b:248126749
TEST="emerge-brya coreboot chromeos-bootimage", flash a skolas with
an image-brya0.serial.bin and verify it boots successfully to kernel.
Change-Id: I28667918e5a183339febdc054465effeac8bddbe
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67879
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Rename variant_base_gpio_table() to baseboard_gpio_table(), since the
GPIO table comes from the baseboard, and is overridden by a separate
table from the variant.
Drop the __weak qualifier as this function is not overridden.
Change-Id: I11814016d654bc2c2e6d24b3d18fb30d5b843fe9
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Rename variant_base_gpio_table() to baseboard_gpio_table(), since the
GPIO table comes from the baseboard, and is overridden by a separate
table from the variant.
Drop the __weak qualifier as this function is not overridden.
Change-Id: Id1e1a67608454466dc65bf4c4985cf4eba84c97d
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Rename variant_base_gpio_table() to baseboard_gpio_table(), since the
GPIO table comes from the baseboard, and is overridden by a separate
table from the variant.
Drop the __weak qualifier as this function is not overridden.
Change-Id: Ib8439e664defeafd2d08cffb74c997ab69230231
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Rename variant_base_gpio_table() to baseboard_gpio_table(), since the
GPIO table comes from the baseboard, and is overridden by a separate
table from the variant.
Drop the __weak qualifier as this function is not overridden.
Change-Id: Iaa3c9404919fd6c43596d7b27cfab43a1a5b0b21
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
This patch selects the SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES to allocate
TBT/USB4 root port resources for PCIe tunneling.
BUG=b:248328015
TEST=Built image and verified TBT/USB4 tunneling functions on Rex.
Change-Id: I69f4d26bb7b3d74dbda068add284a69f1bbeff40
Signed-off-by: zhaojohn <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
In order that GPP_H13 not use the GPIO override programming from its
baseboard (brya), explicitly program GPP_H13 to a output HIGH instead
of relying on the 20K pullup from the baseboard.
BUG=b:240617195
TEST=SSD still functional
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iddedebe2d5cfc0123932b14980d1268bcb147703
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
|
|
The next rev of this board will move the dGPU PEXVDD enable pin from
GPP_E10 to GPP_F12. This patch handles both the old and newer revisions
by using an ACPI Name to hold the GPIO # for PEXVDD enable. It also
cleans up the GPIO handling a little bit between board revs.
BUG=b:242752623
TEST=dGPU is functional and power sequencing tests still pass on board
rev 2
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Icc7968777f86ab07561b0a861b7d22ec714d1c34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
|
|
On Banshee, when the privacy switch is toggled the camera is
disconnected. Which means that we will never be able to tell the user
that the privacy switch is enabled when the camera is on, making the
virtual control unusable.
Remove the description.
BUG=b:248219472
BRANCH=firmware-brya-14505.B
TEST=none
Change-Id: I1a241bd889c0c1aae039510a0620748b2f7a6806
Signed-off-by: Ricardo Ribalda <ribalda@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Modify GXTP7863 generic.irq to generic.irq_gpio.
BUG=b:245082617
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: Iaf6cc6010132d5b33b06909ceb1069115a911b48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
This reverts commit 1a8eb6c02103727431ac1ea23f4f507e49f3cde7.
Reason for revert: migrating to the 32MB AP Firmware hence, need to
revert this CL.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibea1ad0cff008f9391cbda9e51899557b1e9c979
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
'Mendocino' was an embargoed name and could previously not be used.
Update references for consistency with the correct naming convention.
BUG=b:245727030
TEST=builds and boots to kernel
Cq-Depend: chrome-internal:4878294
Cq-Depend: chromium:3763392
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ic0248a872dfc92486658aa9bd92bed755dbf59d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67750
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
BIOS_ERR is inappropriate since the init message is informational.
Use BIOS_INFO instead.
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I6fc15291a6d177a1b9e258d08e165224e5e10b32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67733
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
EN_PP3300_EMMC has be changed to GPP_A21 for DP++ and it based on Moli GPIO Table_20220803.xlsx, so update enable_gpio for emmc_rtd3 by board_ver.
BUG=b:241370405
TEST=emerge-brask coreboot
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I129706861fd1fcf061371ce94352331ef44359d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Add the gma-mainboard.ads for display output definition and enable the
libgfxinit usage in mainboard Kconfig.
Change-Id: I7e7a44736a8136b5320821e744134c7d64c7f1b4
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67683
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Currently the `pch_pirq_init()` function in lpc_lib.c will program
PIRQ IRQs for all PCI devices discovered during enumeration. This
may not be correct for all devices, and causes strange behavior
with the Nvidia dGPU; it will start out with IRQ 11 and then after
a suspend/resume cycle, it will get programmed back to 16, so the
Linux kernel must be doing some IRQ sanitization at some point.
To fix this anomaly, explicitly program the IRQ to 16 (which we
know is what IRQ it will eventually take).
BUG=b:243972575
TEST=`lspci -vvv -s1:00.0|grep IRQ` shows IRQ 16 is programmed
at boot and stays consistent after suspend/resume.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I66ca3701c4c2fe5359621023b1fd45f8afd3b745
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67746
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
