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2022-11-04mb/google/brask/var/kuldax: Update PsysPL2 and PsysPmaxDavid Wu
Update PsysPL2 and PsysPmax. BUG=b:253542746 TEST=Make sure PsysPL2 and PsysPamx values set properly (through debug output) Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I0ffad751e8a99b282a5d05563a60745ee09e892c Reviewed-on: https://review.coreboot.org/c/coreboot/+/69155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-04mb/prodrive/atlas: Add IBECC Kconfig optionMaximilian Brune
Add an option on Atlas to enable IBECC (In Band Error Correction Code), which is currently needed for endurance testing. Test: start atlas mainboard with Linux. See in dmesg that IBECC (EDAC igen6) driver is loaded. Inject a fake error via debugfs and see in dmesg that Linux handles it. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I71ee2401136e2dc70b3164db6c99af03a3e1f346 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-11-04mb/google/rex: Fix fw_config probe for UFC and WFCKapil Porwal
Fix fw_config probe for UFC and WFC. BUG=b:255971791 TEST=Build Google Rex. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I5103e7da04004414d96f42057c105cf9fbf51b25 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-04mb/google/brya/var/lisbon: update USB topology in devicetreeKevin Chiu
update USB topology per the schematic design BUG=b:246657849 TEST=FW_NAME=lisbon emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I2976028d3efa20e25deedb34ffb8b3bab43b5f5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-04mb/system76/adl-p: Add Darter Pro 8Tim Crawford
The Darter Pro 8 (darp8) is an Alder Lake-P board. Tested with a custom TianoCore UefiPayloadPkg. Working: - PS/2 keyboard, touchpad - Both DIMM slots (with NMSO480E82-3200EA00) - M.2 NVMe SSD (with MZVL2500HCJQ) - M.2 SATA SSD (with WDS100T2B0B) - All USB ports - SD card reader - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Backlight controls on Windows 10 and Linux 6.1 - HDMI output - DisplayPort output over USB-C - Internal microphone - Internal speakers - Combined header + mic 3.5mm audio - S0ix suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 5.18.5 - Internal flashing with flashrom v1.2-703-g76118a7c10ed Not working: - Detection of devices in TBT slot on boot Change-Id: Icc84d6cc3aec7149d9b538305288bbe2b56d53e4 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-04mainboard: Include <cpu/cpu.h> instead of <arch/cpu.h>Elyes Haouas
Also sort includes. Change-Id: Iccb7f28a2c913ae0983bf224a03610d7fdd13c68 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03mb/google/brya/gaelin: Configure GPIO settingsRaymond Chung
Override GPIO pad configuration based on the latest gaelin schematic. BUG=b:249000573 BRANCH=firmware-brya-14505.B TEST=FW_NAME=emerge-brask coreboot Change-Id: I649ac5131393008787cbb403fc64b914de23312b Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-11-03mb/ocp/deltalake: Revert OVERRIDE_UART_FOR_CONSOLEJohnny Lin
This reverts commit f6efeae66c (mb/ocp/deltalake: Override uart base address via VPD variable). Both SOL and UART would use 0x2f8, disabling it can also avoid searching flash VPD during each UART tx. Change-Id: I453fdddbb883eb956bac708913c17bb581f75b9d Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-03mb/google/skyrim: Disable SD ASPMEricKY Cheng
Disable ASPM on SD until b/245550573 is root-caused/fixed. Logical_lane 1 on winterhold is EMMC device. Disable ASPM for suspend issue. BUG=b:249914847, b:245550573 TEST=emerge-skyrim coreboot chromeos-bootimage and test on whiterun proto emmc sku with suspend_stress_test -c 10 Change-Id: If080cdb517a3f22aa89c8053fb6bba9e931c6f76 Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68940 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02mb/google/skyrim: Use detect vs probed flag for touchscreensMatt DeVillier
Now that coreboot performs the necessary power sequencing, switch from using the 'probed' flag to 'detect' for all I2C touchscreens. This alleviates ChromeOS from having to probe to see which touchscreen model is actually present, prevents breaking ACPI spec by generating device entries with status 'enabled and present' which aren't actually present, and improves compatibility with upstream Linux and Windows. BUG=b:121309055 TEST=build/boot ChromeOS and Linux on skyrim, ensure touchscreen is functional, and ACPI device entry generated for correct touchscreen model. Change-Id: Id9e3089decf0f94a1358929684ce248e52cbe41f Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-11-02mb/google/hatch/var/kohaku: ensure FPMCU is power cycled on resetTarun Tuli
Leakage from the SPI CS line onto the FPMCU VDD rail was preventing the FPMCU from fully shutting down on AP reset. Instead of simply turning off the power rail, now ensure the CS line is not driven high until late in coreboot. This ensures it is completely off for the requisite minimum of 200ms (now measured at approx 1100ms). BUG=b:245953688 TEST=Confirmed FPMCU is still functional on Kohaku. Confirmed FpRebootPowerCycle unit test now passes BRANCH=Hatch Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I1e7e32f61c3ac1b3154d42821cc1dd4c5d3de303 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68819 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02mb/google/hatch: Add variant finalize support for hatch devicesTarun Tuli
Provide a variant_finalize() method and call to be invoked from mainboard_ops.final BUG=b:245953688 TEST=Hatch and variants build BRANCH=Hatch Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I9253ed4be1b08d0c7f65526c9b26dbcd00ffccc7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68821 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02mb/google/brya/var/lisbon: Enable SaGvKevin Chiu
Enable SaGv support for lisbon BUG=b:246657849 TEST=FW_NAME=lisbon emerge-brask coreboot pass RMT verification Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: Ic7d3203bfe06973b023a38d1aa3d69cce5c3a60c Reviewed-on: https://review.coreboot.org/c/coreboot/+/69013 Reviewed-by: Ricky Chang <rickytlchang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-02mb/google/brya/var/lisbon: Include driver for GL9763E for eMMC boot diskKevin Chiu
Support GL9763E as a eMMC boot disk BUG=b:246657849 TEST=FW_NAME=lisbon emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: Ibe579a913225b5241412bbb1b8ea995a5102a3bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/68888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-02mb/google/brya: enable PCIe RP12 for lisbon eMMC supportKevin Chiu
BUG=b:246657849 TEST=FW_NAME=lisbon emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: Ief8ca9cf845156ac761556d0eb49edb65894c001 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-02mb/google/corsola: Add new board 'voltorb'Mars Chen
Add a new kingler follower 'voltorb'. BUG=b:256737049 TEST=emerge-corsola coreboot Signed-off-by: Mars Chen <chenxiangrui@huaqin.corp-partner.google.com> Change-Id: Ic7175c38fcde76ab0360f62da161994ba2ee6a69 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-11-02mb/clevo/l140mu: work around PECI staying high when idle, blocking s0ixMichael Niewöhner
According to Intel doc# 575683 the PECI bus should be low when idle and is pulled up by clients with strong drive. However, for unknown reasons the bus stays high on this board, blocking s0ix entry. The PECI reference schematic in the ASPEED AST2400 BMC datasheet (actually not related to this board) says that a pull-down is *required* for the idle state. This might be just a requirement of this BMC, since this is nowhere documented in Intel datasheets, schematics or elsewhere. However, configuring a weak pull-down (20 k) on the PECI pad indeed solves this problem for now. Change-Id: I85193000af67cd2c0465bdbb58cdd51b68fd5b4f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68794 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02mb/clevo/l140cu: work around PECI staying high when idle, blocking s0ixMichael Niewöhner
According to Intel doc# 575683 the PECI bus should be low when idle and is pulled up by clients with strong drive. However, for unknown reasons the bus stays high on this board, blocking s0ix entry. The PECI reference schematic in the ASPEED AST2400 BMC datasheet (actually not related to this board) says that a pull-down is *required* for the idle state. This might be just a requirement of this BMC, since this is nowhere documented in Intel datasheets, schematics or elsewhere. However, configuring a weak pull-down (20 k) on the PECI pad indeed solves this problem for now. Change-Id: Ib5a6b0ad3553c2cf795037d6a1982102bcb04644 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68793 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02mb/clevo/l140cu: enable S0ixMichael Niewöhner
Enable S0ix for the board, as done in vendor fw. Change-Id: Ifdf93e1e599e7cc03fc02297eafb49d34b1f6172 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68792 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02mb/google/brya/var/gladios: use RPL FSP headersKevin Chiu
To support an RPL SKU on gladios, gladios must use the FSP for RPL. Select SOC_INTEL_RAPTORLAKE for gladios so that it will use the RPL FSP headers for gladios. BUG=b:239513596 BRANCH=None TEST=FW_NAME=gladios emerge-brask intel-rplfsp coreboot-private-files-baseboard-brya coreboot chromeos-bootimage Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: Ic30f7fe30eb0a3151cdf46fff609819056b2fbfe Reviewed-on: https://review.coreboot.org/c/coreboot/+/68570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-02mb/google/skyrim: Select GOOGLE_SMBIOS_MAINBOARD_VERSIONAmanda Huang
Select GOOGLE_SMBIOS_MAINBOARD_VERSION allows querying board revision from the EC. BUG=b:256723358 TEST=1. emerge-skyrim coreboot chromeos-bootimage 2. flash the image to the device and check board rev by using command `dmidecode -t 1 | grep Version` Change-Id: I97295083dbca1c285ef7359d86abac7315c654c9 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69087 Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-02mb/google/rex: Disable TBT PCIe rp1 and rp3 root portszhaojohn
Rex board only uses TBT PCIe root ports 0 and 2. This change disables rp1 and rp3 root ports. BUG=b:254207628 TEST=Booted to OS and verified rp1 and rp3 root ports were disabled. Change-Id: Ia5c1d657c0ad0482619d739f8949bc9168eac25b Signed-off-by: zhaojohn <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68854 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-11-01mb/{lenovo,packardbell}: Enable MEI deviceEvgeny Zinoviev
Enable the MEI in device trees of some Ibex Peak, Cougar Point and Panther Point boards where they have been disabled. Change-Id: I4327d19d3ed1a93a6466057f6eceed49ab9441c5 Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2022-11-01mb/google/brask/variants/moli: remove fan settingRaihow Shi
Disable Active Policy and remove fan setting to let ec control fan indenpendently. BUG=b:236294162 TEST=emerge-brask coreboot Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Ie8851800d30ebf4d948d6eaadda2387c8afe52d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-10-30mb/google/skyrim: Implement touchscreen power sequencingMatt DeVillier
Assuming variants have a touchscreen by default, set the enable GPIO high and hold in reset during romstage, then release reset in ramstage. This will allow the touchscreen to make use of the runtime I2C detect feature (enabled in a subsequent commit) so that an ACPI device entry is created only for the touchscreen actually present. Variants/SKUs which do not have a touchscreen (if any) can use the romstage/ramstage GPIO override tables to set the associated enable/ reset GPIOs to NC. BUG=b:121309055 TEST=build/boot skyrim with rest of patch series Change-Id: Ic4d7ac8f951bb94da2216a24dc85a96275c9d449 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-29mainboard/amd/chausie: Don't use APCB_FT6_UpdatableNikolai Vyssotski
This APCB binary is not used for coreboot builds. Coreboot does not support RW APCB. Change-Id: I4d317ae31cf226b5481619f1539abb6237033f7c Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-10-29mb/starlabs/*: Change the local version to KconfigSean Rhodes
Replace the string with a Kconfig option Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib11ddd04c44f47b94f4fc9eaed278d554d581b0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-10-29mb/siemens/mc_ehl: Remove spd.bin from CBFSWerner Zeh
The SPD data for DRAM init has moved into the hwinfo data structure and is therefore not used from spd.bin anymore. spd.bin will not receive any updates, changes will only be done in hwinfo. There is no reason to keep spd.bin around so remove it for both variants. Change-Id: Ie6091b655ba7ff2e01b684266ce34b85593b8623 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-10-29mb/google/brya/var/skolas: Adjust I2C3 CLK to meet 400 kHzAlanKY Lee
Fine tune I2C3 clock frequency under the 400 kHz. From 402.7 kHz to 382.9 kHz. BUG=b:255505160 BRANCH=firmware-brya-14505.B TEST=FW_NAME="skolas" emerge-brya coreboot chromeos-bootimage measure by scope with skolas Signed-off-by: AlanKY Lee <alanky_lee@compal.corp-partner.google.com> Change-Id: Ib6c3f895751387256378964ec76be45a4fcbba4e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-10-29mb/amd/birman: Update Birman to work with Morgana or GlindaMartin Roth
Birman should work with either Morgana or Glinda SoCs, so configure the mainboard to allow building with either. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I56206cd9ad5db99c00b734430b250e04ea9e0609 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-10-28mb/google/skyrim/var/winterhold: Update touchscreen devicetree settingEricKY Cheng
Update touchscreen setting. ELAN900C is the I2C over hid device with slave address 0x10. MELF0410 is the pure I2C device with slave address 0x34. The LCD team verification result is on b/251378772 comment#11. BUG=b:251378772 TEST=Build/boot ChromeOS on winterhold, ensure touchscreen is functional. Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I568346d2abc39d9427e49c3b21f38db0184b8b44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2022-10-28mb/google/skyrim/var/winterhold: Enable DPTC supportEricKY Cheng
Enable DPTC support for Winterhold BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I97c2d3ee29687cd8a9c459e90a45cef05ac4436b Reviewed-on: https://review.coreboot.org/c/coreboot/+/68076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2022-10-28mb/getac/p470: Use 'enum cb_err'Elyes Haouas
Change-Id: I9650fc672a94343472b44037f8a664d7d15aaf15 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2022-10-28mb/getac/p470: Remove unused 'ec_oem_write()'Elyes Haouas
Change-Id: Ia955d8736f9b1835ad33ce43dfbbcd9b6a0a9db4 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2022-10-28mb/getac/p470: Remove unused 'send_ec_oem_data_nowait()'Elyes Haouas
Change-Id: If68629f22803ebd61cd00b76b9e61822178325f9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2022-10-28mb/google/skyrim/var/winterhold:Generate RAM IDs for new memory partsEricKY Cheng
Update H58G56BK7BX068 and H58G66BK7BX067 support BRANCH=None BUG=b:243337816 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I2aa6169c6e824318e738878f8cd19e76fcfd5713 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-10-28mb/google/brask/variants/moli: keep SAGV disableRaihow Shi
Since there is not too many low power requirement for moli and it is doing FSI firmware qual, so it is not critical to enable the SAGV and keep SAGV disable. BUG=b:254600066 TEST=emerge-brask coreboot Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I4115b35fed35b74a307b08f7a10ebced2309297f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68898 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-10-27mb/google/brya: Update Crota's ELAN touchscreen delay to 150 msPaz Zcharya
ELAN updated the datasheet of component 4599 (qualification 10511) to version 0.6 (upload date: Oct 24, 2022), decreasing i2c delay during power-on sequence from 300 ms to 150 ms. BUG=b:232893949 TEST=Manually checked touchscreen works after reboot and suspend (on kernel v5.10) Signed-off-by: Paz Zcharya <pazz@google.com> Change-Id: I17e1f7d419637f6dff4049484ce1836ad98017ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/68868 Reviewed-by: Eran Mitrani <mitrani@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-10-27mb/google/brya/var/lisbon: use i2c1 for TPM for lisbonKevin Chiu
This change sets DRIVER_TPM_I2C_BUS to the i2c 1 bus for TPM for the lisbon variant. BUG=b:246657849 TEST=FW_NAME=lisbon emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I16be50258db2111d22f7465458873e92f44c7dac Reviewed-on: https://review.coreboot.org/c/coreboot/+/68887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-10-27mb/google/brya: Update devicetree setting for lisbonKevin Chiu
update devicetree setting per the schematic BUG=b:246657849 TEST=emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I4268a5b43690a22bb703337fed84b83c45da4ad2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-10-27mb/google/brask/var/lisbon: Update gpio tableKevin Chiu
Based on latest schematic to update the gpio table. BUG=b:246657849 TEST=FW_NAME=lisbon emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I531f9ca9f6902d3318e99dadb58a811a4686a6e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-10-27mb/google/skyrim: Expand cbmem console bufferZheng Bao
Expand the size of cbmem console buffer from default value 0x20000 to 0x80000. Verified by running "cbmem -l" in Chromium OS shell. localhost ~ # cbmem -l CBMEM table of contents: NAME ID START LENGTH 0. FSP MEMORY 46535052 b97fe000 01000000 1. CONSOLE 434f4e53 b977e000 00080000 2. RW MCACHE 574d5346 b977d000 00000360 3. RO MCACHE 524d5346 b977c000 00000f20 4. FMAP 464d4150 b977b000 0000047c 5. TIME STAMP 54494d45 b977a000 00000910 6. VBOOT WORK 78007343 b9766000 00014000 7. RAMSTAGE 9a357a9e b9700000 00066000 8. ACPI BERT 42455254 b96fc000 00004000 9. CHROMEOS NVS 434e5653 b96fb000 00000f00 10. REFCODE 04efc0de b96ab000 00050000 11. MEM INFO 494d454d b96aa000 00000768 12. RAMOOPS 05430095 b95aa000 00100000 13. COREBOOT 43425442 b95a2000 00008000 14. ACPI 41435049 b957e000 00024000 15. TPM2 TCGLOG 54504d32 b956e000 00010000 16. SMBIOS 534d4254 b9566000 00008000 17. FSP RUNTIME 52505346 ba7febe0 00000004 18. POWER STATE 50535454 ba7feb80 00000060 19. ROMSTAGE 47545352 ba7feb60 00000004 20. EARLY DRAM USAGE 4544524d ba7feb40 00000008 21. ACPI GNVS 474e5653 ba7feb20 00000020 BUG=246268888 TEST=Skyrim Change-Id: I79205f31b4cc3276c1c213a171a6bf7e18d73a1c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-27mb/lenovo/haswell: Enable VBOOT_VBNV_FLASHYu-Ping Wu
To deprecate VBOOT_VBNV_CMOS [1], replace VBOOT_VBNV_CMOS with VBOOT_VBNV_FLASH for Haswell. Currently BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is selected for CPU_INTEL_HASWELL (see [2]). However, there seems to be no particular reason on those platforms. Flashconsole works on Broadwell, at least, and it writes to flash as early as bootblock. Therefore, remove BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES, so that VBOOT_VBNV_FLASH can be enabled. [1] https://issuetracker.google.com/issues/235293589 [2] commit 6c2568f4f58b9a1b209c9af36d7f980fde784f08 (CB:45740) drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config BUG=b:235293589 TEST=./util/abuild/abuild -t LENOVO_THINKPAD_T440P -a (with VBOOT) Change-Id: If1430ffd6115a0bc151cbe0632cda7fc5f6c26a6 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-10-27mb/siemens/mc_apl2: Enable early POST through NC_FPGAJan Samek
Enable early POST code output for this mainboard, using the NC FPGA device on PCIe. This requires the parent PCI bridge to be initialized early. BUG=none TEST=boot on siemens/mc_apl2 and observe whether the POST codes coming from before FSP-M init are visible Change-Id: Ice5fe26e11d0513e6bb0a20f1d8f0483d7b3dc6a Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-10-27mb/google/brya/gaelin: Change DDR4 from interleave to non-interleaveRaymond Chung
The brask DDR4 is set to interleave, due to the limited number of gaelin PCB layers and the traces need to be smooth, we will use non-interleave for gaelin DDR4. BUG=b:255399229, b:249000573 BRANCH=firmware-brya-14505.B TEST=Build "emerge-brask coreboot" and pass MRC memory training Change-Id: I34413343e3f7c283f49fbbdd277d9da39c09f9f8 Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-10-26mb/google/guybrush,skyrim,zork: rework FCH IRQ mapping table generationFelix Held
This ports the changes to the way the fch_pic_routing and fch_apic_routing arrays get populated from Mandolin to Guybrush, Skyrim and Zork. This is a preparation to move the init_tables implementation to the common AMD SoC code in a later patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie550238dfa0d4c7cebe849966d40fa0b1984a0f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-26mb/amd/bilby,birman,chausie,majolica: rework FCH IRQ mapping generationFelix Held
This ports the changes to the way the fch_pic_routing and fch_apic_routing arrays get populated from Mandolin to Bilby, Birman, Chausie and Majolica. This is a preparation to move the init_tables implementation to the common AMD SoC code in a later patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia957056b60dafbc52a9809a4563a348ad7443376 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-26mb/amd/mandolin: handle invalid intr_index values in init_tablesFelix Held
Make sure that the intr_index is valid to avoid out-of-bounds writes to the fch_pic_routing and fch_apic_routing arrays. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I45ab115f3814b212243c4f6cf706daf77b6ff3b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-26mb/amd/mandolin: introduce mb_get_fch_irq_mappingFelix Held
Introduce mb_get_fch_irq_mapping to access the FCH IRQ routing mapping information and use it in init_tables to get the mapping instead of directly accessing the array's contents. This is a preparation to move the init_tables implementation to the common AMD SoC code in a later patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9c39ea9de5ebbf70d2c5a87bfdfe270796548c5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-26mb/amd,google: unify fch_irq_routing struct instance nameFelix Held
Use the same fch_irq_map name in all mainboards using the Picasso, Cezanne, Mendocino and Morgana instead of using a mainboard-specific name. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I035cffb9c6c8afd6bd115831e8eed4a395e2a7fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/68846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-26mb/google/guybrush,skyrim: add missing string.h includeFelix Held
string.h defines the memset function. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I286557d6ad83990bc101eaa930bde04345859c0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/68845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-26mb/amd/bilby,mandolin: add missing string.h includeFelix Held
string.h defines the memset function. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I242a0382e7020681b6c3a25f75a2a91cbccbe815 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-26soc/amd/mendocino: Enable GPP clk req disabling for disabled devicesRobert Zieba
Enable GPP clk req disabling for disabled PCIe devices. If a clk req line is enabled for a PCIe device that is not actually present and enabled then the L1SS could get confused and cause issues with suspending the SoC. BUG=b:250009974 TEST=Ran on skyrim proto device, verified that clk reqs are set appropriately Change-Id: I6c840f2fa3f9358f58c0386134d23511ff880248 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68139 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-26soc/amd/common/include: introduce and use FCH_IRQ_ROUTING_ENTRIESFelix Held
Instead of using magic constants for the fch_pic_routing and fch_apic_routing array sizes, define FCH_IRQ_ROUTING_ENTRIES in the common code headers and use this definition. This also allows to drop the static assert for the array sizes. In the Stoneyridge mainboard code the equivalent arrays are named mainboard_picr_data and mainboard_intr_data; also use FCH_IRQ_ROUTING_ENTRIES as fixed array size there. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2d7ee46bd013ce413189398a144e46ceac0c2a10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68818 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26mb/amd,google: move fch_irq_routing struct definition to soc/amdFelix Held
Define the fch_irq_routing struct once in a common header file instead of in every mainboard's code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I11d9000b6ed7529e4afd7f6e8a7332c390da6dab Reviewed-on: https://review.coreboot.org/c/coreboot/+/68817 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26mb/google/skyrim: Enable CBFS VerificationKarthikeyan Ramasubramanian
Enable RO verification by GSC and CBFS verification. BUG=b:227809919 TEST=Build and boot to OS in Skyrim with CBFS verification enabled using x86 verstage and PSP verstage. Change-Id: Idd22a521a913705af0d2aca17acd1aa069a77f29 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-26coreboot_tables: Drop uart PCI addrArthur Heymans
Only edk2 used this to fill in a different struct but even there the entries go unused, so removing this struct element from coreboot has no side effects. Change-Id: Iadd2678c4e01d30471eac43017392d256adda341 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-26mb/google/brya/var/kano: select SOC_INTEL_RAPTORLAKEDavid Wu
Select SOC_INTEL_RAPTORLAKE to force coreboot to use the RPL FSP headers for FSP as kano is using a converged firmware image. BUG=b:253337338 BRANCH=firmware-brya-14505.B TEST=Cherry-pick Cq-Depends, then "FW_NAME=kano emerge-brya coreboot-private-files-baseboard-brya coreboot chromeos-bootimage", disable hardware write protect and software write protect, flash and boot kano in end-of-manufacturing mode to kernel. Cq-Depend: chrome-internal:5046060, chromium:3967356 Change-Id: I75da3af530e0eafdc684f19ea0f6674f6dc10f01 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-10-26mb/prodrive/atlas: Disable S3Maximilian Brune
The Atlas board has currently the problem that suspending the System causes the System to freeze. Therefore disable S3, until the cause is figured out and fixed. Change-Id: I5b28787df9b01683fcd4a1de8267840a80bb4fe6 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68591 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26mb/google/rex: Move `DRIVERS_INTEL_USB4_RETIMER` configSubrata Banik
This patch moves DRIVERS_INTEL_USB4_RETIMER config from Meteor Lake SoC to Rex mainboard to maintain the symmetry with previous generation ChromeOS devices (Brya and Volteer). BUG=none TEST=Able to build and boot to Google/Rex with USB4 functionality remaining intact. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I38360f6f1f2fcb4b0315de93c68f00d77e63003c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-10-25mb/google/skyrim/var/frostflow: Update devicetree settingFrank Wu
Update devicetree based on the schematic_20221014. BUG=b:253506651, b:251367588 BRANCH=None TEST=FW_NAME=frostflow emerge-skyrim coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Ia03962b0e01394ddcd4971cbe0172ef5bd913e15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68482 Reviewed-by: Chao Gui <chaogui@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
2022-10-25mb/google/kahlee/liara/devicetree: move Raydium touchscreen to baseboardFelix Held
Move the Raydium touchscreen to the baseboard devicetree. Since only the liara variant uses a level IRQ as I2C devices are supposed to, all other board variants still override this to use an edge IRQ which were added as a workaround to make the touchscreen work on the other devices. Right now it's unclear to me if that edge IRQ workaround was only needed temporarily and can now be removed, so I'll keep it as it was for now. If this turns out to be no longer needed on the other variants, the overrides can be dropped in the future. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic621c1a5856e9e280a25b0668010a1ee5bbb61e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68770 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-10-25mb/siemens/mc_ehl1: Disable L1 prefetcherWerner Zeh
The highly real time driven application executed on mc_ehl1 has shown that the L1 prefetcher on Elkhart Lake is too aggressive which in the end leads to an increased number of cache misses. Disabling the L1 prefetcher boosts up the performance (in some cases by more than 10 %) in this specific use case. Change-Id: Id09a7f8f812707cd05bd5e3b530e5c3ad8067b16 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68668 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2022-10-25mb/google/geralt: Configure firmware display for eDP panelBo-Chen Chen
Add eDP panel power-on sequences and initialize the display in the ramstage. eDP panel in MT8188 EVB: "IVO R140NWF5 RH". Panel spec name: R140NWF5 RH Product Specification Firmware display eDP panel logs: configure_display: Starting display initialization SINK DPCD version: 0x11 SINK SUPPORT SSC! Extracted contents: header: 00 ff ff ff ff ff ff 00 serial number: 26 cf 7d 05 00 00 00 00 00 1e version: 01 04 basic params: 95 1f 11 78 0a chroma info: 76 90 94 55 54 90 27 21 50 54 established: 00 00 00 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a extensions: 00 checksum: fb Manufacturer: IVO Model 57d Serial Number 0 Made week 0 of 2020 EDID version: 1.4 BUG=b:244208960 TEST=see firmware display using eDP panel in MT8188 EVB. Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I67e0699c976c6f85e69d40d77154420c983b715e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68490 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-10-24mb/clevo/tgl-u: Avoid indirect includesElyes Haouas
Change-Id: I51ab987420e592ac2f841c2d7761c0adcc43124e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-10-24mb/google/kahlee: always detect ELAN touchpadFelix Held
Always detecting the presence of the ELAN touchpad doesn't affect the functionality, but allows dropping the override for all variants that have multiple touchpad options. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id5d14eedd5d95dd0990ae56775daed9284c03717 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-10-24mb/google/kahlee: use override devicetrees for variantsFelix Held
This helps with deduplicating the identical parts of the variants' devicetrees. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie050c4624327b904e8cb0959b40421339e43f825 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-10-24mb/Kconfig: Add a prompt string for MAINBOARD_PART_NUMBERSam McNally
For some nissa variants, there are build configurations that need to use different blobs, but otherwise are identical. Currently, they use the same choice of board config and configure blob paths appropriately. This avoids duplication within the Kconfig file, but the resulting firmware images can be difficult to distinguish, since they report the same FRID. Add a prompt string for MAINBOARD_PART_NUMBER so it can be overridden and round-tripped through make oldconfig, allowing customisation of the reported FRID and other MAINBOARD_PART_NUMBER-derived values with minimal overhead. BUG=b:253966060 BRANCH=None TEST=CL:3960290 MAINBOARD_PART_NUMBER configs apply successfully Signed-off-by: Sam McNally <sammc@chromium.org> Change-Id: I3497d7fa1c04c8fa2592025c771d9dbc65632e6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-10-22mb/google/brask/var/kuldax: Revise PsysPL2 to 150W for Pentium CPUDavid Wu
Pentium CPU will use 150W adaptor, this change revises PsysPL2 to 150W based on fw_config. BUG=b:253542746 TEST=Check CPU PsysPL2=150W in AP log with Pentium CPU. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I63b2a9d79454b20b60ba1317a8eebb3c10eff9d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-10-22mb/google/brya: Enable SaGv for brask variantsDerek Huang
SaGv is enabled for all brya variants, so it should be harmless to enable it for brask variants to save some power. BUG=254374912 TEST=Build and boot to Chrome OS Signed-off-by: Derek Huang <derekhuang@google.com> Change-Id: Ib5d1e39b3f901606e2f1449e4ed40d53696562ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/68646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-10-22mb/google/skyrim/var/baseboard: Update gpio setting for touchscreen IRQFrank Wu
The touchscreen IRQ has been configured as LEVEL_LOW in skyrim projects. Therefore, update the gpio.c to be consistent with the configuration. BUG=b:253506651, b:251367588 BRANCH=None TEST=FW_NAME=frostflow emerge-skyrim coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Iccfe5b01f10899c43151762e4730a05990afa602 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chao Gui <chaogui@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-10-22mb/siemens/mc_ehl: Add FIVR config to devicetree for all variantsWerner Zeh
Add a config for FIVR in devicetree for both, mc_ehl1 and mc_ehl2 variants in order to provide the real delay value for the VCC supply rail. This delay is needed to enable proper switching between different VCC levels based on current system state. Change-Id: Ibccb8ea1b42ccd2ff0a37cbd9651528a2a55ebd6 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-22mb/siemens/mc_apl*: Enable early PCI bridge before FSP-MAngel Pons
Apollo Lake seems to start with PCIe root ports unusable/uninitialized before FspMemoryInit() is called and FSP-M properly initializes these root ports. However, we need the root ports accessible before FspMemoryInit() in certain cases, such as emitting POST codes through a PCIe device. For the initialization to happen properly, certain register writes specified in Apollo Lake IAFW BIOS spec, vol. 2 (#559811), chapter 3.3.1 have to be done. BUG=none TEST=Boot on siemens/mc_apl2 with NC_FPGA_POST_CODE enabled and check that the POST codes are emitted before FspMemoryInit(). Change-Id: If782bfdd5f499dd47c085a0a16b4b15832bc040e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68223 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-22mb/google/nissa: Disable SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRYReka Norman
On nissa, the pre-x86 time is not part of the 1s firmware boot time target. Including the pre-x86 timestamps causes confusion since the boot time appears to be greater than 1s, so disable the Kconfig on nissa. We're not doing any analysis or optimisation of the pre-x86 time on nissa anyway, this work will start from MTL onwards. Also, the Kconfig is already disabled on the brya firmware branch, so this will result in the same behaviour as brya. Before: Total Time: 1,205,840 After: Total Time: 995,300 BUG=b:239769532 TEST=Boot nivviks, check "1st timestamp" is the first timestamp. Change-Id: I885071c9e0ff9c8fac9444b382567d38a19c3c15 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68553 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-22mb/lenovo/*/mainboard.c: Clean up includesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I406f21c0c05e6af357e45e718422be94c6fd5408 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-10-22mb/google/kahlee: Fix audio ACPI inclusionMatt DeVillier
Not all kahlee variants use the RT5682 audio codec, so split the baseboard audio ACPI into two parts and only include the asl for the codec(s) actually needed for a given variant. TEST=build/boot aleena, liara variants and verify no ACPI present for RT5682 codec (which is not present on the boards). Change-Id: Icb7df4f8e51495ad3cb40113cd00810fd27dcd00 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-21mb/google/skyrim: Enable genesyslogic gl9755 for frostflowFrank Wu
Enable DRIVERS_GENESYSLOGIC_GL9755 support for frostflow BUG=b:253506651, b:251367588 BRANCH=None TEST=FW_NAME=frostflow emerge-skyrim coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I1db598c68687ed17fd9baa3567ab8fdd3e4fb6a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-10-21mb/gigabyte/ga-h61m-series: Add GA-H61M-DS2Angel Pons
Built from a mixture of autoport output, other variants, schematics and expert guesswork. I don't have this board, but the code has been tested by someone else and boots successfully (first try) with TianoCore. It's reasonable to assume most things work, as this board is very similar to the already-supported variants. Change-Id: I3d8df483e5573f77782b7d18b1410b391bfe387d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61541 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21mb/lenovo/t{410,60}/dock.h: Fix header guardsElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I7b279cf2c69f62b47ef497edd372034f148fff03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-21mb/google/corsola: Initialize MT6315 for MT8186TSen Chu
Initialize MT6315 for powering on big cores on MT8186T. BUG=b:249436110 TEST=build pass. BRANCH=corsola Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com> Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ib1d71d4f1689ba1e7ea5f798503ef11eff423fff Reviewed-on: https://review.coreboot.org/c/coreboot/+/68621 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21mb/lenovo/s230u/mainboard.c: Replace comma with semicolonElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I9e8ad533e939553a93e76f1dbb37fc98b53f06d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-21mb/google/skyrim/port_descriptors: update DDI for MDN and ChausieJason Nien
Add two new types for MDN DDI descriptor BUG=b:228284940 TEST=Normal boot and S0i3 cycles Signed-off-by: Jason Nien <finaljason@gmail.com> Change-Id: I02793f032f9855dac202a5aca8666c26426d6cb2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66847 Reviewed-by: Bao Zheng <fishbaozi@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2022-10-20mb/google/brya: Create gladios ADL variantKevin Chiu
Create the gladios variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:239513596 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_gladios Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I3dc99d97d8e30d9641f56616222dd68e3a0d548d Reviewed-on: https://review.coreboot.org/c/coreboot/+/68569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-20mb/google/(guybrush|skyrim): Use a variable for APCB filenameMartin Roth
We use the name of the APCB file repeatedly, so put it into a variable so that it's easier to update. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I8684db2f7b2d68f0354e37bd8cdfc4f9cab44b8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/67501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-20mb/google/rex: Skip sending the MBP HOB to save boot timeWonkyu Kim
This change is to skip sending the MBP HOB since coreboot doesn't use it and also helps to reduce the boot time by ~40 ms. Boot time data Before: * 955:returning from FspSiliconInit 1,656,985 (274,416) After: * 955:returning from FspSiliconInit 1,593,036 (233,286) BUG=b:252410202 TEST=Verified that boot time is reduced by ~40 msec. Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I0d4f66940529b8d38d9658c769feba8b5c9b715e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68418 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-10-20mb/google/herobrine: Remove NVMe from device treeShelley Chen
We need to boot eMMC for modem calibration, there is not need for BIOS to initialize NVMe anymore as the kernel will do so. Removing the pci device from the device tree as a first step. BUG=b:185426670, b:254281839 BRANCH=None TEST=Boot after removing from the herobrine device tree. Change-Id: I802dd1361bc56a24ab3d65e6782bc611b7b75ee3 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-10-20mb/google/skyrim/var/frostflow: Update GPIO settingsFrank Wu
Configure GPIOs based on GPIO_20221014.xlsx of frostflow. BUG=b:253506651, b:251367588 BRANCH=None TEST=FW_NAME=frostflow emerge-skyrim coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I02272801c85a7c30d24c834a840e026225956fb8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-10-20mb/google/skyrim/var/frostflow: Generate RAM IDs for new memory partsFrank Wu
Add new memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) H9JCNNNBK3MLYR-N6E 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) H9JCNNNCP3MLYR-N6E 1 (0001) MT62F2G32D8DR-031 WT:B 2 (0010) H9JCNNNFA5MLYR-N6E 3 (0011) BUG=b:250470704, b:247683159 BRANCH=None TEST=FW_NAME=frostflow emerge-skyrim coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I34584092c938539c91d65501ebe34b00212b34d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-10-20mb/google/nissa/var/craask: Remove redundant ELAN TouchscreenTyler Wang
Remove redundant touchscreen "ELAN6915". BUG=b:254328657 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I8f90b071b053858cf720de5ac2a71031fe623d70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-20mb/google/nissa/var/craask: Remove SAR Proximity SensorVictor Ding
Craask does not have a SAR proximity sensor. BUG=b:253387689 TEST=Dump ACPI SSDT and verify SX9324 related entries are not present. Change-Id: Ia0e3eb6dba82594ca27040d6ab0197da6095f510 Signed-off-by: Victor Ding <victording@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68564 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-20mb/google/drallion/hda_verb: add verbs for GPU HDMI audioMatt DeVillier
Test: cbmem reports verb table loaded for codec #2 Change-Id: I4db044535c95ccd3e81a67bb5e58e6f04ee8d12f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-20mb/google/drallion: Add default FMAP for non-ChromeOS buildsMatt DeVillier
Test: build/boot google/drallion with non-ChromeOS build, Tianocore payload. Windows 10, Linux 5.10.x booted successfully Change-Id: I6358b1d5c71eee065fed96b7bca31e37f30d3a8f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58405 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-20purism/librem_cnl: Add Kconfig to enable Mini UARTJonathon Hall
Librem Mini has a UART (accessible with soldering), which is very useful for work on coreboot. It can be used for coreboot/SeaBIOS/Linux boot logs, or as a general purpose UART. Change-Id: I38ad5f19da6af5ed286ad3583f34b824a3660916 Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68551 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-20mb/prodrive/hermes: Allow using the Intel iGPU as primaryArthur Heymans
Configure the Intel iGPU as primary video adapter if enabled according to EEPROM settings. The default is to use the ASPEED BMC as primary video adapter, which only has a VGA output and the remote KVM output. For now, use the FSP GOP driver to light up the iGPU. There are several issues with libgfxinit on the Hermes, probably due to the unusual setup of the iGPU's display outputs. They are routed to a mezzanine connector for a piggy-back sub-board, of which there are two models. The Poseidon piggy-back has two DisplayPort outputs and an HDMI output coming from a MegaChips LSPCON. The Avalanche piggy-back routes all three DisplayPort outputs from the iGPU into a FPGA, which acts as a DisplayPort sink. Note that the FSP GOP only initializes at most 2 iGPU display outputs. However, all three outputs function properly once OS (Windows, Linux) graphics drivers take over. Additionally, update the config file that Prodrive uses to build coreboot images so that the iGPU can be used as primary. TEST=Verify that the iGPU's outputs work properly in pre-OS, Windows and Linux, on both the Poseidon and Avalanche piggy-backs. Change-Id: I24d9ebc2055dc246e7f257aa2f3853b22c8af370 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62649 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-20mb/google/reef: Demote NHLT log messages from error to infoMatt DeVillier
Change-Id: I1c00322d2b22e1fafffd6ebd66f2df14bcedbd89 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68461 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-20mb/google/volteer: add VBTs for lindar variantMatt DeVillier
Add VBT data files, ensure secondary VBTs compiled in as needed, select INTEL_GMA_HAVE_VBT. TEST=build/boot lindar variant with FSP/GOP display init, edk2 payload Change-Id: I81022670fabda7994e292d333c999b508e61b469 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-20mb/google/dedede: add VBTs for drawcia, mangolor variantsMatt DeVillier
Add VBT data files, ensure secondary VBTs compiled in as needed, select INTEL_GMA_HAVE_VBT. TEST=build/boot drawcia, mangolor variants with FSP/GOP display init and edk2 payload Change-Id: I58a2ed59bd858ce772e92f6659d341036823b11a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-20mb/google/nissa/var/nivviks: Change ISH name to adl_ish_lite.binReka Norman
The ISH build target used for nissa is called adl_ish_lite: CL:3925007, and by default the binary is installed as /lib/firmware/intel/adl_ish_lite.bin We could change the installed name, but it's nicer to keep it consistent with the build target, so change the name in coreboot instead. BUG=b:234776154 TEST=Build and boot nirwen, check firmware name is updated in SSDT Change-Id: I983a38d08e758cf5a12a3f91a601c7e57d42c0cb Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-10-19mb/google/brask/var/kuldax: Set PL and PsysPLDavid Wu
1. Set the PL1, PL2 and PL4. 2. Set PsysPL2 and PsysPmax. BUG=b:253380352 b:253542746 TEST=Compare the measured power from adapter with the value of 'psys' from the command 'dump_intel_rapl_consumption'. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I0a7ff64689b39e7754e0aed2f6869881a682fc93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68437 Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Maulik Vaghela <maulikvaghela@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-10-18mb/google/dedede/var/storo: Disable PCIE RP8 and CLKSRC4Zanxi Chen
This change disables unused PCIE RP8 and CLKSRC4. Without this change storo cannot enter into s0ix properly. BUG=b:219376808 TEST=Built and verified in storo Change-Id: I9867825ce53de72ef73920c153002bc3be4dbd2d Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com> Reviewed-by: Jamie Chen <jamie.chen@intel.corp-partner.google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Maulik Vaghela <maulikvaghela@google.com> Reviewed-by: Aamir Bohra <aamirbohra@google.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-23 07:29:47 +0000