diff options
| author | Werner Zeh <werner.zeh@siemens.com> | 2022-10-20 15:49:21 +0200 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-10-22 16:42:22 +0000 |
| commit | 6537216b7a4705409ef3eee75bc685bf70ec30a3 (patch) | |
| tree | 3762d809740471dc1521d9cce70009b86f36a5eb /src/mainboard | |
| parent | 516eff01e61155a681a4f684515ae7924b9bff0d (diff) | |
mb/siemens/mc_ehl: Add FIVR config to devicetree for all variants
Add a config for FIVR in devicetree for both, mc_ehl1 and mc_ehl2
variants in order to provide the real delay value for the VCC supply
rail. This delay is needed to enable proper switching between different
VCC levels based on current system state.
Change-Id: Ibccb8ea1b42ccd2ff0a37cbd9651528a2a55ebd6
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb | 6 | ||||
| -rw-r--r-- | src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb | 6 |
2 files changed, 12 insertions, 0 deletions
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index 69277a5b10..bc3c4a0e06 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -126,6 +126,12 @@ chip soc/intel/elkhartlake register "PchTsnGbeLinkSpeed" = "Tsn_2_5_Gbps" register "PchTsnGbeSgmiiEnable" = "1" + # FIVR related settings + register "fivr" = "{ + .fivr_config_en = true, + .vcc_low_high_us = 50, + }" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index ecf5d55558..4109ec9157 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -117,6 +117,12 @@ chip soc/intel/elkhartlake }, }" + # FIVR related settings + register "fivr" = "{ + .fivr_config_en = true, + .vcc_low_high_us = 50, + }" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device |