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2024-03-28cpu/x86: Link page tables in stage if possibleArthur Heymans
When switching back and forth between 32 to 64 bit mode, for example to call a 32-bits FSP or to call the payload, new page tables in the respective stage will be linked. The advantages of this approach are: - No need to determine a good place for page tables in CBFS that does not overlap. - Works with non memory mapped flash (however all coreboot targets currently do support this) - If later stages can use their own page tables which fits better with the vboot RO/RW flow A disadvantage is that it increases the stage size. This could be improved upon by using 1G pages and generating the pages at runtime. Note: qemu cannot have the page tables in the RO boot medium and needs to relocate them at runtime. This is why keeping the existing code with page tables in CBFS is done for now. TEST: Booted to payload on google/vilbox and qemu/q35 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ied54b66b930187cba5fbc578a81ed5859a616562 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80337 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-27mb/google/nissa/var/anraggar: Modify the GPP_F15 of pen to EDGE_BOTHQinghong Zeng
Currently, simply changing the wake event configuration to ANY does not completely resolve the issue of inserting a pen not waking the system. The pen actually needs to wake up the system both when plugged in and when pulled out. This is because in the pen's GPP_F15 configuration, the original attribute is EDGE_SINGLE, which should be changed to EDGE_BOTH. BUG=b:328351027 TEST=insert and remove pen can wakes system up. Change-Id: I1823afd0bcb86804227117d2d5def38788bc7387 Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81441 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-27mb/google/brya: Create yavista varianthsueh.rasheed
Create the yavista variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:321583226 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_YAVISTA. Change-Id: I6fa464a4dcd9551a42e8746e64c724b3582dbe02 Signed-off-by: Hsueh Rasheed <hsueh.rasheed@inventec.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80342 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-27mb/purism: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: I2285d1bdaa2734658ca1a0cc58ef2294d90d333e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
2024-03-27mb/google/brox: Fix GPE_EC_WAKE configurationKarthikeyan Ramasubramanian
Wake signal from EC is routed to GPP_D1 and hence GPE_EC_WAKE corresponds to GPE0_DW1_01. Fix GPE_EC_WAKE configuration. BUG=b:329026602 TEST=Build Brox BIOS image and boot to OS. Trigger suspend and wake up using EC generated events like AC connect/disconnect. Change-Id: Ifb89bd0de7b7fc316792e801ed5a1d3f25ca5b1c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
2024-03-26mb/msi: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: I4a678b433e3e1a492e2a8e679caf75f4741317cb Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81485 Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-26mb/google/butterfly: Fix compiling for 64bit modeArthur Heymans
Change-Id: Ieaaba5b36796d97449896b8475744a21f01e93d1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-03-26mb/razer: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: I2c8cc390bed3aef901d6ada19361c35928dfdb0c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81496 Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-26mb/roda: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: Id039ad885d2f08bc3fe09aca740a72a5820f7fcc Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
2024-03-26mb/lenovo: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: I6ece868184dd772fc2c3c472ae2172d1c34fb179 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81484 Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-26mb/fb/fbg1701: Move VBOOT key locationArthur Heymans
Move it downwards allows for a larger bootblock, which comes in handy if romstage or page tables are linked inside the bootblock. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ib37846c0b039d89396839ffa6047b18bcc228e02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80347 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-24mb/google/veyron_{mickey,rialto}: Remove return statement in void functionElyes Haouas
Return statement is not useful in void function. Change-Id: I8cf020de335e4da933b7bbdc27b7ac6f31afe885 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81430 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-23src: Add missing SPDX license headersNicholas Chin
Other files in the commits that added these files were licensed under GPL-2.0-only, and the project as a whole is GPL-2.0-only, so use that as the license. Change-Id: I6c1a7ba582f61f98069ebf3857a8b5bdc8588c3e Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81421 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-22vc/amd/opensil/genoa_poc/mpio: move PCIe port function below mpio chipFelix Held
Move the gpp_bridge_* device functions that are bridges to the external PCIe ports below the corresponding mpio chip. This avoids the need for dummy devices and does things in a slightly more coreboot-native way. TEST=PCIe lane config reported by openSIL is identical Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Varshit Pandya <pandyavarshit@gmail.com> Change-Id: I7e39bf68d30d7d00b16f943953e8207d6fe9ef41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81340 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-22mb/starlabs/starbook: Correct alphabetisation of Kconfig optionsSean Rhodes
Change-Id: I7626fe9d4740e9f141a674fa457b0714fc38ed91 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-22mb/starlabs/starbook/adl: Set RP9 detection timeout to 50msSean Rhodes
Certain SSDs are not detected in the default time window, so change this to 50ms to allow these SSDs to be detected. Change-Id: I60e66096ef9ea0146a1bc72c5c74234353509439 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81398 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-22mb/starlabs/starbook/adl: Disable the Clock Request 4 GPIOSean Rhodes
The CPU port is not used so disable it. Change-Id: Ia150f99c4679323f08e44b0885af04113dfabd87 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-22mb/starlabs/starbook/{adl,rpl}: Correct the ClkReq GPIO commentsSean Rhodes
Change-Id: I8dc80c5bdde61f3c2dc5c9dc67fbc752de7a103f Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-22Revert "mb/starlabs/starbook/{adl,rpl}: Disable GpioOverride"Sean Rhodes
This reverts commit 8902dfa2bdf33b8ae69fa0d5161b28f67f8c0881. This was originally assumed to be an FSP/Descriptor/PMC mismatch but it turns out that the problem was coreboot incorrectly detecting ASPM support on devices. Revert so that a proper fix can be applied. Change-Id: I3f83e79c1b21a6c3799abed4a279b8bd59ac3570 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81395 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-22mb/starlabs/starbook/adl: Correct the layoutSean Rhodes
Adjust the size of the ME partition to match the descriptor Change-Id: Ibdec5121518452ec16cebcc4f2fb563355373be3 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81394 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-22mb/starlabs/starbook/{adl,rpl}: Disable CNViSean Rhodes
No variants were ever built with CNVi cards, so disable this device. Change-Id: I3725465eae0c7ade3dafa03add151353818ee761 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-22mb/lenovo/s230u: Fix compiling for 64bit modeArthur Heymans
This fixes the warning when an integer is cast to a pointer of a different size. Change-Id: Ide2827ec1b86dcbd804be9f3269c6c968cb4257b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-03-22mb/google/nissa/var/anraggar: Update touchscreen enable pin to GPP_C0Qinghong Zeng
Assign GPP_C0 and enable only the touchscreen. Before modification, GPP_C0 supplies power to the touchscreen and sensor at the same time. Now the hardware circuit has been modified, GPP_C0 supplies power to the touchscreen alone. After the software is synchronously modified, when the device enters suspend(S0ix), GPP_C0 will not enable VDD, which can reduce the standby power consumption of the touchscreen when it is suspended(S0ix), which is about 2.1mW. BUG=b:304920262 TEST= touchscreen function workable Change-Id: Ia06209aa8303be4fc0669c5d6e5d7a06e8e9ab99 Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81265 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
2024-03-21mb/google/brox: Configure I2C timing for I2C devicesIvy Jian
Configure I2C0/1 timing in devicetree to meet timing requirement. (THIGH(us) minimum is 0.6us). Before: I2C0 : THIGH(us) 0.595us I2C1 : THIGH(us) 0.582us After: I2C0 : THIGH(us) 0.673us I2C1 : THIGH(us) 0.666us Change-Id: I79af4fde4eb08d4eb896794756a633701bebb755 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81348 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-03-21mb/google/zork: Update APCB to increase UMA size to 128MBMatt DeVillier
The previous value of 32MB was set to meet Google's ChromeOS reqs, but hampers real-world performance in Linux/Windows, so increase it to 128MB to match the "auto" default for the Picasso UEFI firmware. TEST=build/boot Windows on google/zork (morphius), verify UMA set to 128MB. Change-Id: I8c6487a4cb8155f826d20fd3ceca87859829199c Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81364 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
2024-03-21mb/google/brya: Create a tivviks variantSowmya V
This patch creates a new tivviks variant, which is a Twinlake platform. This variant uses Nivviks board mounted with the Twinlake SOC and hence the plan is to reuse the existing nivviks code. BUG=b:327550938 TEST= Genearte the Tivviks firmware builds and verify with boot check. Change-Id: Ia833a1dad45e13cd271506ade364b116c5880982 Signed-off-by: Sowmya V <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81262 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-20mb/google/brox: support ISHLi Feng
Set FW_CONFIG bit 21 to enable ISH PCI device and define ISH main firmware name so ISH shim loader can load firmware from file system. ISH also need to be enabled if STORAGE_UFS is set. BUG=b:280329972 TEST= Set bit CBI FW_CONFIG bit 21 Boot Brox board, check that ISH is enabled and loaded lspci shows: 00:12.0 Serial controller: Intel Corporation Alder Lake-P Integrated Sensor Hub (rev 01). Change-Id: Iadc5108c62737d27642a6948c00b5c122541aaba Signed-off-by: Li Feng <li1.feng@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80773 Reviewed-by: Tanu Malhotra <tanu.malhotra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Yuval Peress <peress@google.com>
2024-03-20vc/amd/opensil/genoa_poc/mpio: add IFTYPE_ prefix to mpio_type valuesFelix Held
Add an IFTYPE_ prefix to all elements of the mpio_type enum to have more specific names. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I229a3402c36941ee5347e3704fcf8d8a1bbc78a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81338 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-19mb/google/brox: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFSAshish Kumar Mishra
Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS in brox Kconfig. This enables a single binary for both SKU1 and SKU2. For SKU2, upon boot from cold reset, it will disable the UFS Controller and then trigger a warm boot. BUG=b:329209576 BRANCH=None TEST=Boot image on SKU1/SKU2 and check S0ix working. Change-Id: Iabd0b3a83aa386e09310b671632368807a4018d4 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shelley Chen <shchen@google.com>
2024-03-19mb/google/nissa/var/craaskov: Update eMMC DLL settingsIan Feng
Update eMMC DLL settings based on Craaskov board. BUG=b:318323026 TEST=executed 2500 cycles of cold boot successfully on all eMMC sku Change-Id: I56f8329c28261c2bcae9d058da929be6763b293c Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Simon Yang <simon1.yang@intel.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-19mb/google/nissa/var/glassway: Tune I2C timings for 400 kHzFrank Chu
Update touchpad and touchscreen I2C timing. - Data hold time: 300ns - 900ns BUG=b:328724191 BRANCH=firmware-nissa-15217.B TEST=Check wave form and met the spec. I2C1 (touchscreen) Hold time from 83.58ns to 413.87ns I2C5 (touchpad) Hold time from 95.93ns to 425.27ns Change-Id: I65fb1298f9e96ab0b63aba436f6a319f21b38925 Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Shawn Ku <shawnku@google.com>
2024-03-19mb/google/nissa/var/glassway: Adjust touchscreen power sequencingFrank Chu
Adjust touchscreen power sequencing for eKTH5015M. The INX touch panel (eKTH5015M) contains a pull-up register which causes TCHSCR_REPORT_EN pull-up abnormally from Z1 power on.Because the t25 must be at least greater than 20ms, TCHSCR_REPORT_EN is initialized to GPO_L in the early stage (romstage) to meet the spec. BUG=b:328170008 BRANCH=firmware-nissa-15217.B TEST=Build and check I2C devices timing meet spec. [INFO ] input: Elan Touchscreen as /devices/pci0000:00/0000:00:15.1/i2c_designware.1/i2c-10/i2c-ELAN0001:00/input/in4 Change-Id: I50f9c21ddee2bc9c1d313f63049cb587b4ae047a Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81135 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-19soc/intel/xeon_sp/spr: Enable 512 MMCONF buses by defaultPatrick Rudolph
As of now coreboot only supported one PCI segment group and thus the MMCONF size had to be limited to 256 buses on ibm/sbp1. Since the default FSP doesn't allow to disable unused IIO stacks a patched version had to be used. Those unused IIO stacks consume lots of PCI bus ranges, leaving no free buses for the secondary side behind PCI bridges. The IIO disable mechanism doesn't work after ACPI G3 exit and thus requires multiple reboots when the previous state was G3. Since coreboot now supports multi PCI segment groups enable 512 MMCONF buses on 4S platforms by default and drop the IIO stack disable UPDs on ibm/sbp1. This allows to boot faster without the need for a patched FSP. The use of multiple PCI segment groups might prevent legacy software from working properly, however the only board where multiple PCI segment groups are used uses u-root as default payload. TEST=Booted on ibm/sbp1 to ubuntu22.04 using two PCI segment groups. TEST=intel/archercity CRB Change-Id: I4e6e5eca1196d4ab50e43b4b58d24eca444ab519 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-17mb/google/nissa/var/anraggar: Add pen insert/remove for wakeupJianeng Ceng
Currently, inserting the pen does not wake the system, only removing the pen does. This is caused by the wake event configuration being DEASSERTED, so change it to ANY. BUG=b:328351027 TEST=insert and remove pen can wakes system up. Change-Id: Icdea995c2be04ea459e985f79269e49faf88248d Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
2024-03-17mb/google/brya: Create bujia variantShon Wang
Create the bujia variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:327549688 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_BUJIA Change-Id: I453a50f1aa64f8d4119bf0f860d928aa3e00a144 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81198 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
2024-03-17soc/intel/mtl: Enable RAMTOP caching at SoC level for MTL devicesSubrata Banik
This patch enables the `SOC_INTEL_COMMON_BASECODE_RAMTOP` configuration at the SoC level for all MTL devices. This change streamlines the configuration process, avoiding redundant selections on individual mainboards. BUG=b:306677879 BRANCH=firmware-rex-15709.B TEST=Verified boot functionality on google/ovis and google/rex. Change-Id: I3aa3a83c190d0a0e93c267222a9dca0ac7651f9c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2024-03-17mb/google/rex: Reland RAMTOP caching for OvisSubrata Banik
This patch ensures Ovis baseboard can select RAMTOP caching to improve the boot time w/o any runtime hang. BUG=b:306677879 BRANCH=firmware-rex-15709.B TEST=Verified boot on google/ovis with ~30ms savings in boot time. Change-Id: Ic0b73eb8fb9cd6ca70d3d7168b79dfd0fbc550e3 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2024-03-15mb/google/brya/var/xol: Modify clkreq to clksrc mapping for NVMeSeunghwan Kim
NVMe using clk_src[0] and clk_req[1] mapping to hardware design, Due to inconsistency between PMC firmware and FSP, we need to set clk_src to clk_req number, not same as hardware mapping in coreboot. Then swap correct setting to clk_src=0,clk_req=1 in mFIT. BUG=b:328318578 TEST=build firmware and veirfy suspend function on NVMe SKU DUT. Cq-Depend: chrome-internal:7063434 Change-Id: I1777310782a0f4417bd1bb21287bec5852be966e Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81230 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-15brox: ish: Add Kconfigs for ISHYuval Peress
Modeled after the Rex Kconfigs for ISH. Change-Id: Ic670d550a9aaad64e52489d895b8aac2aee4b5ed Signed-off-by: Yuval Peress <peress@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81050 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-14mb/google/nissa/var/glassway: Add 2nd touchscreen via SSFC configFrank Chu
Define SSFC bit 0-1 in coreboot for add 2nd BOE G7500 touchscreen. BUG=b:329339069 BRANCH=firmware-nissa-15217.B TEST=Check touchscreen can detect and function work. [INFO ] input: GTCH7503:00 2A94:A804 as /devices/pci0000:00/0000:00:15.1/i2c_designware.1/i2c-10/i2c-GTCH7503:00/0014 Change-Id: I85688919864e3cac1beb2442ef3e23fe9d5f916c Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-13mb/google/brox: Enable EC SW SyncShelley Chen
Now that EC software sync has been verified to work on Brox, we can enable it by default. BUG=b:326152804 BRANCH=None TEST=Verify that SW sync occurs Change-Id: I3d356c006fc448125605761f7328d1f1e203a7c4 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81211 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-13mb/google/brya/var/omniknight: Pull down USI_REPORT_EN in romstageJamie Chen
Pull down USI_REPORT_EN(GPP_C6) in romstage to solve an abnormal peek pull high before BL_EN. Because power sequence no meet spec, pre #comment36, it may have ghost touch. BUG=b:326337003 TEST=FW_NAME=omnigul emerge-brya coreboot, measurement of HW and test touch detection by evtest Change-Id: I66f4a7915f135927fbc0a16254dece202dfc23a2 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80769 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-03-12mb/amd/birman_plus: Update glinda DXIO descriptors per schematicsAnand Vaikar
glinda FP8 SOC PCIe lanes are updated per the Birman+ schematics document 105-D99700-00C revision 1.0. Change-Id: If22e57fc57b4824550f2dfa8b843a7809c85dbb6 Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81036 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-12mb/google/brya/var/xol: Use unified AP FW for UFS/Non-UFS SKUsSeunghwan Kim
Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS to use unified AP FW for UFS/Non-UFS SKUs. BUG=b:326481458 BRANCH=firmware-brya-14505.B TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Change-Id: I85c3c1c7ccaae9d46b66d3e7a2efea6dc9056188 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81107 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-03-11mb/google/brya: Create nova variantDavid Wu
Create the nova variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:328711879 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_NOVA Change-Id: Ie1cee43f0e2545288130bcc5152075603695c395 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
2024-03-09mb/google/brya/var/xol: Disable unused controllersSeunghwan Kim
Disable unused controllers in overridetree.cb by referring to xol proto2 schematics. Enabling unused controllers blocks entering s0ix. - I2C3 - SATA - PCIE RP8 - PCIE RP9 - GSPI1 BUG=b:328318578 BRANCH=firmware-brya-14505.B TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Change-Id: I1be7caf8234c32406aa2cff8fc7fe9fa39b16d89 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81105 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-09mb/google/brya/var/xol: Update psys_pmax value to 122WSeunghwan Kim
Update psys_pmax value to 122 from 145. This value is from internal power team. BUG=None BRANCH=firmware-brya-14505.B TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Change-Id: I8bc58343d5736e2457db006972dc229e16d3fe59 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81104 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-09mb/google/brya/var/xol: Configure Acoustic noise mitigationSeunghwan Kim
Enable Acoustic noise mitigation for xol. The setting values are from internal power team. - Enable Acoustic noise mitigation - Set slow slew rate VCCIA and VCCGT to SLEW_FAST_4 - Set FastPkgCRampDisable VCCIA and VCCGT to 1 BUG=None TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Change-Id: I6165ae6ca73d1467a1d2cc7bd545298bd4c2f54f Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81103 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-03-09mb/amd/onyx_poc/devicetree: explicitly assign PCIe engine typeFelix Held
Explicitly assign the 'PCIE' value to the 'type' field of the corresponding MPIO chips in the devicetree. Since the mpio_type enum element 'PCIE' has the value 0, this won't change the behavior, but explicitly assigning this makes this easier to understand. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I84a364cf16c99ba11f67cf033962bbf2c982f6ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/81095 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-09mb/google/brox: Enable Wake on WLAN for SKU1Ashish Kumar Mishra
For SKU1, wake pin is WLAN_PCIE_WAKE_ODL. Update gpio config and corresponding ACPI for WoWLAN. BUG=b:327379404 BRANCH=None TEST=Boot image on SKU1 and check Wake on WLAN from S0ix. Change-Id: I04c35da2c9ac57cafdf7f7a35d83ab2e7a05fe4a Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2024-03-06mb/google/nissa/var/glassway: Tune eMMC DLL valuesDaniel Peng
Update eMMC DLL values to improve initialization reliability. BUG=b:327123701 TEST=Improve reboot on MB with eMMC smoothly. Change-Id: Ice9ee217acf7dc6e3e704bc82529e0b9a8faf184 Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80779 Reviewed-by: Shawn Ku <shawnku@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Simon Yang <simon1.yang@intel.com>
2024-03-06mb/sifive/sifive-unmatched: add support for spi1 x4 modeRonald G Minnich
Tested on an unmatched, both SPI1 x1 and x4 work now. Change-Id: Ida7f195eb6e4fc85018ceb83cf317595127c4af5 Signed-off-by: Ronald G Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-03-05mb/google/oak: Don't build the ChromeEC codebase by defaultMartin Roth
Currently, the oak boards are the only boards that build the ChromeEC by default as a part of the coreboot build. As a part of replacing the chromeec submodule with a different build mechanism, disable this default. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Idd4fe45e52dbdd1c8dccf0d2c09d5cf6d61aa839 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81023 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-03-05mb/emulation/qemu-riscv: Change to -bios optionMaximilian Brune
This changes the virt target so that it can be run with the -bios option and a pflash backend for the flash. QEMU can now be run as follows: qemu -M virt -m 1G -nographic -bios build/coreboot.rom \ -drive if=pflash,file=./build/coreboot.rom,format=raw coreboot will start in DRAM, but still have a flash to put CBFS onto and to load subsequent stages and payload from. Tested bootflow: coreboot -> OpenSBI -> Linux -> u-root Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I009d97fa3e13068b91c604e987e50a65e525407d Reviewed-on: https://review.coreboot.org/c/coreboot/+/80746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com> Reviewed-by: Philipp Hug <philipp@hug.cx>
2024-03-05mb/asus/p8x7x-series: Revert to native max_mem_clock_mhz of 800Keith Hui
The setting was reduced to 666 for native raminit in commit 7039edd2da30 (SNB+MRC boards: Migrate MRC settings to devicetree) based on boot test results at the time. With more changes merged, additional native raminit tests were done on p8z77-m. It is now possible for previously failing memory configurations to operate at full speed. This, combined with multiple reports on gerrit that this family does work at 800, warrants returning the setting to what it was. Change-Id: I1fbe9c8d076fcd633f71424d60585681c40677c4 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79726 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-05mb/google/brya/var/xol: Add VGPIO configurations for PEG60Seunghwan Kim
Add VGPIO configurations for NVMe on PEG60. BUG=b:326481458, b:372086400 BRANCH=firmware-brya-14505.B TEST=Verified DUT could detect NVMe. Install ChromeOS into NVMe and boot from it. Change-Id: I5520dc2a4bf6e788701a774674d223b7e8ad5b44 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-05mb/google/nissa/var/gothrax: Add probe and GPIO config for touchpanelYunlong Jia
Add FW_CONFIG probe to separate touch panel settings. TOUCH_PANEL_ENABLE/TOUCH_PANEL_DISABLE Use different gpio tables based on the value of TOUCH_PANEL. BUG=b:325987249 TEST=emerge-nissa coreboot and run in DUT Change-Id: I23c62406a932815ff1cfafe05b70468b1f9cca54 Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kyle Lin <kylelinck@google.com>
2024-03-05soc/intel/xeon_sp: Drop code to locate the UBOX busPatrick Rudolph
Drop the code to retrieve the UBOX bus numbers. Only keep a minial function that works when called from socket0 to retrieve the bus for UBOX(1). Change-Id: I2b18f02f62b69ec7c73cd5665102cb6bfc6e64b5 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80102 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-03-05mb/google/brya/var/dochi: Add wifi sar tableMorris Hsu
Add wifi sar table for dochi BUG=b:326137130 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Change-Id: Iaf90756eb318bef1ffcda9368a976c0ca209a100 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-04riscv/mb/qemu: fix DRAM probingPhilipp Hug
Current version of qemu raise an exception when accessing invalid memory. Modify the probing code to temporary redirect the exception handler like on ARM platform. Also move saving of the stack frame out to trap_util.S to have all at the same place for a future rewrite. TEST=boots to ramstage Change-Id: I25860f688c7546714f6fdbce8c8f96da6400813c Signed-off-by: Philipp Hug <philipp@hug.cx> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36486 Reviewed-by: ron minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-04mb/google/guybrush: turn off SD ASPM L1.1/L1.2JasonNien
Turn off SD ASPM L1.1/L1.2 as w/a for wlan DMA resume failure We completed 4 runs for each of the 2 tests - power_idle and power_VideoCall. Here are the averages for both the tests: L1ss disabled SD plugged power idle test: 735.3875 L1ss enabled SD plugged power idle test: 737.2335 L1ss disabled SD plugged power video test: 333.29325 L1ss enabled SD plugged power video test: 333.442 BUG=b:254382832 TEST=test pass over 10k cycles Signed-off-by: Jason Nien <finaljason@gmail.com> Change-Id: I4d903f0f6333ffa18069e42be3c932aeae8013d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80237 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-04mb/dell: Add OptiPlex 7020/9020 portMate Kukri
The OptiPlex 7020 and 9020 use physically identical motherboards. WARNING: PWM fan control doesn't work via the EC and the fan runs at a fixed speed. There is likely more EC init to reverse engineer. Each model comes in the following form factors: - 7020: SFF, MT - 9020: USFF (not currently supported), SFF, MT (7020 SFF) Boots Linux and Windows 10: - Tested with an i3-4160 and i5-4460 - DRAM init works using the MRC (4G, 4G+4G) - iGPU init works using libgfxinit (VGA, 2x DP) - PCIe 16x: tested, ok - PCIe 4x: tested, ok - All USB2 and USB3 ports work - SMSC SCH5555 Super I/O: serial works, PS/2 untested - Audio: back and front output works, internal speaker works, mic inputs untested - Ethernet: tested, works (9020 MT) - Tested by Michael Büchler (thanks for the overridetree) Change-Id: Ie7c7089f443aef9890711c4412209bceb1f1e96a Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55232 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-03-04mb/google/brya: Enable CSE telemetry for ADL-NKapil Porwal
BUG=none TEST=Verify CSE telemetry data in boot time data on Yahiko. Before: ``` yahiko-rev9 ~ # cbmem -t 71 entries total: 0:1st timestamp 197,583 (0) ``` After: ``` yahiko-rev9 ~ # cbmem -t 76 entries total: 990:CSME ROM started execution 0 944:CSE sent 'Boot Stall Done' to PMC 49,000 945:CSE started to handle ICC configuration 49,000 (0) 946:CSE sent 'Host BIOS Prep Done' to PMC 51,000 (2,000) 947:CSE received 'CPU Reset Done Ack sent' from PMC 168,000 (117,000) 0:1st timestamp 195,861 (27,861) ``` Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I3f90d0462cb766655bf8e59a90bc550ceefb2256 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79768 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-04mb/system76/adl,rpl: Add 50ms timeout for PCIe 3.0 RPsTim Crawford
The FSP may fail to detect PCIe 4.0 devices in PCIe 3.0 slots on S3 resume. This issue has only been experienced on lemp12, and only with Samsung drives, but implies it could happen on other systems or with other drives as well. A timeout of 50ms is arbitrarily chosen. Tested on lemp12 with Samsung 980 PRO (FW: 3B2QGXA7, 5B2QGXA7) and 990 PRO (FW: 4B2QJXD7) drives. Change-Id: I4f44fc429c52e407b7566d6bb6dd31b2cf85c48d Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80756 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-04mb/system76/adl: Remove duplicate PchHdaAudioLinkHdaEnableTim Crawford
This UPD is hooked up in devicetree since commit 854bd492fcfa ("mb/{system76,msi}: Enable PchHdaAudioLinkHdaEnable via devicetree"). As these boards were in development when the change happened, they still had the UPD set via romstage. Remove them now so they are only set in devicetree. Change-Id: I393e2c7b0134a31feae20f8992d7fd447ff7ee59 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80755 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2024-03-04mb/system76/adl,rpl: Enable PchHdaSdiEnableTim Crawford
Commit 4a58d14506ef ("soc/intel/alderlake: Hook up UPD PchHdaSdiEnable") and commit 2d482386182e ("soc/intel/alderlake: Set PchHdaSdiEnable for Alder Lake") hooked up this UPD in devicetree, causing the FSP default to be overridden (now disabled by default). Enable SDI to fix the following error: [DEBUG] PCI: 00:00:1f.3 init [DEBUG] azalia_audio: base = 0xbfbcc000 [DEBUG] azalia_audio: No codec! [DEBUG] PCI: 00:00:1f.3 init finished in 5 msecs Tested on gaze17-3050: Speaker output works again. Change-Id: Iceac1faec939ce9eea68c335929f96ec5f2bd132 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2024-03-04mb/system76/rpl: Add TCSS ACPI for all boardsDan Campbell
Fixes ACPI errors about missing methods: ACPI BIOS Error (bug): Could not resolve symbol [_SB.PCI0.TDM0], AE_NOT_FOUND (20230628/dswload2-162) ACPI Error: AE_NOT_FOUND, During name lookup/catalog (20230628/psobject-220) ACPI: Skipping parse of AML opcode: OpcodeName unavailable (0x0010) ACPI BIOS Error (bug): Could not resolve symbol [_SB.PCI0.TRP0], AE_NOT_FOUND (20230628/dswload2-162) ACPI Error: AE_NOT_FOUND, During name lookup/catalog (20230628/psobject-220) Tested on lemp12: ACPI errors in dmesg are gone. Change-Id: I9b79cb04f57a27af2a6c8f3118e573f7ac0041e5 Signed-off-by: Dan Campbell <dan@compiledworks.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80791 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-04mb/google/brox: Update Verbtable for beep functionalitypoornima tom
For boot beep functionality, relevant register values are required to be updated. BUG=b:324528901 BRANCH=None TEST=Build & verified Boot Beep functionality on Brox Change-Id: If236c8ac173a279db676af412377fa4e4122c1cd Signed-off-by: poornima tom <poornima.tom@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80416 Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-04mb/google/brya/var/xol: Update NVMe clock source index to 0Seunghwan Kim
Change ClkSrc index for NVME to 0 from 1 by referring to proto2 schematics. BUG=b:326481458 BRANCH=firmware-brya-14505.B TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Change-Id: I7ea1cd7d8e16d4cee953e931d2f1829eae7d1978 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80768 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-03Revert "Revert "mb/sifive: Add Hifive Unmatched mainboard""ron minnich
This reverts commit ec7b48076009cfe82e5ee91050f5fc66c4850193. Reason for revert: <Reland> I made the commit out of order with the fu740 commit; that's now merged so there should be no problem. Signed-off-by: ron minnich <rminnich@gmail.com> Change-Id: I2fb8c2e0a7fcd5f26f4a004e0949332b108b6fcf Reviewed-on: https://review.coreboot.org/c/coreboot/+/81052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: ron minnich <rminnich@gmail.com>
2024-03-02Revert "mb/sifive: Add Hifive Unmatched mainboard"Martin L Roth
This reverts commit e26bcaefbeb1d64cf2a78ad54e0f6ad4affab086. Reason for revert: Patch submitted out of order. Change-Id: I71c024b13411c4e0c9b4d6358f9cd31c57bbbfe2 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2024-03-02mb/sifive: Add Hifive Unmatched mainboardMaximilian Brune
working: Linux v6.3.5 poweroff via Linux PMIC driver UART console output SPI -> SDCARD I2C -> PMIC 16 GB LPDDR4 memory VSC8541XMV-02 (gigabit ethernet PHY) PCIe x16 Slot M.2 NVMe Slot MSEL: only '1100' has been tested untested: M.2 WiFi/Bluetooth Slot tested bootflow: ZSBL -> coreboot --FDT-> Linuxboot -> uroot --kexec-> ubuntu defconfig used: CONFIG_VENDOR_SIFIVE=y CONFIG_BOARD_SIFIVE_HIFIVE_UNMATCHED=y CONFIG_PAYLOAD_NONE=n CONFIG_PAYLOAD_ELF=y CONFIG_PAYLOAD_FILE="[path-to-linux]/arch/riscv/boot/Image" CONFIG_PAYLOAD_IS_FLAT_BINARY=y CONFIG_PAYLOAD_OPTIONS="-l 0x82000000 -e 0x82000000" CONFIG_COMPRESSED_PAYLOAD_LZMA=y uroot kexec command: kexec -d --cmdline "console=ttySIF0 root=/dev/mmcblk0p1 debug" \ --initrd /mnt/boot/initrd.img-6.5.0-9-generic \ /mnt/boot/vmlinuz-6.5.0-9-generic Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ife0afdce89d5a1a1b936c30c8027f1bc191b8c53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2024-03-02mb/google/nissa/var/glassway: Select drivers for gpio-keys and GL9750Daniel Peng
Add 2 configuration on Kconfig for glassway. - DRIVERS_GENERIC_GPIO_KEYS - DRIVERS_GENESYSLOGIC_GL9750 BUG=b:319071869 BRANCH=firmware-nissa-15217.B TEST=Local build successfully and boot to OOBE normally. Change-Id: Id7e358d2f472cd435d2828f6256f5ee91dfb8ef6 Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80766 Reviewed-by: Shawn Ku <shawnku@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-01mb/google/nissa/var/glassway: Add GPIO tableDaniel Peng
Refer to the reference board of nivviks, and update GPIO settings via glassway schematic of ca24a_r10_240108_v3_mb_gsen_gmr.pdf. BUG=b:319071869 BRANCH=firmware-nissa-15217.B TEST=Local build successfully and boot to OOBE normally. Change-Id: I0de743746160c6eb081cb9a061ac1703b01ba5b4 Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-01mb/google/link: Use automatic fan controlMatt DeVillier
Several users complained of link's fan not running at all, particularly when using ChromeOS Flex. Enabling auto fan control at boot/s3 resume resolved the issue for them. Change-Id: I8f0db6b6c94fac2e0dcb580be0f6df839780c38c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80713 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-29mb/google/skyrim/var/skyrim: Hide fingerprint reader from Windows OSMatt DeVillier
No Windows driver exists or is needed, so hide to prevent an unknown device from being listed in Windows Device Manager. Same change was made for frostflow variant previously. TEST=build/boot Win11 on skyrim, verify unknown device for the fingerprint reader no longer present. Change-Id: Ia700aa4ccd478bc734db012e1419e566a5dcf493 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80711 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-29mb/amd/birman_plus: Add glinda SOC option for Birman+Anand Vaikar
Change-Id: I1efeb7cf1dca31e2a7e17f483f8882925b55e7ea Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2024-02-29mb/lenovo: Add ThinkCentre M700/M900 Tiny board (Skylake/Kaby Lake)Michał Kopeć
The M700 / M900 Tiny boards are USFF PCs that come with Skylake LGA1151 processors. M700 comes with B150 chipset, M900 comes with Q170 and is vPro capable. There is an onboard discrete TPM 1.2. Intel PTT fTPM can also be enabled in vendor FW, but for now it's not used here. LPSS UART for debugging is available on pins 17,18 on the underside of the mainboard, but it is not enabled by default. Tested unit is M900 with i5-6500T. Boots to Fedora 38 w/ kernel 6.5.5 and Windows 11. Tested and working: - Serial port (via optional module) - Rear DisplayPort connectors - Graphics w/ libgfxinit - Ethernet - SATA - NVMe - Internal speaker, front combo jack, rear line-out - Discrete TPM 1.2 - USB ports (Port 1 untested, apparently broken on my unit) - M.2 2230 Wi-Fi slot (needs ASPM L1s disabled) - S3 suspend - ME disable via NVRAM setting Untested: - Front mic input - Optional expansion headers: DisplayPort, USB, PS/2, SATA / PCIe Change-Id: I6786e068ec03c8bf243e1767cd7b9d50512ea77f Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-29mb/clevo/tgl-u: hda_verbs: correct vendor value commentsMichael Niewöhner
The vendor vendor values for the hda verbs´ location field were decoded wrong because of relying on the wrong bit shift value in `device/azalia_device.h`. Since this was fixed now, correct the comments. Change-Id: I45b1d09d5a11b357ac2a20ef448ea642540cdc99 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80720 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-29mainboard/lenovo: Add ThinkCentre M710s (Skylake)Nicholas Sudsgaard
The processor may be a Pentium or 6/7th generation Core i3/i5/i7. This port was tested on an i5-7400. Working: - Can boot Ubuntu 22.04.1 (Linux 6.5.0) using payloads: - SeaBIOS - TianoCore EDK 2 - Internal flashing (from coreboot) - PEG - PCIe - SATA - M.2 SSD - M.2 WLAN (+ Bluetooth) - LAN - USB - Memory card reader - CPU fan - VGA (DP bridge) - Display ports - Audio (output) - COM1 - TPM Not Working: - SuperIO related things - Power button LED - PCIe clock related things and AER issues (LiveCD) - Some drm issue when using EDK 2 and libgfxinit (LiveCD) - ME cleaner Untested: - Audio (input) Won't Test: - COM2 header - LPT header - PS/2 keyboard and mouse Thanks to Nico Huber and everyone else on the IRC for helping me write my first port! Change-Id: I551753aecfbd2c0ee57d85bb22cb943eb21af3cc Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80343 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-29include/device/azalia_device.h: Merge location1 and location2Nicholas Sudsgaard
This changes the location to be expressed as a combination of ORs. This allows aliases for special locations. For example, `AZALIA_REAR_PANEL` is easier to read than `AZALIA_EXTERNAL_PRIMARY_CHASSIS, AZALIA_SPECIAL7`. References: - Intel High Definition Audio Specification, rev. 1.0a, page 180, Table 110. Location. Change-Id: I5a61a37ed70027700f07f1532c500f04d7a16ce1 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-29include/device: Merge enums from azalia_device.h and azalia.hNicholas Sudsgaard
We were keeping 2 copies of the same thing (albeit there were some slight differences). As azalia_device.h is used much more in the codebase this was kept as the base and then some of the nice features of azalia.h were incorporated. The significant changes are: - All enum names now use the `AZALIA_` prefix. This also drops the AzaliaPinConfiguration enum as it was never used since added in 2013. Change-Id: Ie874b083a18963679981a9cd2b25d123890d628e Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80695 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2024-02-29mb/qemu/fw_cfg: Support using DMA to select fw_cfg fileAlper Nebi Yasak
Commit 8dc95ddbd4a935 ("emulation/qemu-i440fx: use fw_cfg_dma for fw_cfg_read") adds DMA support to interface with the QEMU firmware configuration device, and uses it to read from the "files" exposed by the device. However, the file selection step still uses port-based IO. Use DMA for fw_cfg file selection when possible, as a step towards porting this driver to other architectures. Change-Id: I46f9915e6df04d371c7084815f16034c7e9879d4 Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-28mb/google/brya/var/xol: Add storage option in FW_CONFIGSeunghwan Kim
Add STORAGE config in FW_CONFIG to support NVME sku. - STORAGE_UFS : 0 - STORAGE_NVME: 1 BUG=b:326481458 BRANCH=firmware-brya-14505.B TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Change-Id: Id8316f643ba9a55319b67431a24a507e92419aa7 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80767 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-02-27mb/qemu/fw_cfg: Use fw_cfg_read() to read SMBIOS dataAlper Nebi Yasak
The QEMU firmware configuration driver can help initialize SMBIOS tables using the table data that QEMU provides over the device. While doing so, it reads from the device "file" manually using port-based IO. Use the fw_cfg_read() helper function to read the SMBIOS-related file, so that the driver is easier to port the driver to other architectures. Change-Id: I18e60b8e9de34f2b0ff67af4113beec1d7467329 Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80367 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-27mb/qemu/fw_cfg: Fix build when not generating SMBIOS tablesAlper Nebi Yasak
Parts of the QEMU firmware configuration device driver refers to SMBIOS related kconfig values. These depend on GENERATE_SMBIOS_TABLES and are undefined if it isn't enabled, causing a build error. Cover the SMBIOS-related region in this driver with an #if directive checking the necessary config option. This is mostly to help port the driver to non-x86 architectures where support for generating SMBIOS tables isn't there yet. Change-Id: I3ff388d4574eb52686a5dda3dcbc3d64a7ce6f7b Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80366 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-27mb/google/nissa/var/glassway: Add initial override devicetreeDaniel Peng
Refer to the reference board of nivviks, and update devicetree settings via glassway schematic of ca24a_r10_240108_v3_mb_gsen_gmr.pdf. BUG=b:319071869 BRANCH=firmware-nissa-15217.B TEST=Local build successfully and boot to OOBE normally. Change-Id: Ibbb10a373bd5fa52a0833b81133517d2a088536b Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80742 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-26mb/google/rex/var/deku: replace IOEX with GPIOsEran Mitrani
IOEX was replaced with GPIOs, this CL makes the required changes BUG=b:325533052 TEST=Built FW image correctly. Change-Id: I09ebba336b179cb36c6801b47ee0be5ade08c257 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80570 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-02-26mb/google/rex/var/deku: Correct GPIO F19/F20 to not connectedEran Mitrani
GPP_F19 and GPP_F20 sre set incorrectly previously. Change them to not connected according to schematics. BUG=b:305793886 TEST=Built FW image correctly. Change-Id: Ifb6da1f8696f44cb47be3d1de83c55e62b12a9e9 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80569 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-02-26mb/hp/snb_ivb_desktops: Make baseboard more genericRiku Viitanen
In preparation to merging all the other HP sandy/ivy desktops in here as variants. Move hda_verb.c, early_init.c, gma-mainboard.ads and data.vbt into variant directories. Kconfig: Move options not common to the others under the variants instead. devicetree: Move XHCI to variant overridetrees (8200 gen has no USB 3) board_info.txt: Make it more generic. It seems to be copied from 8200 SFF and inaccurate to Z220 anyway. TEST: BUILD_TIMELESS=1 & Don't include .config in ROM image. CMT and SFF ROMs are (SHA1) same as before. Change-Id: Icce22efb8d353359781db3f03c67058d8fbe11b8 Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-02-26soc/mediatek: Add `MEDIATEK_DRAM_ADAPTIVE` config to support dram adaptiveYidi Lin
Starting from MT8195, MediaTek platform supports "dram adaptive" to automatically detect dram information, including channel, rank, die size..., and can automatically configure EMI settings. So we can just pass a placeholder param blob to `mt_mem_init_run` by enabling this option. Platforms (MT8173, MT8183, MT8192) which do not support "dram adaptive" need to implement `get_sdram_config` to get onboard DRAM configuration info. TEST=emerge-geralt coreboot && emerge-asurada coreboot TEST=CONFIG_MEDIATEK_DRAM_ADAPTIVE is set to y on geralt TEST=CONFIG_MEDIATEK_DRAM_ADAPTIVE is no set on asurada Change-Id: I05a01b1ab13fbf19b2a908c48a540a5c2e1ccbdc Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-02-25mb/google/rex/var/deku: Refactor SSD power sequencingSubrata Banik
Improve SSD readiness time by enabling earlier power sequencing. Here are the two GPIOs to look for: * GPP_A19: Power Enable * GPP_A20: PERST The flow is presented as `stage (GPIO PAD/Value)` for easy understanding: bootblock (A20/0, A19/1) | v romstage (A20/1) Ideally, we don't need SSD power sequencing at ramstage, hence, remove the logic from ramstage. TEST=Able to build and boot google/deku using NVMe without any problems. S0ix and read/write from/to SSD are also normal. Change-Id: Iedaff8a793f1ba5d2b97352b95c4dfdd2b818ebd Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80664 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-25mb/google/rex/var/karis: Refactor SSD power sequencingSubrata Banik
Improve SSD readiness time by enabling earlier power sequencing. Here are the two GPIOs to look for: * GPP_A19: Power Enable * GPP_A20: PERST The flow is presented as `stage (GPIO PAD/Value)` for easy understanding: bootblock (A20/0, A19/1) | v romstage (A20/1) | v ramstage (A19/1, A20/1) Ideally, we don't need SSD power sequencing at ramstage, but due to the fact that Karis has RO locked, any change in the bootblock won't be applicable for FSI'ed karis devices. Therefore, we're keeping the existing ramstage power sequencing flow as is TEST=Able to build and boot google/karis using NVMe without any problems. S0ix and read/write from/to SSD are also normal. Change-Id: I79171a7830b75f5c20bbe30023f2814a62743a13 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80663 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-25mb/google/rex/var/ovis: Refactor SSD power sequencingSubrata Banik
Improve SSD readiness time by enabling earlier power sequencing. Here are the two GPIOs to look for: * GPP_A19: Power Enable * GPP_A20: PERST The flow is presented as `stage (GPIO PAD/Value)` for easy understanding: bootblock (A20/0, A19/1) | v romstage (A20/1) Ideally, we don't need SSD power sequencing at ramstage, hence, remove the logic from ramstage. TEST=Able to build and boot google/ovis using NVMe without any problems. S0ix and read/write from/to SSD are also normal. Change-Id: I891b5a6d2c29f5d940793a4e90215265f2a4fcd8 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-02-25mb/google/rex/var/rex0: Refactor SSD power sequencingSubrata Banik
Improve SSD readiness time by enabling earlier power sequencing. Here are the two GPIOs to look for: * GPP_A19: Power Enable * GPP_A20: PERST The flow is presented as `stage (GPIO PAD/Value)` for easy understanding: bootblock (A20/0, A19/1) | v romstage (A20/1) Ideally, we don't need SSD power sequencing at ramstage, hence, remove the logic from ramstage. TEST=Able to build and boot google/rex0 using NVMe without any problems. S0ix and read/write from/to SSD are also normal. Change-Id: Idde2f7693771f1d7e3171e51232d1bb899bfe33e Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-02-25mb/google/rex/var/screebo: Refactor SSD power sequencingSubrata Banik
Improve SSD readiness time by enabling earlier power sequencing. Here are the two GPIOs to look for: * GPP_A19: Power Enable * GPP_A20: PERST The flow is presented as `stage (GPIO PAD/Value)` for easy understanding: bootblock (A20/0, A19/1) | v romstage (A20/1) | v ramstage (A19/1, A20/1) Ideally, we don't need SSD power sequencing at ramstage, but due to the fact that Screebo has RO locked, any change in the bootblock won't be applicable for FSI'ed screebo devices. Therefore, we're keeping the existing ramstage power sequencing flow as is. TEST=Able to build and boot google/screebo using NVMe without any problems. S0ix and read/write from/to SSD are also normal. Change-Id: I0ee1fa4613178da8771c9e6b5ee871e50ea6324c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80640 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-23arch/x86/ioapic: use uintptr_t for IOAPIC base addressFelix Held
Use uintptr_t for the IOAPIC base parameter of the various IOAPIC- related functions to avoid needing type casts in the callers. This also allows dropping the VIO_APIC_VADDR define and consistently use the IO_APIC_ADDR define instead. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I912943e923ff092708e90138caa5e1daf269a69f Reviewed-on: https://review.coreboot.org/c/coreboot/+/80358 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-02-22riscv/mb/qemu: fix qemu invocation commentPhilipp Hug
Change-Id: I773fb39801f180fead584942dfb385fcde9d2680 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80262 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: ron minnich <rminnich@gmail.com>
2024-02-22mb/google/brox: Disable Early EC SyncShelley Chen
Early EC Sync does not need to be enabled in coreboot as EFS2 is being enabled in the EC. BUG=b:326152804 BRANCH=None TEST=emerge-brox coreboot To be tested with EC sync enabled Change-Id: I08bdbe9f3dcea837b0b148adc137c03d3461877a Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80689 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-22mb/intel/adlrvp: Remove ADLRVP_M mainboardSean Rhodes
These boards are not commerically available so can be removed. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Icc853a9df44a4a770db76e119644f0b4c7fcc2c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-22 10:34:13 +0000