vc/amd/opensil/genoa_poc/mpio: move PCIe port function below mpio chip

Move the gpp_bridge_* device functions that are bridges to the external
PCIe ports below the corresponding mpio chip. This avoids the need for
dummy devices and does things in a slightly more coreboot-native way.

TEST=PCIe lane config reported by openSIL is identical

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: Varshit Pandya <pandyavarshit@gmail.com>
Change-Id: I7e39bf68d30d7d00b16f943953e8207d6fe9ef41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81340
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 95 insertions, 119 deletions

diff --git a/src/mainboard/amd/onyx_poc/devicetree.cb b/src/mainboard/amd/onyx_poc/devicetree.cb
index 578bc42f7a..c1b2f5c28c 100644
--- a/src/mainboard/amd/onyx_poc/devicetree.cb
+++ b/src/mainboard/amd/onyx_poc/devicetree.cb
@@ -55,36 +55,30 @@ chip soc/amd/genoa_poc
 	device domain 0 on
 		device ref iommu_0 on end
 		device ref rcec_0 on end
-		device ref gpp_bridge_0_0_a on
-			chip vendorcode/amd/opensil/genoa_poc/mpio # P2
-				register "type" = "IFTYPE_PCIE"
-				register "start_lane" = "48"
-				register "end_lane" = "63"
-				register "gpio_group" = "1"
-				register "aspm" = "L1"
-				device generic 0 on end # dummy for configuring mpio
-			end
-		end
-		device ref gpp_bridge_0_0_b on
-			chip vendorcode/amd/opensil/genoa_poc/mpio # G2
-				register "type" = "IFTYPE_PCIE"
-				register "start_lane" = "112"
-				register "end_lane" = "127"
-				register "gpio_group" = "1"
-				register "aspm" = "L1"
-				register "hotplug" = "ServerExpress"
-				device generic 0 on end
-			end
-		end
-		device ref gpp_bridge_0_0_c on
-			chip vendorcode/amd/opensil/genoa_poc/mpio
-				register "type" = "IFTYPE_PCIE"
-				register "start_lane" = "128"
-				register "end_lane" = "131"
-				register "gpio_group" = "1"
-				register "aspm" = "L1"
-				device generic 0 on end
-			end
+		chip vendorcode/amd/opensil/genoa_poc/mpio # P2
+			register "type" = "IFTYPE_PCIE"
+			register "start_lane" = "48"
+			register "end_lane" = "63"
+			register "gpio_group" = "1"
+			register "aspm" = "L1"
+			device ref gpp_bridge_0_0_a on end
+		end
+		chip vendorcode/amd/opensil/genoa_poc/mpio # G2
+			register "type" = "IFTYPE_PCIE"
+			register "start_lane" = "112"
+			register "end_lane" = "127"
+			register "gpio_group" = "1"
+			register "aspm" = "L1"
+			register "hotplug" = "ServerExpress"
+			device ref gpp_bridge_0_0_b on end
+		end
+		chip vendorcode/amd/opensil/genoa_poc/mpio
+			register "type" = "IFTYPE_PCIE"
+			register "start_lane" = "128"
+			register "end_lane" = "131"
+			register "gpio_group" = "1"
+			register "aspm" = "L1"
+			device ref gpp_bridge_0_0_c on end
 		end
 		device ref gpp_bridge_0_a on
 			device ref xhci_0 on end
@@ -99,51 +93,43 @@ chip soc/amd/genoa_poc
 	device domain 1 on
 		device ref iommu_1 on end
 		device ref rcec_1 on end
-		device ref gpp_bridge_1_0_a on
-			chip vendorcode/amd/opensil/genoa_poc/mpio # P3
-				register "type" = "IFTYPE_PCIE"
-				register "start_lane" = "16"
-				register "end_lane" = "31"
-				register "gpio_group" = "1"
-				register "aspm" = "L1"
-				device generic 0 on end
-			end
-		end
-		device ref gpp_bridge_1_0_b on
-			chip vendorcode/amd/opensil/genoa_poc/mpio # G3
-				register "type" = "IFTYPE_PCIE"
-				register "start_lane" = "80"
-				register "end_lane" = "95"
-				register "gpio_group" = "1"
-				register "aspm" = "L1"
-				device generic 0 on end
-			end
+		chip vendorcode/amd/opensil/genoa_poc/mpio # P3
+			register "type" = "IFTYPE_PCIE"
+			register "start_lane" = "16"
+			register "end_lane" = "31"
+			register "gpio_group" = "1"
+			register "aspm" = "L1"
+			device ref gpp_bridge_1_0_a on end
+		end
+		chip vendorcode/amd/opensil/genoa_poc/mpio # G3
+			register "type" = "IFTYPE_PCIE"
+			register "start_lane" = "80"
+			register "end_lane" = "95"
+			register "gpio_group" = "1"
+			register "aspm" = "L1"
+			device ref gpp_bridge_1_0_b on end
 		end
 	end
 
 	device domain 2 on
 		device ref iommu_2 on end
 		device ref rcec_2 on end
-		device ref gpp_bridge_2_0_a on
-			chip vendorcode/amd/opensil/genoa_poc/mpio # P1
-				register "type" = "IFTYPE_PCIE"
-				register "start_lane" = "32"
-				register "end_lane" = "47"
-				register "gpio_group" = "1"
-				register "aspm" = "L1"
-				register "hotplug" = "ServerExpress"
-				device generic 0 on end
-			end
-		end
-		device ref gpp_bridge_2_0_b on
-			chip vendorcode/amd/opensil/genoa_poc/mpio # G1
-				register "type" = "IFTYPE_PCIE"
-				register "start_lane" = "64"
-				register "end_lane" = "79"
-				register "gpio_group" = "1"
-				register "aspm" = "L1"
-				device generic 0 on end
-			end
+		chip vendorcode/amd/opensil/genoa_poc/mpio # P1
+			register "type" = "IFTYPE_PCIE"
+			register "start_lane" = "32"
+			register "end_lane" = "47"
+			register "gpio_group" = "1"
+			register "aspm" = "L1"
+			register "hotplug" = "ServerExpress"
+			device ref gpp_bridge_2_0_a on end
+		end
+		chip vendorcode/amd/opensil/genoa_poc/mpio # G1
+			register "type" = "IFTYPE_PCIE"
+			register "start_lane" = "64"
+			register "end_lane" = "79"
+			register "gpio_group" = "1"
+			register "aspm" = "L1"
+			device ref gpp_bridge_2_0_b on end
 		end
 
 	end
@@ -151,56 +137,46 @@ chip soc/amd/genoa_poc
 	device domain 3 on
 		device ref iommu_3 on end
 		device ref rcec_3 on end
-		device ref gpp_bridge_3_0_a on
-			chip vendorcode/amd/opensil/genoa_poc/mpio # P0
-				register "type" = "IFTYPE_PCIE"
-				register "start_lane" = "0"
-				register "end_lane" = "15"
-				register "gpio_group" = "1"
-				register "aspm" = "L1"
-				device generic 0 on end
-			end
-		end
-		device ref gpp_bridge_3_0_b on
-			chip vendorcode/amd/opensil/genoa_poc/mpio # G0
-				register "type" = "IFTYPE_PCIE"
-				register "start_lane" = "96"
-				register "end_lane" = "111"
-				register "gpio_group" = "1"
-				register "aspm" = "L1"
-				device generic 0 on end
-			end
-		end
-		device ref gpp_bridge_3_0_c on # WAFL
-			chip vendorcode/amd/opensil/genoa_poc/mpio
-				register "type" = "IFTYPE_PCIE"
-				register "start_lane" = "132"
-				register "end_lane" = "133"
-				register "gpio_group" = "1"
-				register "aspm" = "L1"
-				device generic 0 on end
-			end
-		end
-		device ref gpp_bridge_3_1_c on # BMC
-			chip vendorcode/amd/opensil/genoa_poc/mpio
-				register "type" = "IFTYPE_PCIE"
-				register "start_lane" = "134"
-				register "end_lane" = "134"
-				register "gpio_group" = "1"
-				register "aspm" = "L1"
-				register "bmc" = "1"
-				device generic 0 on end
-			end
-		end
-		device ref gpp_bridge_3_2_c on # BMC
-			chip vendorcode/amd/opensil/genoa_poc/mpio
-				register "type" = "IFTYPE_PCIE"
-				register "start_lane" = "135"
-				register "end_lane" = "135"
-				register "gpio_group" = "1"
-				register "aspm" = "L1"
-				device generic 0 on end
-			end
+		chip vendorcode/amd/opensil/genoa_poc/mpio # P0
+			register "type" = "IFTYPE_PCIE"
+			register "start_lane" = "0"
+			register "end_lane" = "15"
+			register "gpio_group" = "1"
+			register "aspm" = "L1"
+			device ref gpp_bridge_3_0_a on end
+		end
+		chip vendorcode/amd/opensil/genoa_poc/mpio # G0
+			register "type" = "IFTYPE_PCIE"
+			register "start_lane" = "96"
+			register "end_lane" = "111"
+			register "gpio_group" = "1"
+			register "aspm" = "L1"
+			device ref gpp_bridge_3_0_b on end
+		end
+		chip vendorcode/amd/opensil/genoa_poc/mpio
+			register "type" = "IFTYPE_PCIE"
+			register "start_lane" = "132"
+			register "end_lane" = "133"
+			register "gpio_group" = "1"
+			register "aspm" = "L1"
+			device ref gpp_bridge_3_0_c on end # WAFL
+		end
+		chip vendorcode/amd/opensil/genoa_poc/mpio
+			register "type" = "IFTYPE_PCIE"
+			register "start_lane" = "134"
+			register "end_lane" = "134"
+			register "gpio_group" = "1"
+			register "aspm" = "L1"
+			register "bmc" = "1"
+			device ref gpp_bridge_3_1_c on end # BMC
+		end
+		chip vendorcode/amd/opensil/genoa_poc/mpio
+			register "type" = "IFTYPE_PCIE"
+			register "start_lane" = "135"
+			register "end_lane" = "135"
+			register "gpio_group" = "1"
+			register "aspm" = "L1"
+			device ref gpp_bridge_3_2_c on end # BMC
 		end
 		device ref gpp_bridge_3_a on
 			device ref xhci_3 on end