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2021-06-30mb/google/dedede/var/storo: Enable Wifi SAR for storoTao Xia
BUG=b:190027970,b:178175837 BRANCH=dedede TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage. Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I7084f9b7be2b66adda2d9d5a83ce5dd9c31d01b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-30mb/google/brya: Set GPP_B3 to APIC modeEric Lai
Set GPP_B3 to APIC mode to avoid PCI IRQ conflict. BUG=b:181555900 TEST=check dmesg there are no IRQ request errors like below. genirq: Flags mismatch irq 27. 00002008 (sx932x_event) vs. 00000080 (idma64.1) Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Idf88fae9e244858445c45e66e26715cebe0c93ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/55777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-29mb/google/guybrush: Initialize WWAN for USB if requestedMartin Roth
To set the Fibocom 850-GL module to USB mode, it needs to be disabled when PCIe training happens, or it will automatically switch to PCIe mode. This patch makes sure it's shut down when training happens in FSP-M. It will be brought up in ramstage and will be available for USB enumeration later. BUG=b:187316460 TEST=Run lsusb from the OS and see that the Fibocom module is present on USB. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I153eb6cd7c3a0e2cc3b71c99f76db3e565173cfe Reviewed-on: https://review.coreboot.org/c/coreboot/+/54743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-29mb/google/guybrush: Update romstage power-on timings for PCIeMartin Roth
This configures the romstage portion of the PCIe GPIOs in the correct sequence to meet the power-on timings. The PCIe_RST line is anded with the Aux reset lines, so to take the PCIe devices out of reset, both need to be brought hign. BUG=b:184796302, b:184598323 TEST=Verify timings between GPIO init sections. All available modules are present after training. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ib1990bba31c84827467d4ff8a15f1e0682501e70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54741 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-29mb/google/guybrush: Update bootblock power-on timings for PCIeMartin Roth
This configures the bootblock portion of the PCIe GPIOs in the correct sequence to meet the power-on timings. Setting the PCIE Reset happens in coreboot instead of in the FSP. The Aux reset lines are anded with the PCIe RST line, so both have to be brought up together. On v1 of guybrush, the PCIe reset line also resets EC communication, so it must be brought up immediately on that version. BUG=b:184796302, b:184598323 TEST=Verify timings between GPIO init sections. All available modules are present after training. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I2d0b812b654b0cd317a2c8c1ce554e850c96be44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-29Kconfig: Escape variablesPatrick Georgi
New kconfig parsers interpret $(var) themselves, leading to empty fields. Old kconfig understands \$(var), so use that. Change-Id: I927fc9dc7a66211bfe51d4324cf7c51b555ea3a8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55912 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-29mb/google/herobrine: Add Senor and Piglin variantsShelley Chen
Add configs for Herobrine variants. Also enable ec sw sync as this should not be disabled by default. BUG=b:182963902 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_SENOR -x -a -B ./util/abuild/abuild -p none -t GOOGLE_PIGLIN -x -a -B Change-Id: Ide4e375aa0236dce65a954a2f68455d05fa841eb Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-06-29mb/google/guybrush: provide full range backlight settings to kernelPratik Vishwakarma
Utilize the SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF option to provide full range backlight settings to the kernel. BUG=b:190443612 Change-Id: If071b701c383e3a6b78bf45a562f5a9b31397835 Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-29mb/google/brya0: Enable MIPI UFCVarshit B Pandya
1. Add 2 port 2 endpoint 2. Add support for OVTI5675 3. Guard entries in override device tree by FW_CONFIG MIPI UFC is on I2C2 This configuration is as per P2 schematics BUG=b:190674542 TEST=Build and Boot on Brya Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: Id3ef974994fd0d447e398b365cdf01d78c94cc4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/55670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-06-28mb/google/guybrush: Configure eSPI requirements before setting it upMartin Roth
When initializing eSPI early, guybrush has requirements to configure the bus properly. Those are normally run in bootblock_mainboard_early_init, but when setting up eSPI early, those have not run yet. BUG=192100564 TEST=Build along with previous patch, eSPI works on guybrush Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ifec6113d48aea0bb5efe47909e4faf0161148a99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55864 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-28mb/google/volteer/var/volet: add G2 touch supportSheng-Liang Pan
Enable G2 touchscreen support for Volet. BUG=b:185097280 TEST=emerge-volteer coreboot chromeos-bootimage Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I907356448b5d5cbf3974717654ea09cd995962f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55835 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-28mb/google/dedede/var/blipper: Update devicetree and gpio settingZanxi Chen
To reduce power load, set unused GPIOs to NC and close unused interface in devicetree. GPIOs and interfaces are as below: GPIO: GPP_C18/C19/D12/D14/D15/D19/D20/D21/E00/E02/H06/H07 Interface: I2C1/I2C3/I2C5 USB: port2_3/2_4/2_6 BUG=b:185044041 BRANCH=dedede TEST=Built bios and test, it reduces power load without affecting device function. Change-Id: Ib5999f0e129bf3e660fe293eda7af3e8e1426151 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Ben Kao <ben.kao@intel.com>
2021-06-28mb/google/brya0: Add FW_CONFIG for UFCVarshit B Pandya
UFC on brya can be USB or MIPI Add FW_CONFIG bit for this option Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I2f1492d7c769aba8da80763124dda474b32cfbfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/55780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-28mb/google/brya: Update mainboard properties for BB retimer upgradeMaulik V Vaghela
This changes updates mainboard properties by adding DFP number and power_gpio for each DFP. Reference CB:54292 BUG=b:186521258 TEST=Updated BB retimer FW from 3.4 to 3.5 without any device connected. Change-Id: I24a02fd446cb66bda9e66e59802b4deea6894273 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-06-28mb/google/dedede/var/sasukette: Update DPTF parametersTao Xia
Update DPTF parameters from internal thermal team. BUG=b:180875580 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I4dbe3947779395903d7999627948d3e97d6cc985 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-28mb/google/dedede/var/cret: Add ssfc codec cs42l42 supportDtrain Hsu
Add cs42l42 codec support in cret. BUG=b:188623237, b:189073353 TEST=Build and boot to check functional with cs42l42 EV board. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I2c53291e07fd785c1360c05171eed634788bc665 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55091 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-28mb/intel/adlrvp_m: Enable TCSS USB ports device pathBernardo Perez Priego
This provide a more consistent mechanism to enable corresponding USB TCSS port. BUG=b:182960979 TEST=Boot device, Type C port should operate correctly. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: Iadc0df2e6e19a5afacbb7db1ae0bc7546dbcdc1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/55772 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-28mb/google/dedede/var/pirika: Update DPTF parametersAlex1 Kao
Update DPTF parameters from internal thermal team. BUG=b:190518303 BRANCH=None TEST=emerge-dedede coreboot Change-Id: I4005047e0c5f39a12c161a92fbd0afaaec1dc976 Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com>
2021-06-28mb/google/dedede/var/pirika: Support audio AMP auto modeAlex1 Kao
Support audio AMP selection with fw_config. BUG=b:188446060 BRANCH=None. TEST=built pass Change-Id: Idf0eb2a87bfa9665e61d185e37adb90987f3cefb Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com>
2021-06-28mb/google/dedede/var/blipper: Enable ELAN touchscreenZanxi Chen
Modify driver from hid to generic(ELAN0001 that used generic driver without hid). BUG=b:191620724 BRANCH=dedede TEST=build bios and boot, touchscreen will work properly. Change-Id: Ife77d514d9906049f237edd169bc07bb53c48579 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
2021-06-26mb/google/brya/variants/primus: init overridetree for PrimusCasper Chang
init overridetree.cb based on the schematic ver MB_20210616C. BUG=b:191897776, b:191897775 Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I185b36e34d24b703092e3798e91c70ce3912b11f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-25mb/facebook/fbg1701/fbg1701/vboot-rw.fmd: Correct FMD statementFrans Hendriks
CB:55452 uses FMAP instead of "cbfs master header". The flash size statement in vboot-rw.fmd does not contain the start address, resulting in a non-booting system. Add start address to FLASH statement. BUG = N/A TEST = Boot Facebook FBG1701 Change-Id: Id05ad33babb416a37c657b25cdb1e98d47c1a56d Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-25mb/google/{octopus,reef}: Fix size of SI_BIOS region in default.fmdMatt DeVillier
0xf7f000 - 0x1000 = 0xf7e000, not 0xf6f000. This fixes build failure when selecting the option to validate the layout using the flash descriptor (CONFIG_VALIDATE_INTEL_DESCRIPTOR) Test: build google/casta successfully with IFD validation selected Change-Id: I6df67f76f5d766a9f4f85ffc3e1f0de4a241f509 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55815 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25security/intel/cbnt: Remove fixed size requirementArthur Heymans
The CBnT provisioning tooling in intel-sec-tools are now cbfs aware and don't need to have a fixed size at buildtime. Tested on OCP/Deltalake with CBnT enabled. Change-Id: I446b5045fe65f51c5fa011895cd56dbd25b6ccc7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55821 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christopher Meis <christopher.meis@9elements.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25mb/google/brya/variants/primus: add dram part idMalik_Hsu
This change adds mem_parts_uesd.txt that contains the only memory parts used by primus for Proto build and Makefile.inc generated by gen_part_id.go using mem_parts_used.txt. BUG=b:186091208,b:189169995 Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I423fd9ad4349c51c6e6b166734ae706509d6ac3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/55748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-06-25mb/google/volteer/var/chronicler: add chronicler memory configuration and ↵Sheng-Liang Pan
gpio and devicetree settings add memory configuration for chronicler, based on schematic and gpio table, update gpio and devicetree settings for chronicler. BUG=b:187318819 BRANCH=None TEST=FW_NAME=chronicler emerge-volteer coreboot chromeos-bootimage verify bootable with chronicler Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Id5524b97a236dcc64d18ab1cd2ce13f6bb2d998f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55340 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25mb/facebook/fbg1701/fbg1701/Kconfig: Update VBOOT key locationFrans Hendriks
Error Could not add [key.vbpubk]: too big occurs, when Eltan verified boot is enabled. Update value of VENDORCODE_ELTAN_VBOOT_KEY_LOCATION. BUG = N/A TEST = Boot Facebook FBG1701 with Eltan verified boot enabled. Change-Id: I1faecd189915985df633ac74627fd872ce8867f0 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-25mb/google/octopus: add audio codec into SSFC support for Garg/GarfourKevin Chiu
BUG=b:191213716 BRANCH=octopus TEST=adjust SSFC value of CBI to select RT5682 or DA7219 then check whether device tree is updated correspondingly by disabling unselected one. Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I2d5738442d2c173fd5b4802d8b5dff76b428c6f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55564 Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25mb/google/guybrush: Change ACPI HID for machine driverYu-Hsuan Hsu
To avoid from using same the name AMDI5682 as Zork, changing to use AMDI1019. The corresponding kernel change is on CL:2929864 BUG=b:189297564 TEST=Audio works with the corresponding kernel change. Cq-Depend: chromium:2929864 Signed-off-by: Yu-Hsuan Hsu <yuhsuan@google.com> Change-Id: Ie89302f3b6cd3edb8253b909fde4722c2ea1e102 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55508 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25mb/asus/p5q_se: Add initial supportAlice Sell
This motherboard is almost identical to the ASUS P5QL PRO, with the only noticeable difference being that the ASUS P5Q SE has a P45 MCH while the P5QL PRO has a P43 MCH. Few changes were required. Signed-off-by: Hunter Sell <alicelyralain@gmail.com> Change-Id: I36612bac16a79f05f3fe57e535e4ba3c73790a86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-25mb/google/brya: add generic LPDDR4 SPDs for GimbleMark Hsieh
Add Makefile.inc to include three generic LPDDR4 SPDs for the following parts for Gimble: DRAM Part Name DRAM ID to assign MT53E512M32D2NP-046 WT:E 0 (0000) H9HCNNNCPMMLXR-NEE 1 (0001) H9HCNNNBKMMLXR-NEE 0 (0000) BUG=b:191574298 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I60f95ac5ed7f3134882f6580335ec33632676796 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-06-25mb/google/brya/variants/gimble: set up gpioMark Hsieh
Set the GPIO configuration of gimble BUG=b:191213263 Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I667943578a2bf58cc5841564b8df5b6469d7594b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55717 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-24mb/google/trogdor: Add new vaviant mrblandZanxi Chen
New boards introduced to trogdor family. BUG=b:191800434 BRANCH=none TEST=make Change-Id: I93b74e79188bd0cc36c8b48e552230ae0d6f593a Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-06-24soc/intel/alderlake: Update mainboard_memory_init_params() argumentSubrata Banik
This patch updates mainboard_memory_init_params() function argument from FSPM_UPD to FSP_M_CONFIG. Ideally mainboard_memory_init_params() function don't need to override anything other than FSP_M_CONFIG UPDs hence passing config block alone rather passing entire FSP-M UPD structure. Change-Id: I238870478a1427918abf888d71ba9c9fa80d3427 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-24mb/google/guybrush: configure eSPI mux on psp_verstageKangheui Won
Temporarily set eSPI mux in verstage_mainboard_early_init. Ideally cezanne code should have common function to do this and mb-specific code would just call it, but for now PCI access doesn't work in the PSP so we can't do it. AMD team confirmed that the current PSP doesn't configure LPC so we don't have to disable LPC when configuring eSPI mux so we can temporarliy skip the LPC part here. BUG=b:183149183 TEST=boot guybrush with psp_verstage Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I8317409fa5efd1adffc184d75affbb4d305183f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-06-24mb/google/cherry: Implement regulator interfaceRex-BC Chen
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Iab58edd019ccf9130e96fae55f147ab20cd0f45b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55751 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-24mb/google/cherry: Initialize DPM in romstageRyan Chuang
Add initialization of DPM drvier used by DRAM calibration test. Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: I8bd10864267dfa4db8528d40483eccee2d05c1d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-06-24mb/google/cherry: Add mt6360 driver for PMIC accessRyan Chuang
Add initialization of mt6360 drvier used by DRAM calibration test. Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: Id74835d8395afac9e7e2c987a0a033f1b524fbfb Reviewed-on: https://review.coreboot.org/c/coreboot/+/55750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-06-23mb/google/guybrush: Indicate the presence of ACP DMICKarthikeyan Ramasubramanian
In order to enable ACP DMIC hardware runtime detection, indicate that ACP DMIC is present. BUG=b:182960979 TEST=Build and boot to OS in guybrush. Ensure that the _WOV ACPI method is populated in the ACP device. Change-Id: I9a53d158ed08a6b46c29bcb8fe3a2a0d108bd6cd Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55030 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23mb/google/guybrush: Add guybrush specific AMDFW config fileMartin Roth
This takes the "generic" AMD firmware config file from the cezanne directory and removes pieces unnecessary for guybrush. Removed: - PSPTRUSTLETS_FILE TypeId0x0C_FtpmDrv_CZN.csbin - PSP_MP2FW0_FILE TypeId0x25_Mp2Fw_CZN.sbin - PSP_KVM_ENGINE_DUMMY_FILE TypeId0x29_KvmEngineDummy.csbin - DRTMTA_FILE TypeId0x47_DrtmTA_CZN.sbin - PSP_MP2CFG_FILE MP2FWConfig.sbin BUG=b:187103438 TEST=Build & Boot Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I5a0ed1edd7616a890f906b7f3e4a7d364758ca47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-23mb/google/dedede/var/magolor: Enable weida touchscreen for magisterDavid Wu
Add weida touchscreen support for magister. BUG=b:191633024 BRANCH=dedede TEST=Build and verify that touchscreen works on magister. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I3de6a84d2d58ef87f0ae13e8a117a980a0210ac4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Randy Lai <randy.lai@weida.corp-partner.google.com>
2021-06-23mb/google/dedede/var/sasukette: Change ELAN touchpad driverZhi Li
Use drivers/i2c/hid can't update firmware by kernel update script, so change to drivers/i2c/generic. BUG=b:188602529 BRANCH=dedede TEST=can update ELAN touchpad firmware(277.0_1.0) by kernel script Change-Id: I3592403fe5d0f8d0f67059f8296277e3c028c117 Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55248 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23mb/{fb/fbg1701,portwell/m107}: Don't select HAVE_FSP_BINArthur Heymans
This selected by default if 3rdparty/fsp is used. There is no need to override this behavior in the mainboard Kconfig. Change-Id: I01ee2e90e0eceaa3100d911b5460cf99f413b185 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-06-23mb/facebook/fbg1701/Kconfig: Correct dependencyFrans Hendriks
Config items depends on USE_VENDORCODE_ELTAN but are VBOOT specific. Correct dependency of these items on VENDORCODE_ELTAN_VBOOT. BUG = NA TEST = Boot facebook FBG-1701 with possible combinations of Eltan security. Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Change-Id: Icd1c3e5c70ca562190308752f45aac734826649a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52132 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23mb/intel/sm: Skip FSP to program UART0Subrata Banik
Set "SerialIoUartMode" for UART0 as PchSerialIoSkipInit Change-Id: Idc7da7bf38634c04b0f4acd4c7c2ea9fa88545e5 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55207 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-22mb/google/guybrush: Only enable early port80s if using psp_verstageMartin Roth
PSP_Verstage will enable eSPI early in the boot sequence. If the platform isn't using psp_verstage, the system can hang on the first port 80h postcode that comes out because they aren't routed to an active device until eSPI is configured. BUG=b:191370340 TEST=Build without PSP_Verstage, verify system doesn't hang. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I37fbb251cd79609b856c4480ca29ce94b08897d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55738 Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-22mb/intel/adlrvp: Update Mainboard part number and VendorMeera Ravindranath
dmidecode output should match with the CrOS kernel updated string. TEST=dmidecode grep "Manufacturer" = Intel Corporation dmidecode grep "Product name" = Alder Lake Client Platform Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I7cce423de624e7056e88b52a1443c554fd9123bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/51408 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-22mb/google/brya/variants/primus: set up gpioMalik_Hsu
Set the GPIO configuration of primus BUG=b:190643562 Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I405561ae8a44d95ffdc526241f9c52761f67ed35 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-22mb/asus/p8h61-m_pro_cm6630: Add initial supportAlice Sell
This motherboard is somewhat similar to the p8h61-m_pro, but also different. It has two exposed RAM slots with a pinout for four, and it's an OEM variant used in PCs ASUS sold in stores. Signed-off-by: Hunter Sell <alicelyralain@gmail.com> Change-Id: Id08349feb0aeaf21406f814f6d19bbe0d9312a4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/55661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-22mb/lenovo/t440p: Disable second PEG deviceAngel Pons
PEG bifurcation is strapped to x8/x8 on this board, but only the first port is used. Disable the PEG device at 00:01.1 because it is unused. Should fix booting with commit ae999503f62ef8a3b9b2756a2810d29c383a009e (nb/intel/haswell/pcie.c: Add missing pre-ASPM init). The `config_of()` function call added in that commit makes coreboot die if any PEG device that is enabled by strapping is not present in the devicetree. While it is true that the PEG code should not use `config_of()`, this PEG device should still be disabled on this board as it is never used. Change-Id: I16809e081f9a56ba2f1fdfcb4b8289d75161056b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Máté Kukri <kukri.mate@gmail.com>
2021-06-22mb/lenovo/t440p/devicetree.cb: Visually align devicesAngel Pons
Visually align devices and corresponding comments in the devicetree. Tested with BUILD_TIMELESS=1, Lenovo T440p remains identical. Change-Id: Id6f521275ffd0b35c247152dc9293c4182c4a96d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-06-22mb/lenovo/t440p: Drop redundancy in devtree commentsAngel Pons
Remove some redundant parts of devicetree comments. This used to happen when using autoport, but has been fixed at some point. Tested with BUILD_TIMELESS=1, Lenovo T440p remains identical. Change-Id: Ie24b5430c7771c9ce4dda6c9a10d70ee9000df7c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-06-22drivers/i2c: sx9310: fix overridetree.cbGwendal Grignou
An error in script did not set the attribute properly: - Entry CS0 is not used as sensor, but as ground, - Entry CS1 is used as the startup sensor. This fixes a regression caused by commit 689c25b9d6 (drivers/i2c: sx9310: Replace register map with descriptive names) EQ=b:173341604 BRANCH=volteer Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Change-Id: I92c01209031e9a917d95b1cb2537b0ce7b93e66d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51893 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-21mb/google/dedede/var/storo: Update DPTF parametersTao Xia
Update DPTF parameters from internal thermal team. BUG=b:180875582 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: Ica2f2856000c8dcbf4d23b7b4a3c479dc7d4862b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-06-21mb/google/guybrush: Add devfn macros for devices on GPP bridgeKarthikeyan Ramasubramanian
Add devfn macros for some peripheral devices that are attached to PCIE GPP Bridge. BUG=None TEST=Build and boot to OS in Guybrush. Change-Id: I7c5433dff2329f13c282908e2b848405819347ff Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-21mb/google/dedede/var/blipper: Configure Acoustic noise mitigation UPDsZanxi Chen
Enable Acoustic noise mitigation for blipper and set slew rate to 1/8 which is calibrated value for the board. BUG=b:187760191 BRANCH=dedede TEST=build firmware to UPD and Acoustic noise test Change-Id: I187702c23712416eaaaaf1e210dcfc6b2c560041 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-21mb/purism/librem_mini/hda_verb.c: Fix subsystem, jack detectMatt DeVillier
- set subsystem/subvendor ID to Realtek default, as the one dumped from the vendor UEFI firmware provides no advantages - Add a codec reset before setting the subvendor ID using the Azalia macro for consistency with all other Realtek HDA codecs - disable jack detect for the external mic on the 3.5mm jack, since it's not currently working, so that the external microphone can be manually selected Change-Id: Ib0f99e5088973a721c0a295899012c9aea5009cf Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-21mb/purism/librem_14/hda_verb.c: Fix subsystem, verb count, jack detectMatt DeVillier
- set subsystem/subvendor ID to Realtek default, as the one dumped from the vendor UEFI firmware provides no advantages - fix the number of verb entries, which excluded the 4 following the pin configs - issue the reset *before* setting the subvendor, and use the Azalia macro - disable jack detect for the 3.5mm jack, both line out and mic, since it's not currently working, so that the outputs can be manually selected Change-Id: Icd961c3c5aec23cf61d6a9ad65c603c6dc04697a Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-21mb/purism/librem_mini: Enable acoustic noise mitigationMatt DeVillier
Enable FastPkgCRampDisable for all domains, set SlowSlewRate to fast/16 for all domains. This aligns the settings with the Librem 14. Test: boot Librem Mini v2, observe high frequency acoustic noise reduced. Change-Id: I10bc2a3e6b631b8c0b430e204f376aa9a81ac683 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-21mb/purism/librem_14: set SA slew rate to fast/16Matt DeVillier
Decrease SA slew rate to match other domains and reduce high-frequency noise slightly. Change-Id: I02cd93481f6bfba6249cb338a0e2f47d471a438e Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-21mb/guybrush: Probe FW_CONFIG for FP_PRESENTRob Barnes
Only enable fingerprint device when FP=FP_PRESENT in FW_CONFIG. BUG=b:186685292 TEST=Boot guybrush, no "EC failed to respond in time" error Change-Id: Ifaea9e23e6cdfdae024464ff36c1520b8ad05e50 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-19mb/google/dedede: Configure CBI EEPROM WPAseda Aboagye
On dedede boards without Cr50, the CrOS Board Info (CBI) EEPROM write protect signal is decoupled from the hardware write protect signal. Instead, we'd like for it to mirror the software write protect status. This commit simply checks the software write protect status of the SPI flash and sets the CBI EEPROM write protect if it's enabled. To prevent changing the WP signal at run-time, the GPIO configuration is also locked down after the level has been set. If HW WP is deasserted, the CBI EEPROM WP will be deasserted as well. BUG=b:191189275,b:184592299 BRANCH=None TEST=Build and flash lalala, disable SW WP by running `flashrom -p host --wp-disable` from a root shell and verify that the GPIO is asserted after a reboot. Export the gpio via sysfs and verify that attempting to change the value of the GPIO is futile. Enable SW WP via `flashrom -p host --wp-enable` and reboot the DUT. Again, export the GPIO via sysfs and verify that attempts to change the GPIO value are futile. localhost ~ # iotools mem_read32 0xfd6e08d0 0x44000200 localhost ~ # cd /sys/class/gpio/ localhost /sys/class/gpio # echo 217 > export localhost /sys/class/gpio # cd gpio217/ localhost /sys/class/gpio/gpio217 # echo out > direction localhost /sys/class/gpio/gpio217 # cat value 0 localhost /sys/class/gpio/gpio217 # echo 1 > value localhost /sys/class/gpio/gpio217 # cat value 1 localhost /sys/class/gpio/gpio217 # iotools mem_read32 0xfd6e08d0 0x44000200 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: Ic103037921ec7d2f96f86178675c11a3a1357d1b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-18mb/google/cherry: enable display supportJitao Shi
To enable display, we have to: 1. Configure panel power and backlight 2. Configure eDP driver BUG=b:189985956 Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Change-Id: Ida6c157a6a3bd904d3fa3dd2001385ced34f7711 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55574 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18mb/intel/ehlcrb: Change default romsize and remove chromeos.fmdLean Sheng Tan
Change the default rom size to 32MB and remove chromeos.fmd because Chrome OS is not supported on EHL for now. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I49d9404eb901087037b5423a4a503c5271e14138 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55554 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18mb/google/bry: remove GSC option as it's not usedYH Lin
BUG=None BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: I932178dc395a4a96682a2e2076131feb3342aa52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55597 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18google/trogdor: change board ID detect to tristate solution.Sheng-Liang Pan
change binary board ID to tri-state mode. BUG=b:190250108 BRANCH=None TEST=emerge-trogdor coreboot Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I79d1212abc227341be126969ef32e76a635cbdaf Reviewed-on: https://review.coreboot.org/c/coreboot/+/55563 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17mb/intel/adlrvp_m: Remove DP_HPD 1 & 2 definition from devicetreeBernardo Perez Priego
Due to latest corresponding UPD filling implementation, this is not required. This patch fixed the brokenness caused by Commit hash b10afbd2e2a8326fb21dc726a6c2bd53b06eb010. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I49e434f7bbafcb148e82202697e87c3e4268d7b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-17mb/google/guybrush: Add helpers for cbi fw_config settingsMartin Roth
Turn on CBI and add helper functions for determining the board configuration from the firmware config settings in CBI. BUG=b:187316460 TEST=Built Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I212e7f413b4d8a7d15122cde90100a0ec28e88a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54639 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17mb/google/brya/brya0: Update GPIO tables based on new board revTim Wawrzynczak
This change also restores GPIOs to their proper settings for prior board revs. BUG=b:189362981 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I89d7ba94dfbd5e4a000cdde7a0c65f38b53b722d Reviewed-on: https://review.coreboot.org/c/coreboot/+/55325 Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17mb/intel/adlrvp_m: Configure DP_HPD as PAD_NC and disable DdiPortHpdBernardo Perez Priego
GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function (NF1), this causes redundancy with legacy HPD interruption. This change configures GPP_A19 and GPP_A20 to be no connection and disables DdiPort1Hpd and DdiPort2Hpd. BUG=None TEST=Boot to kernel and verified no kernel HPD pins assertion message. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I80ef40a1aca19cd6ad56219175d2fd40890a393d Reviewed-on: https://review.coreboot.org/c/coreboot/+/55548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sanrio Alvares <sanrio.alvares@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2021-06-17mb/google/dedede/var/kracko: Configure I2C high and low timesTony Huang
Configure I2C high / low time in device tree to ensure I2C CLK runs under I2C_SPEED_FAST (400 kHz). Touchpad: 387.7kHz Touchscreen: 389.4kHz Audio: 387.6kHz P-sensor: 372.5kHz BaUG=b:178092096 BRANCH=dedede TEST=Build and EE check after tuning I2C clock is under 400kHz Change-Id: I4f6bdd3802cd94671325a89458cde981a2ffa929 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-17mb/google/cherry: fix GPIO polarity for TPM interruptRex-BC Chen
The GPIO_GSC_AP_INT itself is active low, but the payloads will create the IRQ using its eint driver, which is active high. BUG=b:188392736 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ie39f3b9a5dbe15057ef3e96f6c99211949692003 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-06-17mb/google/cherry: Add display configurationRex-BC Chen
BUG=b:189985956 Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com> Change-Id: I2b68f6342e7d46d90ea0e7aef9a01ecfd35f8fa9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-06-17mb/lenovo/x230: Fix overridetrees not overridingAngel Pons
Any chip entry without a device node below them are silently dropped by sconfig. Copy the same device node from the devicetree to prevent this. Change-Id: I778f6b2d980e78142ae12ef941e7d9bd1f753057 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55540 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17nb/intel/ironlake: Factor out common uncore ASLAngel Pons
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I7e37d32251fa3dcc64aec62dd2d814463c4a9999 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55580 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17soc/amd/picasso: introduce and use devicetree aliases for UART0-3Felix Held
Since the default state of the MMIO UART devices in the chipset devicetree is off, the mainboard devicetree entries that disable MMIO UART devices are removed. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I913a587802020ce4e182b48632cdde1104c2a6e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55545 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17mb/google/dedede: Create cappy variantZhi Li
Create the cappy variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:190515828 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_CAPPY Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com> Change-Id: Id5a3b0cb475ee77a9f62523d8322a5e4123ce3be Reviewed-on: https://review.coreboot.org/c/coreboot/+/55451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-17mb/google/dedede/var/pirika: Add camera supportAlex1 Kao
Add camera support in devicetree. BUG=b:190797339 BRANCH=None. TEST=built pirika firmware and verified camera function is OK. Change-Id: I66ded32105f3166e2faec3ea5dcfb93c29822366 Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55450 Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17mb/google/brya: Configure WWAN GPIO earlyVarshit Pandya
In order to meet timing requirement of WWAN reseting it in early GPIOs and asserting Reset GPIO in ramstage BUG=b:180166408 TEST=Build and boot Brya system and verify enumeration of L850 and FM350 devices Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com> Change-Id: Id6d69696b6c645eec3fa314a608c69214bafba82 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54912 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17mb/*: Fix some indirect includesKyösti Mälkki
Fix build failures in the case <vc/.../chromeos.h> is removed. Change-Id: Ie45066f39cd6fb92cca697a6bd5bc8bb8c60b4e7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-16arch/x86/ioapic: Drop irq_on_fsb as a configurable itemKyösti Mälkki
APIC Serial Bus pins were removed with ICH5 already, so a choice 'irq_on_fsb = 0' would not take effect. The related register BOOT_CONFIG 0x3 is also not documented since ICH5. For emulation/qemu-q35 with ICH9 the choice INTERRUPT_ON_APIC_BUS was wrong and ignored as BOOT_CONFIG register emulation was never implemented. For ICH4 and earlier, the choice to use FSB can be made based on the installed CPU model but this is now just hardwired to match P4 CPUs of aopen/dxplplusu. For sb/intel/i82371eb register BOOT_CONFIG 0x3 is also not defined and the only possible operation mode there is APIC Serial Bus, which requires no configuration. Change-Id: Id433e0e67cb83b44a3041250481f307b2ed1ad18 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55257 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-16mb/google/zork: enable UART0 in devicetreeFelix Held
This a mainly a preparation for adding the MMIO UART devices to the chipset devicetree. TEST=none Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I533e4a909fdeb1614dbc5df015440b9df5d83233 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-16soc/amd/picasso: introduce and use devicetree aliases for I2C2&I2C3Felix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I06102f4fcc3bf9de332c71a52c632241b95cde19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-16mb/prodrive/hermes: Use serial numbers from BMCAngel Pons
The BMC EEPROM layout has been updated to contain system and mainboard serial numbers. Use these values in SMBIOS Type 1 and Type 2 tables. Change-Id: I55b51a856b4ad28fd56b02015b2e1d49cd629735 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55275 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-16broadwell boards: Use Haswell hostbridge.aslAngel Pons
Use hostbridge.asl from Haswell instead of Broadwell. Both files are equivalent. Then, drop the now-unused hostbridge.asl from Broadwell. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I87d51727b75a9c59e2f5f3ba8d48c575ce93c78c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-16mb/asus/p8x7x-series: Add P8H77-V as a variant of P8X7X seriesBill XIE
Mainboard information can be found in the included documentation. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: Ic811e24bd72da84e5ca8f5b09f2eb65872153b72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55111 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-16soc/intel/alderlake/romstage: Update display UPDs based on InternalGfxSubrata Banik
Disable all display related UPDs if IGD is not enabled as FSP don't need to perform display port initialization while IGD itself is disabled else assign UPDs based on devicetree config. TEST=Dump FSP-M display related UPDs with IGD enable and disable to ensure patch integrity. Change-Id: I0479904141dfc5e707679109aa18b7ef4264cf96 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-15mb/lenovo/w541: Add ThinkPad W541Amersel
Add support for the ThinkPad W541 based on Peter Lemenkov's initial W541 port. Compiled and tested with SeaBIOS and Tianocore booting into Arch Linux 5.10.32-lts. The Haswell mrc.bin blob is required. Tested working: - SATA SSD - SATA DVD drive - M.2 SATA - All USB ports - SD card reader - Speakers/headphone jack - Keyboard/touchpad - libgfxinit - VGA - mini DisplayPort (Thunderbolt untested) - eDP laptop screen - NVIDIA GPU in Linux - Camera/Mic - Smartcard reader - Internal flashing when IFD is unlocked - ThinkPad basic dock (VGA, USB, Ethernet) - CMOS options - WLAN - Bluetooth - Ethernet - Using me_cleaner - All DDR3 slots Not working: - Keyboard backlight - First boot can take up to 20s (MRC.bin is slow) Untested: - Thunderbolt - Internal flashing when IFD is locked - Other ThinkPad docks (DisplayPort, DVI, Audio) - ExpressCard slot - Battery thresholds - WWAN card - Fingerprint reader - USB Debug console Signed-off-by: Justin Wu <amersel@runbox.me> Change-Id: Ia43070f51bba3cf59ba9b7d9e29e4e778efbeb08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52659 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-14mb/google/volteer/var/collis: change GPP_B2 to PLTRSTNick Vaccaro
Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang. BUG=b:174776411 BRANCH=none TEST=none Change-Id: I18ee085cde0570ef278ea3869be30471ed04e3db Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-14mb/google/volteer/var/eldrid: change GPP_B2 to PLTRSTNick Vaccaro
Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang. BUG=b:174776411 BRANCH=none TEST=none Change-Id: Icfde6b57ff5f6e49ff7804eff6e6a5819bb784bc Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-14mb/google/volteer/var/volet: change GPP_B2 to PLTRSTNick Vaccaro
Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang. BUG=b:174776411 BRANCH=none TEST=none Change-Id: Ib0858afa1b5dc9de9db87485d3e0bf6032416746 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-14mb/google/volteer/var/elemi: change GPP_B2 to PLTRSTNick Vaccaro
Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang. BUG=b:174776411 BRANCH=none TEST=none Change-Id: I19b5e1c4beebbc1ebd3d2e30bc22e8c890aaf78f Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-14mb/google/volteer/var/copano: change GPP_B2 to PLTRSTNick Vaccaro
Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang. BUG=b:174776411 BRANCH=none TEST=none Change-Id: I7d35c284b88b8828d31fff9ccafeb914542b0837 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-14mb/google/volteer/var/voema: change GPP_B2 to PLTRSTNick Vaccaro
Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang. Add GPP_B2 to the early_gpio_table. BUG=b:174776411 BRANCH=none TEST=none Change-Id: If8c253236051f6d170fab444cfc166e5d2ed7bc2 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-14mb/google/volteer/var/drobit: change GPP_B2 to PLTRSTNick Vaccaro
Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang. Add GPP_B2 to the early_gpio_table. BUG=b:174776411 BRANCH=none TEST=none Change-Id: I49f7b1b69c3c3ab5593c7230d8f631a3b54c9c9d Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-14mb/google/volteer/var/terrador: change GPP_B2 to PLTRSTNick Vaccaro
Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang. Add GPP_B2 to the early_gpio_table. BUG=b:174776411 BRANCH=none TEST=none Change-Id: I1214246bb1318869e9b6f57cb6a7e74bbe6574cc Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-14mb/google/volteer/var/delbin: change GPP_B2 to PLTRSTNick Vaccaro
Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang. Add GPP_B2 to the early_gpio_table. BUG=b:174776411 BRANCH=none TEST=none Change-Id: Ifb6b5b14cec9e6f7c68aa9b01621fdb21c885552 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-14mb/google/volteer/var/volteer2: change GPP_B2 to PLTRSTNick Vaccaro
Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang. Add GPP_B2 to the early_gpio_table. BUG=b:174776411 BRANCH=none TEST=none Change-Id: I07be950096aef42dbf4f067134e56c5849dfa02d Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-14mb/google/volteer/var/voxel: change GPP_B2 to PLTRSTNick Vaccaro
Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang. BUG=b:174776411 BRANCH=none TEST=none Change-Id: Ia7db2d0a1fff98d1cfb8e7e979c0a81b9f3d0e9e Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-14mb/google/volteer/var/baseboard: change GPP_A11 to PLTRSTNick Vaccaro
The system will hang when resuming from S3 if the SSD reset gpio is not reset early enough. Change GPP_A11 in baseboard to PLTRST to avoid an S3 resume hang. BUG=b:174776411 BRANCH=none TEST=none Change-Id: Ia78d813cb6bc689b07e8d8ead1ade6e77f925ce1 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-18 22:37:55 +0000