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2020-12-02mb/google/dedede: Add Daughter-board FW_CONFIG in devicetreeKarthikeyan Ramasubramanian
Add daughter-board ports bit field and mask in devicetree. BUG=b:161190931 BRANCH=dedede TEST=Build and boot to OS in drawlat & drawman. Change-Id: Ibbd86fc8c3e44a7d1703b8ce75c48881226545c9 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-12-02mb/google/zork: Update SPD table for ShubozKane Chen
Add memory table to "mem_parts_used.txt", and command to generate files: go build gen_part_id.go ./gen_part_id ../../../src/mainboard/google/zork/spd ../../../src/mainboard/google/zork/variants/shuboz/spd/ ../../../src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt Shuboz memory table as follow: value Vendor Part number 0x00 MICRON MT40A512M16TB-062E:J 0x01 HYNIX H5AN8G6NCJR-XNC 0x02 MICRON MT40A1G16KD-062E:E 0x03 SAMSUNG K4AAG165WA-BCWE BUG=b:174528384 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I5f5f875daab58343f1cc8a9327ea128ba5e1f050 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2020-12-02mb/google/dedede/var/lantis: Configure IRQs as level triggered for HID over I2CTony Huang
Config HID-I2C device to level trigger. As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:171546871 TEST=emerge-dedede coreboot Change-Id: If8be25f591715765a99920b79482c862b1cc7079 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-01mb/intel/jslrvp: Modify the flash layout for fsp debug buildV Sowmya
Current flash layout doesn't support the fsp debug builds since the FW_MAIN_A/B doesn't have enough space to hold the fsp debug binaries along with ME RW binaries. This patch reduces the SI_ALL size to 3.5MiB and increase the SI_BIOS to 12.5MiB to include both ME RW and FSP debug binaries. BRANCH=dedede TEST=Build and Boot jslrvp with fsp debug enabled coreboot. Cq-Depend: chrome-internal:3425366 Change-Id: I6f6354b0c80791f626c09dabafe33eefccedb9c2 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-12-01mb/google/zork: Mark RW_MRC_CACHE as "Preserve"Martin Roth
AGESA checks to make sure that the firmware version reading the MRC cache is the same version that wrote it, so it doesn't need to be erased during a firmware update. BUG=b:173724014 TEST=Flash firmware to DUT, update firmware, check RW_MRC_CACHE was not erased BRANCH=Zork Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ice3d1d467c25366b7ef678cd6481d043f62644ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/47776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-01mb/kontron/mal10: Use the system library for headersFelix Singer
Use the system library for header files instead of relative filesystem paths. Built with BUILD_TIMELESS=1, coreboot.rom remains the same. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: I0b356d0188f104d7c49571ce5c8fe65e79589123 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-12-01mb/kontron/mal10/Kconfig: Reorder selects alphabeticallyFelix Singer
Built with BUILD_TIMELESS=1, coreboot.rom remains the same. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: Id78c478a1252099cd1aa42c62efd406e7e1c5ef8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-12-01mb/ocp/deltalake: Update SMBIOS type 8 informationTim Chu
Update port connector information for Delta Lake. Tested=Execute "dmidecode -t 8" to check all the information of SMBIOS type 8 is correct. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I880bb9a5a41077172423f78b56c19aadd93e001f Reviewed-on: https://review.coreboot.org/c/coreboot/+/47893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-01mb/intel/adlrvp: Remove unused EC_SYNC_IRQ GPIO on ADLRVPSubrata Banik
As per latest schematics GPP_A15 is not used for EC_SYNC_IRQ hence remove the unused GPIO. Wrong GPIO configuration is causing platform reboot issue on ADLRVP with Chrome SKU. Change-Id: I704cd722683258c80197d8872d3bdaafb7c923dc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-12-01mb/intel/adlrvp: Add ASL support for WFC annd UFCVarshit Pandya
1. Add 2 ports and 2 endpoints 2. Add support for OVTI5675 WFC Cam is on I2C5 and UFC is on I2C1 BUG=None BRANCH=None TEST=Build and Boot adlrvp board and able to capture image using camera. Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com> Change-Id: I6d2a4fdca99354d1b6977233c70ccd950c99d8a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47497 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-01mb/intel/adlrvp: Configure Camera related GPIO as per schematicsVarshit Pandya
Configure RST and PWR_EN signals for both WFC and UFC Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com> Change-Id: Ie416da373756b1c73472b8572f87930965a3d6ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/47496 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-01mb/intel/adlrvp: Update GPIO configuration as per schematicsVarshit Pandya
Configure I2C related GPIO as per ADL-P schematics. This is based on Revision 0.974 of schematics. Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com> Change-Id: I76e1207cb31bed10b6e9fbeb2456b6feec42f97e Reviewed-on: https://review.coreboot.org/c/coreboot/+/47495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-12-01mainboard/intel/adlrvp: Enable PCH PCIe device over x1 slotSubrata Banik
List of changes: 1. Enable Root Port 8 aka 0:0x1c:7 2. Assign free running clock for RP8 3. Apply W/A to get card detected on x1 slot - Drive OEB 7:GPP_A7 and OEB 6:GPP_E5 low TEST=Able to detect PCIe SD card over x1 slot localhost ~ # dmesg | grep mmc [ 3.643755] mmc0: SDHCI controller on PCI [0000:02:00.0] using ADMA [ 3.825201] mmc0: new ultra high speed DDR50 SDHC card at address 17f8 [ 3.835452] mmcblk0: mmc0:17f8 SE16G 14.4 GiB [ 3.849158] mmcblk0: p1 Change-Id: Ibea37b8de4dd020ff0108ec90ea6f8bcfaa4fb17 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48080 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-01mainboard/intel/adlrvp/spd: Update SPD for LP4x SKUSubrata Banik
List of changes in SPD: 1. SPD Revision (of JEDEC spec) 2. SDRAM Maximum Cycle Time (tCKAVGmax) (MTB) 3. MSB -> CAS Latencies Supported, First Byte 4. CAS Latencies Supported, Second Byte 5. CAS Latencies Supported, Third Byte 6. LSB -> CAS Latencies Supported, Fourth Byte 7. Minimum CAS Latency Time (tAAmin) 8. Fine Offset for SDRAM Maximum Cycle Time (tCKAVGmax) 9. Fine Offset for SDRAM Minimum Cycle Time (tCKAVGmin) 10.Cyclical Redundancy Code (0- 125 byte) TEST=Able to build and boot with updated SPD. Change-Id: Iae7f2693e87bffb2dfa20bd07b22f4a4768c56cb Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-12-01mb/intel/adlrvp: Add support for LPDDR5Sridhar Siricilla
This patch adds LPDDR5 memory configuration parameters to FSP. TEST=Able to pass FSP-M MRC training on LPDDR5 RVP. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I787bf97dd6c244bd3b0662e5bd061a2da80baa90 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-12-01mb/intel/adlrvp: Refactor lpddr4_mem_config structureSubrata Banik
List of changes: 1. Initialize dq_map array in a single line 2. Make dqs_map array also in a single line TEST=Able to build and boot ADLRVP LP4 SKU. Change-Id: I64f2b38492934c8ede301f4b252c8700060ed4ac Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48077 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30mb/siemens/chili: Configure GPIOs in gpio.cFelix Singer
Get rid of variant_gpio_table() and configure GPIOs in gpio.c instead of passing data around. Change-Id: Ib158d6bdbcbceb3c1dc4f47fc7c3e098b9c7e5c4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47974 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30mb/siemens/chili: Introduce include folder for header filesFelix Singer
Use include folder for header files allowing proper includes. Change-Id: I80066fb925b918d040062397e633c5d499a50dbe Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47973 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30mb/kontron/bsl6: Configure GPIOs using mainboard_opsFelix Singer
Hook up the mainboard_ops driver and configure the GPIOs using .init, since mainboard_silicon_init_params() is meant for the configuration of the FSP, not the GPIOs. Change-Id: I6ab8d258c6f81c90d835cb8d07c6387d3de76d85 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47850 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30soc/amd/picasso: remove PICASSO_LPC_IOMUX Kconfig option from SoCFelix Held
PICASSO_LPC_IOMUX was only used in the amd/mandolin board, but not in the corresponding SoC code, so remove it from the SoC's Kconfig and reanme it in the mainboard's Kconfig to MANDOLIN_LPC. Change-Id: I261e093d6c56be6073a816b79c60d3a0457616f8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-30mb/google/volteer: Create drobit variantFrank Chu
Create the drobit variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:171947885 BRANCH=none TEST=emerge-volteer coreboot Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I63b7312bba236bd5af028359804d042f6850d8ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/47787 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30mb/google/dedede: Update Imon slope and Offset Value for DrawciaMeera Ravindranath
Updating Imon slope and offset values as per recommendation of ODM based on calibaration. Updating Imon slope to 1.0 and offset to 1.4 BUG=b:167294777 BRANCH=dedede TEST=Boot dedede platform and confirm values in FSP. Change-Id: I3eb32218040163f0abef9b8dd4c52efb16289fe7 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Vinay Kumar <vinay.kumar@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2020-11-30mb/google/dedede: Create sasuke variantRaymond Chung
Create the sasuke variant of the waddledoo reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.3.1). BUG=b:172104731 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_SASUKE Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Change-Id: I29405d63fd266224807e535c3f86a2ad5ab8cdf3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: SH Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-11-30lenovo/g505s: remove the unused and not present devicesMike Banon
Remove the devices unused or not present on this laptop. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I0decad499dfbb5f1e0a189d21f0fca47c80bd490 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-30mb/google/volteer/variants/delbin: Enhance I2C5 bus freq closer 400 kHzFrank Chu
The current I2C5 bus frequency is 367 kHZ, which does not meet the spec. This change updates scl_lcnt, scl_hcnt, scl_hcnt value for I2C5 to bring the bus frequency closer to 400kHz. BUG=b:173670150 TEST=Verified that I2C5 frequency is between 386-387kHz. Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I6d60abe15645dc51ed9ee30975d2521b8940c2d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47736 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30mb/google/volteer/variant/copano: Add memory part supportNick Vaccaro
Add support for the following 5 LPDDR4x memory parts: - MT53E512M64D4NW-046 WT:E - H9HCNNNCRMBLPR-NEE - MT53D1G64D4NW-046 WT:A - H9HCNNNFBMBLPR-NEE - MT53D512M64D4NW-046 WT:F DRAM Part Name ID to assign ------------------------------------------- MT53E512M64D4NW-046 WT:E 0 (0000) H9HCNNNCRMBLPR-NEE 0 (0000) MT53D1G64D4NW-046 WT:A 1 (0001) H9HCNNNFBMBLPR-NEE 2 (0010) MT53D512M64D4NW-046 WT:F 0 (0000) BUG=b:172993397 TEST=none Change-Id: Iff8f6257c6cff77fc3f0bda7e75434f9f4de1777 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47981 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30mb/prodrive/hermes: Use PCH_DEV_SMBUS definitionAngel Pons
This allows dropping ugly preprocessor usage from this file. Change-Id: Idb66d295129d98725f38d11ac162978418bd94c2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-11-30mb/prodrive/hermes: Encapsulate GPIO setupAngel Pons
Having variants' gpio.c call the `gpio_configure_pads` function results in an API that does not need to pass data around, which is much simpler. Change-Id: I1064dc6258561bcf83f0e249d65b823368cf0d31 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-11-30mb/prodrive/hermes: Use C-style commentsAngel Pons
Most of the existing comments are C-style already. Change-Id: I9ca4779f5b0560320e9bce4f33e54766522689f9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-11-30mb/siemens/mc_apl1: Deduplicate wait_for_legacy_dev()Angel Pons
There's one copy of this function for all variants except mc_apl4. Move one copy into common mainboard.c and exit early if running on mc_apl4. Change-Id: I4e35b58adc074831ccec433b8e014db0695b955e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-11-30mb/siemens/mc_apl1: Simplify is_mac_adr_valid() logicAngel Pons
A MAC address that is neither 00:00:00:00:00:00 nor ff:ff:ff:ff:ff:ff is considered valid. Instead of using a temporary buffer and memcmp(), use a single loop that exits as soon as the MAC cannot possibly be invalid. Change-Id: I2b15b510092860fbbefd150c9060da38aeb13311 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
2020-11-30drivers/intel/i210: Define MAC_ADDR_LENAngel Pons
Define and use the MAC_ADDR_LEN macro in place of the `6` magic value. Change-Id: Icfa2ad9bca6668bea3d84b10f613d01e437ac6a2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47404 Tested-by: siemens-bot Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-11-30mb/siemens/mc_apl1/mainboard.c: Refactor loop bodyAngel Pons
Break down multi-line compound conditions into multiple if-statements, and leverage `continue` statements to avoid nesting multiple checks. Change-Id: I5edc279a57e25a0dff1a4b42f0bbc88c0659b476 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Tested-by: siemens-bot Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
2020-11-29mb/google/volteer: eldrid: use devtree aliases for PMC MUX connectorsScott Chao
Now that soc_get_pmc_mux_device() is gone, the PMC MUX connector devices can be hooked up together via devicetree aliases. BUG=b:172528109 BRANCH=firmware-volteer-13521.B TEST=built and USB3.0, type-c display work. Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: Iedf9b972b341064ff62a4443bfa83f69c8c60108 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48066 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-29mb/intel/adlrvp: Disable dq_pins_interleaved for DDR4/5 RVPSubrata Banik
TEST=Able to pass MRC training on DDR4/5 SKUs Change-Id: I38fcb17a1be5a8544a17cef8255631b6abef0741 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-29mb/supermicro/x11-lga1151-series: set FADT PM profile to ENTERPRISE_SERVERMichael Niewöhner
Set the FADT PM profile to ENTERPRISE_SERVER, since the currently supported X11 boards are server boards. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I8fb5c7c262fbd3f3c085d7c2e2ef3d6ff6ce73eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/48088 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-29mb/supermicro/x11-lga1151-series: rework gpio setup to not use headersMichael Niewöhner
Rework gpio setup for the board series to not use headers but stage-specific compilation units. Tested successfully on X11SSM-F. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Ic62ce4335af605c081ef288e892441585ff2bd3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/48087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-11-29mb/supermicro/x11-lga1151-series: switch from dev.init to mb_ops.initMichael Niewöhner
GPIO needs to be initialized before the IPMI device gets initialized, so the GPIOs can be read/set by the code in CB:48096 and CB:48094. Thus, use mainboard_ops.init for GPIO configuration instead of using the indirection via a mainboard_enable function. To make it more visible, that we use chip.init, rename `mainboard_init` to `mainboard_chip_init`. Tested successfully on X11SSM-F including the IPMI changes. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I192e69a34fa262b38bc40a95fb11c22a4041d0ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/48083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-28mb/supermicro/x11ssm-f: drop unneeded ITSS overrideMichael Niewöhner
The ITSS override is not needed for LPC_CLKOUT* pads. Drop it. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I3dbbc8944751779151dcd4f92fb870d937801d69 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48084 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-28mb/supermicro/x11-lga1151-series: configure gpios in mainboard initMichael Niewöhner
Move gpio configuration from the Fsp callback to mainboard init. Tested successfully on X11SSM-F. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: If2a54c75c5243d94cdc025c597ee347820b35d32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48086 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-28mb/supermicro/x11-lga1151-series: restructure and clean up devicetreeMichael Niewöhner
Drop zero-value devicetree options and move PcieRpEnable options down to the corresponding devices. Test: built with TIMELESS=1; binaries remain identical Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I9285d786e973621a732e2627c734adc930e54207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-27{docs/,}mb/supermicro/x11ssh-tf: drop TODO sectionMichael Niewöhner
Drop the TODO comment, since there is no TODO left. Also drop the now obsolete TODO section from the board documentation. Change-Id: I4192aaedc1429c8ff1bd7c52baa4741e1df0d0c5 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-11-25mb/google/dedede: Create galtic variantFrankChu
Create the galtic variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.3.1). BUG=b:170913840 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_GALTIC Signed-off-by: FrankChu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Ie7534d56bc67aca4484f40af1221d669addc01fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/47900 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-25mb/google/volteer: Update Eldrid USB2 port settings in overridetreeNick Chen
1. Disable M.2 WWAN and Type-A Port A1 2. Change register 4 to 3 and tuning USB2 Port1 eye diagram 3. Lower camera driving BUG=b:169105751 Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com> Change-Id: I6b8a5c0d5e814de232d79a43354f5ec0220fc5ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/47863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-25mb/ocp/deltalake: Define SMBIOS type 16 error correction type byTim Chu
RasModesEnabled Use RasModesEnabled from SystemMemoryMapHob to define SMBIOS type 16 error correction type Tested=Execute "dmidecode -t 16" to check if error correction type is correct. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I3636fcc4a874261cf484c10e2db15015ac5d7e68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2020-11-25mb/google/hatch: select SOC_INTEL_CSE_LITE_SKU only if CHROMEOSMatt DeVillier
Selecting SOC_INTEL_CSE_LITE_SKU without conditioning on CHROMEOS force-selects CHROMEOS, per src/soc/intel/common/block/cse/Kconfig. Conditioning on CHROMEOS allows for non-ChromeOS targets to be built. Test: build wyvern variant with CONFIG_CHROMEOS=n Change-Id: I61c9c78a3b02d64bab2813b7a80915b7ecf7f934 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-25mb/google/volteer/variant/lindar: change speaker smart amplifier to ALC1011Stanley Wu
Lindar change amp to ALC1011 Add ALC1011 amp acpi info to devicetree BUG=b:171771736 BRANCH=firmware-volteer-13521.B TEST=build and verify ALC1011 can be recognized. Change-Id: I4d83a19b3baa87cc926bb7c3a2cb96bf3165d2f4 Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-11-25mb/amd/mandolin: Add decode range for LPC debug cardNikolai Vyssotski
Some LPC debug boards hard strap SIO address to be at 0x164e/0x164d vs 0x4e/0x4d. Add support for configurable SIO address to support these cards. BUG=b:159933344 TEST=boot with LPC debug card, verify serial output Change-Id: I103c61f21f13970dfa3b9a788b29964e478fb84c Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-25mb/google/volteer/var/elemi: Add H5ANAG6NCJR-XNCWisley Chen
Add H5ANAG6NCJR-XNC. BUG=b:165461530 BRANCH=volteer TEST=emerge-volteer coreboot Change-Id: I827158ce0abe764f1e3b5de46abf50dc148a6ff0 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-25nb/amd: Deduplicate nb_common.hAngel Pons
Save for the IO_APIC2_ADDR definition, they are equivalent. Change-Id: I14da3d9aeefcc725428957ce0c9ac164eabacec6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47408 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-24mb/clevo/kbl-u: Configure GPIOs using mainboard_opsFelix Singer
Hook up the mainboard_ops driver and configure the GPIOs using .init, since mainboard_silicon_init_params() is meant for the configuration of the FSP, not the GPIOs. Change-Id: I82f1eaf6693d9b117fb211776047058cdc787288 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-24mb/kontron/bsl6: Move GPIO configuration to C fileFelix Singer
Change-Id: I008de1bf91ba97ee5eefbde11947c73059fff5f7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-24mb/kontron/bsl6: Use include folder for header filesFelix Singer
Change-Id: Id73a7385f7701920efebaa3e293ac50a6ba93272 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47849 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-24mb/**/cmos.layout: Drop copy-pasted `volume` entriesAngel Pons
This option only applies to boards using the Lenovo H8 EC code. Change-Id: I3b16a61a0aa9f51a4061b1b5e58fc276e7383415 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47150 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-24mb/**/cmos.layout: Drop copy-pasted SNB entries on non-SNBAngel Pons
Only Sandy Bridge MRC stores scrambler seeds in CMOS. Non-Sandybridge boards ended up with these entries because of copy-paste programming. Change-Id: I5a5bda6ea4e63ba03a4219bb2a6aa546bb6ecd7a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47149 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-24mb/google/volteer/var/voxel: Update DPTF parametersSheng-Liang Pan
update the DPTF parameters received from the thermal team. BUG=b:167523658 TEST=emerge-volteer coreboot Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Iafc3fb389ade5cfec79a816a28880262bdce7c74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47858 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-24mb/google/volteer: fw_config: Add setting for new sd readersZhuohao Lee
This patch adds three settings for the new sd readers. The new assigned values are: 1. RTS5227S: 3 2. L9750: 4 3. SD_OZ711LV2LN: 5 BUG=b:173676531 BRANCH=volteer TEST=abuild -t google/volteer Change-Id: I595695f99d3298f146fcdb7c2b942ce007ae9327 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-11-23mb/google/zork: correct USB2 phy TXVREFTUNE0 parameter nameKevin Chiu
From spec, [31:28] "HS DC Voltage Level Adjustment" is "TXVREFTUNE0". correct rx_vref_tune -> tx_vref_tune BUG=None BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I27003a952d8f8bdd8fe52af8a37010e23ee9cdfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/47735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-23mb/siemens/mc_apl1: Use `pci_or_config16` functionAngel Pons
Change-Id: I93e09fc9801f6d32cade351bac0cba82f671acfe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Tested-by: siemens-bot Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2020-11-23mb/clevo/cml-u: Get rid of gpio.h and use C files insteadFelix Singer
Split up gpio.h into two seperate compilation units, gpio.c and gpio_early.c, containing the complete configuration and a minimal configuration used in early stages. Tested on clevo/l140cu and it still boots. Change-Id: I5b056e8faac0c426a37501dbc175373c22dde339 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-23mb/clevo/cml-u: Get rid of cnl_configure_pads()Felix Singer
Get rid of cnl_configure_pads() since it is a hack for the FSP. Instead, hook up to the mainboard_ops driver and configure the GPIOs using .init. Tested on clevo/l140cu and it still boots. Change-Id: I75dd15ab6d2b3b72b3ad0398df87b349fd00bc3c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-23mb/clevo/cml-u: Move bootblock.c and ramstage.c to mb levelFelix Singer
Change-Id: Ifca49c656f259b08fb8ab47fe36e93c146f25266 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-23mb/clevo/cml-u: Use include folder for header filesFelix Singer
Change-Id: I50be3d9b829f624cbe460060c40482047f39774c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-23mb/clevo/cml-u: Move hda_verb.c to mainboard's MakefileFelix Singer
Move hda_verb.c from the variant's Makefile to the mainboard's Makefile, because every variant needs one. Change-Id: Ia94813f68620abcff48de4fdb117466c91f6863c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47820 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-23mb/**/cmos.layout: Indent everything with tabsAngel Pons
Time has shown that using spaces never converges into proper alignment. Change-Id: I5338aeaf139580f9eab3e1e02cb910080a95d2c2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-11-23mb/**/cmos.layout: Remove crusty commentsAngel Pons
Most of these comments have been copy-pasted or serve no purpose other than to eventually turn into misleading info. While the description of the first 120 bits of CMOS could be useful, it should instead be added to the documentation for the CMOS option infrastructure, or /dev/null. Moreover, trim down newlines to no more than two consecutive newlines. Change-Id: I119b248821221e68c4e31edba71ba83b7d2e14e9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-11-23mb/intel/adlrvp: Enable pre-boot display over HDMI-B portSubrata Banik
List of changes: 1. Configure CTRLCLK and CTRLDATA for HDMI 2. Enable Ddc and HPD for Port-B 3. Disable dual eDP configuration for Port-A and B TEST=Able to see depthcharge pre-boot screens over HDMI-B port. Change-Id: I7509b981f35fc60a7885b2b07067cb0d35ec625f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22mb/ocp/deltalake: Override SMBIOS type 4 cpu voltageTim Chu
Override SMBIOS type 4 cpu voltage. For Delta Lake, 1.6V is expected. Tested=Execute "dmidecode -t 4" to check if cpu voltage is correct. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I0ecbec8fb3dc79b8c3f3581d6193aade01bcd68e Reviewed-on: https://review.coreboot.org/c/coreboot/+/47562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2020-11-22mb/google/puff/var/dooly: update USB2 type-c strengthTony Huang
Based on USB DB report. BRANCH=puff BUG=b:163561808 TEST=build and measure by EE team. Change-Id: I379987b6d6d2a7aef33d4c42e589dc52d40205a3 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2020-11-22mb/google/volteer: Remove unused devices for terrador and todorDavid Wu
Remove the following devices - Goodix Touchscreen - SAR0 Proximity Sensor BUG=b:173480406 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I6b56ca136533b53ff7e003a665be67fbe12c1ade Reviewed-on: https://review.coreboot.org/c/coreboot/+/47690 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22mb/facebook/fbg1701/Kconfig: Add dependencyFrans Hendriks
VENDORCODE_ELTAN items are only used when USE_VENDORCODE_ELTAN is enabled. Add dependency of USE_VENDORCODE_ELTAN. Change-Id: Ibcc40014930c90e29904661f5ffa41bc688d368b Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22mb/google/octopus: fix droid lte sku load specific wifi sar valueSheng-Liang Pan
This CL add droid lte sku 37 38 39 40 to load wifi_sar-droid.hex. BUG=none BRANCH=octopus TEST=emerge-octopus coreboot Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I55dda85b8f3e664d97834b712a2c6a48d1434010 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47697 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22mb/google/volteer/var/voema: Update gpio and devicetree settingsDavid Wu
Based on latest schematic and gpio table of voema, update gpio and devicetree settings for voema Proto. BUG=b:169356808 TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I719a9948ed0d60e1de5368e096ff60c2345803b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-22mb/facebook/fbg1701: Add VBOOT supportFrans Hendriks
Add VBOOT support. Disable USE_VENDOR_ELTAN when VBOOT is enabled. Add FMD file and split binary into RW and RO region settings. Tested on Facebook FBG1701 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Change-Id: I641bca58c0f7c81d5742235c8b2c184d13c00c55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-11-22mb/kontron: Add Kontron mAL10 COMe module supportMaxim Polyakov
This patch adds support for the Kontron mAL10 COMe module with the Apollo Lake SoC together with Kontron T10-TNI carrierboard. Working: - UART console and I2C on Kontron kempld; - USB2/3 - Ethernet controller - eMMC - SATA - PCIe ports - IGD/DP - SMBus - HWM Not tested: - IGD/LVDS - SDIO TODO: - HDA (codec IDT 92HD73C1X5, currently disabled) Tested payloads: - SeaBIOS - Tianocore, UEFIPayload - without video, EFI-shell in console only Tested on COMe module with Intel Atom x5-E3940 processor (4 Core, 1.6/1.8GHz, 9.5W TDP). Xubuntu 18.04.2 was used as a bootable OS (5.0.0-32-generic linux kernel) Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22mb/google/sarien: Configure IRQs as level triggered for HID over I2CKarthikeyan Ramasubramanian
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: I27c485c9c8c5d47a44fc050d8cf12c553bffd01e Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-22mb/google/brya: Add new google brya mainboardTim Wawrzynczak
This commit is a stub for brya, which is a an Intel Alder Lake-P reference platform. BUG=b:173562731 TEST=util/abuild/abuild -p none -t google/brya -a -c max Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia34130ff92a0a07063cb8e80527204b3a80184a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47819 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-11-22mb/*: Use ACPI_DSDT_REV_2 instead of hard-coded valueFelix Singer
Change-Id: I6c5b86c348386aa17ee42bdaf34aa388fe6207f9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-22mb/google/zork: update berknip CHTC thermal settingKevin Chiu
Update APU CHTC thermal temperature protection point: Temperature limit(C'): 90 Update system config=2 to meet TDP 15W design. BUG=b:162377903 BRANCH=zork TEST=1. emerge-zork coreboot 2. check CHTC temperature by AMD utility Change-Id: I03245a824d838c2d9468ae0fa3cfa34389560e9d Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-21mb/google/asurada: Get RAM code from ADC 3Yidi Lin
On Chromebooks the RAM code is implemented by the resistor straps that we can read and decode from ADC. For Asurada the RAM code can be read from ADC channel 3. Signed-off-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Iaadabea1b6aa91c48b137f7c6784ab7ee0adc473 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-21zork: Create gumboz variantKevin Chiu
Create the gumboz variant of the dalboz reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:173536689 BRANCH=zork TEST=util/abuild/abuild -p none -t google/zork -x -a make sure the build includes GOOGLE_GUMBOZ Change-Id: I48db7eba7864c18e7307b45fe9f84073bfca0155 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2020-11-21mb/google/zork: update DRAM table for dirinbozKevin Chiu
Add Hynix DDR4 DRAM, index was generated by gen_part_id H5ANAG6NCJR-XNC BUG=b:173480390 BRANCH=zork TEST=emerge-zork coreboot Change-Id: Ib6f26a7b8d014493f4a256b328bee7ad3bf3c2b9 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2020-11-21util: Add new DDR4 H5ANAG6NCJR-XNC for zork boardsKevin Chiu
Add DDR4 part H5ANAG6NDMR-XNC. Attributes are derived from data sheets. BUG=None TEST=Compared generated SPD with data sheets and checked in SPD Change-Id: I324aefbce1b138a2f71aad3173d6a138cf7fa510 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2020-11-21mb/google/zork: update telemetry settings for WoomaxKane Chen
Update Woomax to improve the performance. BUG=b:168073070 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I2703d15f1fbe715ab1c684274d9e4e0bb55ef23b Reviewed-on: https://review.coreboot.org/c/coreboot/+/47743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-20mb/google/dedede/variants/madoo: Increase TCC offset from 5 to 10John Su
Increase TCC offset value from 5 to 10 for Thermal Control Circuit (TCC) activation. BUG=b:171531244 TEST=build and verify by thermal team Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Ic2822b059f166779e1f0bcf92e753dad1078783c Reviewed-on: https://review.coreboot.org/c/coreboot/+/47691 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Ben Kao <ben.kao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20mb/google/zork: Remove 50ms WIFI delayMartin Roth
As a part of trying to get our boot time as low as possible, any delays in the code should try to be refactored out. This removes the 50ms delay in the WIFI sequence by enabling power and putting the wifi module into reset in bootblock, then bringing it out of reset in ramstage. This is significantly longer than the 50ms requirement. The reset GPIO was already being set high in ramstage, so that code didn't need to be added. BUG=b:171513520 TEST=Boot on boards with different module types, WIFI works on both. BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I211d3da338ad368d1f011f03cf7d05121c057075 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-20mb/google/volteer/var/elemi: Update gpioWisley Chen
1. Config EN_PP3300_SSD (GPP_B2) to gpo 2. EMMC_CLKREQ_ODL(GPP_C1) change to GPP_H11 3. WLAN_PERST_L (GPP_H10) change to GPP_H10 BUG=b:172630765, b:171467336 BRANCH=volteer TEST=emerge-volteer coreboot chromeos-bootimage and boot into emmc Change-Id: I9d112373c4ecd2cea5ce3d2d47b190c061d50da6 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47705 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20mb/google/volteer/var/elemi: enable Genesys Logic GL9763EWisley Chen
Enable Genesys GL9763E as PCI-to-eMMC bridge. BUG=b:171467336 BRANCH=volteer TEST=emerge-volteer coreboot Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Change-Id: I858c12151df5b6fc19132869317edfa1b090335d Reviewed-on: https://review.coreboot.org/c/coreboot/+/47040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-20mb/asus/f2a85-m_pro: Enable PCIe bridge 00:15.2 in AGESAPaul Menzel
Currently, the PCIe bridge 00:15.2 is not detected by coreboot, causing the connected network device also to be missing. This is caused by not configuring the third of the four PCIe General Purpose Ports (GPP) of the AMD Fusion Controller Hub (FCH), which can be exposed as one to four PCIe devices. So, enable it in AGESA but disable enumeration in coreboot. Otherwise, the serial console stops working in romstage after […] PCI: 00:15.1 bridge ctrl <- 0013 PCI: 00:15.1 cmd <- 06 PCI: 00:15.2 bridge ctrl <- 0013 PCI: 00:15.2 cmd <- 07 and the system hangs in the payload (SeaBIOS banner is shown on VGA attached monitor). TEST=Serial console and payload works, and Linux 5.10-rc2 configures PCIe bridge. Output of `lspci -t`: -[0000:00]-+-00.0 +-00.2 +-01.0 +-01.1 +-10.0 +-10.1 +-11.0 +-12.0 +-12.2 +-13.0 +-13.2 +-14.0 +-14.2 +-14.3 +-14.4-[01]-- +-14.5 +-15.0-[02]-- +-15.1-[03]----00.0 +-15.2-[04]----00.0 +-18.0 +-18.1 +-18.2 +-18.3 +-18.4 \-18.5 Change-Id: Ia1d60a212b0d249c7d8b3f8ec16baf5e93c985da Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46527 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20mb/clevo/kbl-u: Add Clevo N130WU/N131WUFelix Singer
Working: - TianoCore - NVMe, SATA3 - USB2, USB3 - Thunderbolt - Graphics (GOP and libgfxinit) - Sound - Webcam - WLAN, LAN, Bluetooth, LTE - Keyboard, touchpad - TPM - flashrom support; reading / flashing from Linux - ACPI S3 WIP: - Documentation Not working: - EC ACPI (e.g. Fn keys, battery and power information) Boots Arch Linux (Linux 5.8.12) successfully. Change-Id: I364f5849ef88f43b85efbd7a635a27e54d08c513 Signed-off-by: Felix Singer <felixsinger@posteo.net> Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/28640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-20soc/mediatek: Move auxadc driver from MT8183 to commonPo Xu
The auxadc (auxiliary analogue-to-digital conversion) is a unit to identify the plugged peripherals or measure the temperature or voltages. The MT8183 auxadc driver can be shared by multiple MediaTek SoCs so we should move it to the common folder. Signed-off-by: Po Xu <jg_poxu@mediatek.com> Change-Id: Id4553e99c3578fa40e28b19a6e010b52650ba41e Reviewed-on: https://review.coreboot.org/c/coreboot/+/46390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-11-20mb/scaleway/tagada: GPIO on M.2 PCIe/SATA configure FSP HSIO lanesJulien Viard de Galbert
Change-Id: Ic3ed97fc2b54d4974ec0b41b9f207fe3d49d2cce Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-20mb/google/volteer: Add keyboard layout to fw_configDuncan Laurie
A new field was defined for different keyboard layouts, so add this field to the list and provide the two options that were defined. Change-Id: Ic357446725e34221040705929d54cbce94c5ab8b Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-20mb/google/volteer/variants: Set TCSS PCIe RP0 to hidden by defaultDuncan Laurie
Set the default state of the TCSS PCIe RP0 to hidden so that coreboot does not allocate resources to this hotplug root port. The default behavior on the reference design is that there is only one USB4 port attached to port C1 while port C0 is only a USB3 port. Meanwhile the Voxel and Terrador variants do have USB4 on both C0 and C1 ports, so these boards change the default to 'on' so that coreboot does allocate resources for the hotplug port. BUG=b:159143739 BRANCH=volteer TEST=build volteer and voxel and check the resulting static.c to ensure the device is hidden or not. Also boot with the two different configurations and ensure resources are assigned or not. Finally check that S0ix still functions with the C0 port set to 'hidden' after authorizing a PCIe tunnel on port C1. Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I8bb05ae8cd14412854212b7ed189cfa43d602c1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/47198 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20mb/google/volteer: Set up SATAXPCIE1 IOSSTATE based on detected deviceDuncan Laurie
There is an issue with the storage device being mis-detected on exit from S0ix which is causing the root device to disappear if the power is actually turned off via RTD3. To work around this read the RX state of the pin and apply the IOSSTATE setting to drive a 0 or 1 back to the internal controller. This will ensure the device is detected the same on resume as on initial boot. BUG=b:171993054 TEST=boot on volteer with PCIe NVMe and SATA SSD installed in the M.2 slot and ensure this pin is configured appropriately. Additionally test with PCIe RTD3 enabled to ensure suspend/resume works reliably. Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I85542151eebd0ca411e2c70d8267a8498becee78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-20mb/google/volteer: Enable RTD3 for SD cardDuncan Laurie
Enable the PCIe RTD3 driver for the PCIe attached SD card interface and provide the enable/reset GPIOs. These GPIOs are common across all variants so this is implemented in the baseboard devicetree with an fw_config probe if the device is present. The RTS5261 device does not have an enable GPIO so it is disabled in a workaround in mainboard.c, along with marking the SD-Express device as external. BUG=b:162289926, b:162289982 TEST=Tested on Delbin platform to ensure the system can enter the S0i3.2 substate and suspend/resume is stable. enabling this for the regular Genesys Change-Id: I40fe05829783c7bce2a2c4c1520a4a7430642e26 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-20mb/google/volteer/variants: Enable RTD3 for the NVMe deviceDuncan Laurie
Enable Runtime D3 for the volteer variants that have GPIO power control of the NVMe device attached to PCIe Root Port 9. Enable the GPIO for power control for variants that do not already have it configured to allow the power to be disabled in D3 state. BUG=b:160996445 TEST=tested on delbin Change-Id: I6ebf813c6c3364fec2e489a9742f04452be92c45 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46262 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20soc/intel/common/acpi,mb/*: replace the two obsolete LPID with PEPDMichael Niewöhner
Replace the two obsolete LPID implementations with the new PEPD device. The PEPD device gets included in the plaforms' `southbridge.asl`, since it is required to load the `intel_pmc_core` module in Linux, which checks for the _HID. (See CB:46469 for more info on that.) There is no harm for mainboards not supporting S0ix, because the _DSM function won't be called with the LPS0 UUID on such boards. Such boards can use the debugging functionality of `intel_pmc_core`, too. Change-Id: Ic8427db33286451618b50ca429d41b604dbb08a5 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46471 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19soc/intel/common/acpi: rename LPID to PEPDMichael Niewöhner
Rename LPID to PEPD for consistency. PEPD means "Power Engine Plug-In Device" and is the name Intel and vendors usually use, so let's comply. Change-Id: I1caa009a3946b1c55da8afbae058cafe98940c6d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46470 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19mb/google/zork: Set GPIO 86 high on bootMartin Roth
GPIO 86 should be set high on boot to save power. BUG=b:173340497 TEST=Build only BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I31ef1d2a1967d82ba5370462783a909417088d2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/47673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>