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2022-05-05soc/intel/tigerlake: Add enum for `DdiPortXConfig`Angel Pons
Add an enum for `DdiPortXConfig` devicetree options. Note that setting these options to zero does not disable the corresponding DDI port, but instead indicates that no LFP (Local Flat Panel, i.e. internal LCD) is connected to it. Change-Id: I9ea10141e51bf29ea44199dcd1b55b63ec771c0a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2022-05-02mb/system76: Configure I2C HID IRQs as level triggeredTim Crawford
Per Microsoft's spec for HID over I2C [1], interrupts must be level triggered. Switch GPIOs and the devicetree config to conform to this. Touchpad and multitouch gestures were already working, so no behavior changes are observed in normal use. [1]: http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx Change-Id: I485e616ae00e10bc3620ff3fa1fc1e903653c5cc Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-04-21tpm: Refactor TPM Kconfig dimensionsJes B. Klinke
Break TPM related Kconfig into the following dimensions: TPM transport support: config CRB_TPM config I2C_TPM config SPI_TPM config MEMORY_MAPPED_TPM (new) TPM brand, not defining any of these is valid, and result in "generic" support: config TPM_ATMEL (new) config TPM_GOOGLE (new) config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE) config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE) What protocol the TPM chip supports: config MAINBOARD_HAS_TPM1 config MAINBOARD_HAS_TPM2 What the user chooses to compile (restricted by the above): config NO_TPM config TPM1 config TPM2 The following Kconfigs will be replaced as indicated: config TPM_CR50 -> TPM_GOOGLE config MAINBOARD_HAS_CRB_TPM -> CRB_TPM config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE Signed-off-by: Jes B. Klinke <jbk@chromium.org> Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-15soc/intel/tgl: move DIMM_SPD_SIZE from mb to SoC KconfigMichael Niewöhner
All TGL mainboards are setting DIMM_SPD_SIZE to 512. Thus, default to 512 in the SoC Kconfig and drop it from the mainboard Kconfigs. Change-Id: I9fd947b61c984e10bd5fba20b73280b08623a008 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62766 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-15{mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototypeSubrata Banik
This patch modifies `memcfg_init` and `variant_memory_init`functions argument from FSP_M_CONFIG to FSPM_UPD. This change in `memcfg_init()` argument will help to update the architectural FSP-M UPDs from common code blocks rather than going into SoC and/or mainboard implementation. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=Able to build and boot redrix without any visible failure/errors. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3002dd5c2f3703de41f38512976296f63e54d0c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-01-25mb/system76: Enable SrcClk pin for CPU PCIe RPsTim Crawford
This reverts commit bd9b044a96cc ("mb/system76: rtd3: Remove SrcClk pin on CPU RP"). Previously, RTD3 expected a PCH index for the root port and did not work with the CPU PCIe RP present on TGL, so SrcClk pin was disabled. Set them now that RTD3 supports mapping the index for the CPU RP. Change-Id: Ia7519b9f5a2be52cd5575615c28d20371a26996b Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2022-01-24mb/system76/lemp10: Remove incorrect SPD address 0x50Tim Crawford
The Lemur Pro, with its mixed memory topology, only has a DIMM at address 0x52. Change-Id: Iecea8c70c7fd40943d86f8918f8e3b384538b5c3 Fixes: 4dcee4f21db5 ("mb/system76/lemp10: Add System76 Lemur Pro 10") Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-01-22mb/system76/lemp9: Make GPIO for touchpad interrupt level triggeredJeremy Soller
Fixes commit 6bcaf6f (mb/system76/lemp9: Configure IRQs as level triggered for HID over I2C), which changed the interrupt configuration in the device tree but not in the GPIO definitions. Tested on a System76 Lemur Pro (lemp9), multi-touch I2C-HID was working. Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: I7f0559675a65453a1ad071f96049549a2dc21378 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-01-21mb/system76/*: Enable measured bootTim Crawford
Tested by checking PCR-2 data is recorded in cbmem log. Change-Id: I70cb9a93de44e75f3a3ed24979c243fccea1213d Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-01-21mb/system76/gaze15: Set _UID for touchpad devicesTim Crawford
The _UID must be unique as these devices use the same _HID. Fixes BSOD when booting Windows 10. Change-Id: I67fda892a496dc9e5a6fa5e133ff0b35cde8fce7 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-01-16soc/intel/skl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik
List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. 3. Make dt CSE PCI device `on` by default. 4. Mainboards set DISABLE_HECI1_AT_PRE_BOOT=y to make Heci1 function disable at pre-boot instead of the dt policy that uses `HeciEnabled = 0`. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I5c13fe4a78be44403a81c28b1676aecc26c58607 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-14soc/intel/tgl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik
List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4a81fd58df468e2711108a3243bf116e02986316 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-14soc/intel/tigerlake: add devicetree option PcieRpSlotImplementedMichael Niewöhner
Add the UPD PcieRpSlotImplemented as devicetree option. To keep the PI bit set for any slots of already existing boards, add set the option PcieRpSlotImplemented=1 where appropriate. Change-Id: Ia6f685df3c22c74ae764693329a69817bf3cd01d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-23mb: Remove dot from end of non-sentence commentPaul Menzel
Run the command below to fix all occurrences. $ git grep -l 'configuration in bootblock\. \*/' | xargs sed -i 's,configuration in bootblock\. \*/,configuration in bootblock */,' Change-Id: I84669341e2c8976953284dbaf113da3397857de3 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-23drivers/intel/pmc_mux/conn: Change usb{23}_port_number fields to device pointersReka Norman
Currently, the pmc_mux/conn driver uses integer fields to store the USB-2 and USB-3 port numbers from the SoC's point of view. Specifying these as integers in the devicetree is error-prone, and this information can instead be represented using pointers to the USB-2 and USB-3 devices. The port numbers can then be obtained from the paths of the linked devices, i.e. dev->path.usb.port_id. Modify the driver to store device pointers instead of integer port numbers, and update all devicetrees using the driver. These are the mainboards affected (all are Intel TGL or ADL based): google/brya google/volteer intel/adlrvp intel/shadowmountain intel/tglrvp system76/darp7 system76/galp5 system76/lemp10 Command used to update the devicetrees: git grep -l "usb._port_number" src/mainboard/ | \ xargs sed -i \ -e 's/register "usb2_port_number" = "\(.*\)"/use usb2_port\1 as usb2_port/g' \ -e 's/register "usb3_port_number" = "\(.*\)"/use tcss_usb3_port\1 as usb3_port/g' BUG=b:208502191 TEST=Build test all affected boards. On brya0, boot device and check that the ACPI tables generated with and without the change are the same. Change-Id: I5045b8ea57e8ca6f9ebd7d68a19486736b7e2809 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-12-19mainboard: Fix comment about early GPIOsAngel Pons
These boards program the early GPIO table in bootblock, not romstage. Change-Id: Iae9353d106483f30cefa2d035d96e63e4c127261 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Sean Rhodes <admin@starlabs.systems> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-09soc/intel/tigerlake: Hook up DPTF device to devicetreeFelix Singer
Hook up `Device4Enable` FSP setting to devicetree state and drop its redundant devicetree setting `Device4Enable`. The following mainboards enable the DPTF device in the devicetree despite `Device4Enable` is not being set. * google/deltaur Thus, set it to off to keep the current state unchanged. Change-Id: Ic7636fc4f63d4beab92e742a6882ac55af2565bc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-09soc/intel/tigerlake: Hook up SMBus device to devicetreeFelix Singer
Hook up `SmbusEnable` FSP setting to devicetree state and drop its redundant devicetree setting `SmbusEnable`. The following mainboards enable the SMBus device in the devicetree despite `SmbusEnable` is not being set. * google/deltaur * starlabs/laptop Thus, set it to off to keep the current state unchanged. Change-Id: I0789af20beb147fc1a6a7d046cdcea15cb44ce4c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-23mb/system76/*: Enable dGPU temp/fan reportingTim Crawford
Select the EC option on boards with dGPUs to report GPU temperature and fan data. Tested on system76/oryp6. The GPU fan speed is reported in sensors when the system is under load. system76_acpi-acpi-0 Adapter: ACPI interface CPU fan: 1985 RPM GPU fan: 2348 RPM CPU temp: +68.0°C GPU temp: +0.0°C Change-Id: Ieb45dc277c7eb11be1c50b9a9e3e20e3a88578b7 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-11-23mb/system76/*: Disable IME by CMOS optionTim Crawford
Add CMOS option to set IME mode. Default to "Disable" for CNL and TGL-H, and "Enable" for TGL-U. Not set for KBL, which uses ME_CLEANER. The HECI device must be enabled in devicetree for switching modes to function correctly. Change-Id: I3163dcb0a4af020c2cf6f94f2bb26380f17c253e Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-11-11mb/system76/gaze16: Add System76 Gazelle 16Jeremy Soller
https://tech-docs.system76.com/models/gaze16/README.html The gaze16 comes in 3 variants due to differences in the discrete GPU and network controller used. - NVIDIA RTX 3050, using Realtek Ethernet controller - NVIDIA RTX 3060, using Realtek Ethernet controller - NVIDIA RTX 3060, using onboard Intel I219-V Ethernet controller Tested on the 3050 variant. Tested with TianoCore (UefiPayloadPkg). Working: - PS/2 keyboard, touchpad - Both DIMM slots - M.2 NVMe SSD - M.2 SATA SSD - 2.5" SSD - All USB ports - SD card reader - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - HDMI output - Internal microphone - Internal speakers - Combined headphone + mic 3.5mm audio* - 3.5mm microphone input* - S3 suspend/resume - Booting to Pop!_OS Linux 21.04 and Windows 10 20H2 - Flashing with flashrom Not working: - Discrete/Hybrid graphics - Mini DisplayPort output (requires NVIDIA GPU) - 3.5mm audio input/output detection on Windows Change-Id: Ifb90f9b73a10abf53a21738e2c466d539df9a37c Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-04mb/system76/*: Enable HECI deviceTim Crawford
The HECI device needs to be enabled to send the commands to have the CSME change between Soft Temporary Disable mode and Normal mode. Change-Id: I668507e3b522137bcc827aa615dab1fccd1709a0 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-11-02mb/system76/oryp8: Add System76 Oryx Pro 8Jeremy Soller
https://tech-docs.system76.com/models/oryp8/README.html Tested with TianoCore (UeifPayloadPkg). Working: - PS/2 keyboard, touchpad - Both DIMM slots - Both M.2 SSD slots - All USB ports - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Internal microphone - Internal speakers - Combined 3.5mm headphone & microphone jack - Combined 3.5mm microphone & S/PDIF jack* - S3 suspend/resume - Booting to Pop!_OS Linux 21.10 and Windows 10 20H2 - Flashing with flashrom Not working: - Discrete/Hybrid graphics Not tested: - Thunderbolt functionality - S/PDIF output Change-Id: Iabc8e273f997d7f5852ddec63e0c1bf0c9434acb Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02mb/system76/bonw14: Add System76 Bonobo Workstation 14Jeremy Soller
Change-Id: I55a827f8d6a5421c36f77049935630f4db4ba04d Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02mb/system76/kbl-u: Add Galago Pro 2 as a variantJeremy Soller
Change-Id: Ia277b3ad50c9f821ab3e1dcb8327314ba955fa79 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-02mb/system76/kbl-u: Add Galago Pro 3 as a variantJeremy Soller
Change-Id: Ie203883cc9418585da4f9c7acd89e7624234caf1 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-02mb/system76/kbl-u: Add System76 Galago Pro 3 Rev BJeremy Soller
Change-Id: I25464d3a2dd02e613a8392db90b1eaf0f9b3ca70 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02mb/system76/gaze15: Add Gazelle 14 as a variantTim Crawford
Change-Id: Ib455951d1d26ddfa010d4eb579905235bd1385a9 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02mb/system76/gaze15: Convert to variant setupTim Crawford
Change-Id: I6d8a97d71ff3b4408f5e11230ed3ff00357f7123 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02mb/system76/oryp6: Add Oryx Pro 7 as a variantJeremy Soller
Change-Id: Id00a45a6a6acf0880934c55f1a3f18e63f2aed43 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02mb/system76/oryp6: Convert to variant setupTim Crawford
The Oryx Pro 6 has the same board layout as the next model in series, Oryx Pro 7. The primary difference between the two is the dGPU (20 series to 30 series). Convert oryp6 to a variant setup in preparation for adding the oryp7. Change-Id: I976750c7724d23b303d0012f2d83c21a459e5eed Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02mb/system76/*: CMOS: Drop power_on_after_fail optionTim Crawford
Our boards do not boot if power_on_after_fail=Disable. Drop the option and use the default of powering on. Change-Id: Ia1857e52f838337048f79f8ca5c12d669cae321a Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-10-15mainboard: Drop invalid `VGA_BIOS_FILE` defaultsAngel Pons
If the VGA BIOS file path for `VGA_BIOS_FILE` in a mainboard's Kconfig does not exist in the coreboot tree (including submodules), drop it. These files should be stored in the `site-local` subdirectory and the paths specified for each board in `site-local/Kconfig`. For example: config VGA_BIOS_FILE default "site-local/x200_vbios.bin" if BOARD_LENOVO_X200 Note that this is just an example. There are better ways to structure one's `site-local` subfolder. Using the `CONFIG_MAINBOARD_DIR` option would be one of them, though variants may still need special handling. Also, update autoport to not generate `VGA_BIOS_FILE` defaults. Change-Id: I1b5dfba035a42d7943f270f95fb7d32b285584d2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-10-12soc/intel: replace dt option PmTimerDisabled by KconfigMichael Niewöhner
Replace the dt option `PmTimerDisabled` with use of the Kconfig option `USE_PM_ACPI_TIMER` for enabling/disabling the PM Timer. A default value representing the prior devicetree value was added to the boards system76/{lemp10,galp5,darp7}, so this change will not alter behaviour. Change-Id: If1811c6b98847b22272acfa35ca44f4fbca68947 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-09mb/system76: tgl-u: Add gfx register for GMA ACPITim Crawford
Add gfx register to System76 TGL-U boards so GMA ACPI data is generated. Change-Id: If944a90921b518efdcd5f0e0998bddb4f56e5764 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-27mb/system76/gaze15: Disable OC supportTim Crawford
Clevo indicated that DIMMs running at 2933 MHz are not supported on a number of processors used for this model. Change-Id: Iadf611a64de664c783696e51cfe858ca95903936 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-09-27mb/system76/lemp10: Use PME virtual wire for SWITim Crawford
Match the behavior of the other TGL-U boards. Change-Id: Ida962255f7a2435319d739d59eb2dc58fe342ae8 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-09-27mb/system76: rtd3: Remove SrcClk pin on CPU RPTim Crawford
Setting srcclk_pin only works for PCH PCIe devices. Disable them on the CPU RP and add a TODO. Change-Id: I32db116feb33a8448eb8586fe9e882b8879489d4 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57882 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-09-22mb/system76/addw1: Add Adder WS 2 as a variantTim Crawford
Change-Id: I3965a90151bd9250a87dabc715d68a39699ff9e1 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-22mb/system76/addw1: Add System76 Adder Workstation 1Tim Crawford
Change-Id: I5dd3bc320ca640728e1d86180c6bfa0dc7295760 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-20mb/system76/cml-u: Add Darter Pro 6 as a variantTim Crawford
Change-Id: I9ba7d2af3c9c298fda2b2997d52546cc2f702a82 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-20mb/system76/cml-u: Add System76 Galago Pro 4Tim Crawford
Change-Id: I3dfa2ab430439d8dc71531b92aa7800db94d603b Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-17mb/system76/gaze15: Correct CMOS type for debug_levelTim Crawford
When the century byte was reserved, the debug_level was accidentally converted from an enum to a hidden value. Change it back to an enum. Fixes: f05bd8830de ("mb/system76/*: cmos.layout: Reserve century byte") Change-Id: Id88a7aed7b2fc793fd003db5b45f3f201b1a7630 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-09-16mb/system76/darp7: Add System76 Darter Pro 7Tim Crawford
https://tech-docs.system76.com/models/darp7/README.html Tested with TianoCore (UefiPayloadPkg). Working: - PS/2 keyboard, touchpad - Both DIMM slots - M.2 NVMe SSD - M.2 SATA SSD - MicroSD card reader - All USB ports - USB-PD - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - HDMI output - DP over USB-C output - Internal microphone - Internal speakers - Combined 3.5mm headphone/microphone jack - S0ix suspend* - Booting to Ubuntu Linux 21.04 and Windows 10 - Flashing with flashrom Not working: - S0ix when a device is attached to the TBT port Not tested: - Thunderbolt functionality Change-Id: I80e5c5375f9d3881fc89a45a91ba68ed2e104a93 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52349 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-15mb/system76/galp5: Add System76 Galago Pro 5Tim Crawford
https://tech-docs.system76.com/models/galp5/README.html Tested with TianoCore (UefiPayloadPkg). Working: - PS/2 keyboard, touchpad - Both DIMM slots - M.2 NVMe SSD - All USB ports - SD card reader - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - HDMI output - Internal microphone - Internal speakers - Combined 3.5mm headphone/microphone jack - S0ix suspend* - Booting to Pop!_OS Linux 21.04 and Windows 10 - Flashing with flashrom Not working: - Discrete/Hybrid graphics - S0ix when a device is attached to the TBT port Change-Id: I0d9052c0b064d4d43812ad837578d4a097149cc8 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-15mb/system76/lemp10: Add System76 Lemur Pro 10Tim Crawford
https://tech-docs.system76.com/models/lemp10/README.html Tested with TianoCore (UefiPayloadPkg). Working: - PS/2 keyboard, touchpad - DIMM slot and onboard RAM - Both M.2 NVMe SSDs - MicroSD card reader - All USB ports - USB-PD - Webcam - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - HDMI output - DP over USB-C output - Internal microphone - Internal speakers - Combined 3.5mm headphone/microphone jack - S0ix suspend* - Booting to Pop!_OS Linux 21.04 and Windows 10 - Flashing with flashrom Not working: - S0ix when a device is attached to the TBT port Change-Id: I15f7a3b6e9af07fcfde9a71d3f4a84ed625159b7 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-10cannonlake mainboards: Set PMC as hidden in devicetreeTim Wawrzynczak
FSP-S hides the PMC from the PCI bus when it runs, but there are still initialization steps coreboot programs for the PMC. Therefore, change all of the cannonlake mainboards to set the PMC as hidden in the devicetree, which means the device will be skipped during enumeration, but device callbacks are still issued as if the device were enabled. TEST=Ran full patch train on google/dratini, disassembled SSDT and the PEPD device matches what is in pep.asl. Also verified via dmesg that the INT33A1 device is still initialized by the kernel. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib4a20ce9075ce7653388a5d3e281fe774bf89355 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-08mb/system76/whl-u: Add missing device nodeNico Huber
All `chip` entries need a device node below them to actually get hooked up. Add a dummy generic device like other instances of this driver use. Change-Id: Ifbb5c9a6b389a2c809ce654d584d5197af764893 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57475 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Crawford <tcrawford@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-03src/*: Specify type of `DIMM_MAX` onceAngel Pons
Specify the type of the `DIMM_MAX` Kconfig symbol once. Change-Id: I2e86baaa8bd50c7b82c399fde5dcea05da6b4307 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-09-02mb/system76/*: cmos.layout: Reserve century byteTim Crawford
Windows will write to the century byte (0x32), causing the option table checksum to be invalid and reset all options to their default values. Move options and checksum to start after the century byte. Change-Id: Ia395acacda1e251251c880587bbf61d7ee81ba3d Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-08-28soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by defaultFelix Singer
Since all mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, make it the default by changing its enum value to 0 and remove its configuration from all related devicetrees. If `common_soc_config.chipset_lockdown` is not configured with something else in the devicetree, then `CHIPSET_LOCKDOWN_COREBOOT` is used. Also, add a release note for the upcoming 4.15 release. Change-Id: I369f01d3da2e901e2fb57f2c83bd07380f3946a6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-12mb/system76/*: Add CMOS option tableTim Crawford
System76 uses several custom CMOS values downstream. Reduce our diff by providing a generic layout with the defaults: boot_option=Fallback debug_level=Debug power_on_after_fail=Enable Tested on galp3-c, gaze15, oryp5, oryp6. All boards boot multiple times with USE_OPTION_TABLE selected. Change-Id: Ie57b0e5713bba8ad46e1a4123a3ddd43e0eea964 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-08-10mb/system76/oryp6: Enable TAS5825M smart ampTim Crawford
Allows using the internal speakers of the oryp6. Smart AMP data was collected using a logic analyzer connected to the IC during system start on proprietary firmware. This data is then used to generate a C file [1]. [1]: https://github.com/system76/smart-amp Change-Id: I57781a7223a52b8fc5295cf686412926529c3a7f Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-09mb/system76/oryp6: Drop DIMM_SPD_SIZETim Crawford
The board uses the default size specified in the SoC. Change-Id: Ie71a0fea1ff9de6c4f1ce8db2db09bb3cd35d04d Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-07-26mb/*: Specify type of `VARIANT_DIR` onceAngel Pons
Specify the type of the `VARIANT_DIR` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: Iea2f992a59e41e00fec3cdc9d6a13b5f3ab0a437 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56558 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `OVERRIDE_DEVICETREE` onceAngel Pons
Specify the type of the `OVERRIDE_DEVICETREE` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I4cbf4e318a30f0cf75aa8690e7454b9caa115c9d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56556 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `MAINBOARD_PART_NUMBER` onceAngel Pons
Specify the type of the `MAINBOARD_PART_NUMBER` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I3692f9e82fe90af4d0da1d037018a20aa1b45793 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56554 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `MAINBOARD_DIR` onceAngel Pons
Specify the type of the `MAINBOARD_DIR` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: If1cc538b0c4938dac193699897b690e402b3c1e8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56553 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26src/*: Specify type of `CBFS_SIZE` onceAngel Pons
There's no need to specify the type of the `CBFS_SIZE` Kconfig symbol more than once. This is done in `src/Kconfig`, along with its prompt. Change-Id: I9e08e23e24e372e60c32ae8cd7387ddd4b618ddc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56552 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-29Kconfig: Escape variablesPatrick Georgi
New kconfig parsers interpret $(var) themselves, leading to empty fields. Old kconfig understands \$(var), so use that. Change-Id: I927fc9dc7a66211bfe51d4324cf7c51b555ea3a8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55912 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26mb/system76/oryp6: Add System76 Oryx Pro 6Tim Crawford
https://tech-docs.system76.com/models/oryp6/README.html Tested with TianoCore (UefiPayloadPkg). Working: - PS/2 keyboard, touchpad - Both DIMM slots - M.2 NVMe - M.2 SATA - MicroSD card slot - All USB ports - Integrated graphics using Intel GOP driver - Webcam - Ethernet - Internal microphone - Combined headphone + mic 3.5mm jack - Combined microphone + S/PDIF 3.5mm jack - Booting to Ubuntu Linux 20.10 and Windows 10 - Flashing with flashrom Not working: - S3 suspend/resume: System hangs on wake from S3 - Discrete/Hybrid graphics: Requires a new driver - Internal speakers: Enabled in separate patch Not tested: - Thunderbolt functionality - S/PDIF output Change-Id: If017d65ca6cb36fe1f631d4dadd050a1547c93fa Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47768 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-23mb/system76/oryp5: Leave NC GPIOs unterminatedTim Crawford
Remove the unneeded pull up, as leaving them unterminated disconnects them from internal logic. Also replace use of PAD_CFG_TERM_GPO with PAD_CFG_GPO where no termination is used. Change-Id: Ia85ea39d46d7d9584b94726a7d601ca06826b1d1 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-23mb/system76/gaze15: Leave NC GPIOs unterminatedTim Crawford
Remove the unneeded pull up, as leaving them unterminated disconnects them from internal logic. Also replace use of PAD_CFG_TERM_GPO with PAD_CFG_GPO, as none configure termination. Change-Id: I28549a89a885598ba2d5111a9974356562a03cde Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-22soc/intel/cannonlake: Set DIMM_SPD_SIZE to 512Felix Singer
All related mainboards are setting DIMM_SPD_SIZE to 512. Therefore, default to 512 in the SoC Kconfig and drop it from related mainboard Kconfigs. Change-Id: Idb6a0e42961eeb490afd76b4aa7d940961991733 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52513 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18soc/intel/cnl and mainboards: Drop `cnl_configure_pads()`Furquan Shaikh
CB:31250 ("soc/intel/cannonlake: Configure GPIOs again after FSP-S is done") introduced a workaround in coreboot for `soc/intel/cannonlake` platforms to save and restore GPIO configuration performed by mainboard across call to FSP Silicon Init (FSP-S). This workaround was required because FSP-S was configuring GPIOs differently than mainboard resulting in boot and runtime issues because of misconfigured GPIOs. This issue has since been fixed in FSP (verified with FSP v1263 on hatch). However, there were still 4 boards in coreboot using `cnl_configure_pads()`. As part of RFC CB:50829, librem_cnl, clevo/cml-u and system76/lemp9 were tested to ensure that this workaround is no longer required. This change drops the workaround using `cnl_configure_pads()` and updates all mainboards to use `gpio_configure_pads()` instead. Signed-off-by: Furquan Shaikh <furquan@google.com> Tested-by: Angel Pons <th3fanbus@gmail.com> (Tested purism/librem_cnl) Tested-by: Michael Niewöhner <foss@mniewoehner.de> (Tested clevo/cml-u which is similar to system76/lemp9) Change-Id: I7a4facbf23fc81707cb111859600e641fde34fc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52248 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16mb/system76/lemp9: correct pad GPP_A11 (INTP_OUT)Michael Niewöhner
This pad is connected to INTP_OUT of the Type-C PD controller. Correct the comment. Also remove the unneeded pull-up. Checked with schematics. Change-Id: I16a769ac6a2d54da700ddb45bd9c7c84383a43dd Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2021-04-16mb/system76/whl-u: Add Darter Pro 5 variantTim Crawford
The darp5 has several GPIO differences to the galp3-c, which are already accounted for in gpio.c. Change-Id: I951e86e53e9c47b9f3038927f44e505d37200c26 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-15mb/system76/oryp5: Enable TAS5825M smart ampTim Crawford
Allows using the internal speakers of the oryp5. Smart AMP data was collected using a logic analyzer connected to the IC during system start on proprietary firmware. This data is then used to generate a C file [1]. [1]: https://github.com/system76/smart-amp Change-Id: I148f18ff3e754d913bdf907121b103c6de02ffc3 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47962 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-14mb/system76/whl-u: Add System76 Galago Pro 3 Rev CTim Crawford
Tested with TianoCore payload (UefiPayloadPkg). Working: - PS/2 keyboard, touchpad - Both DIMM slots - NVMe port - SATA port - SD card slot - Left USB 3 Type-A port - Right USB 3 Type-A port - Right USB 3 Type-C port - Webcam - Ethernet - Integrated graphics using Intel GOP driver - mDP output - HDMI output - Internal microphone - Internal speakers - 3.5mm audio input - 3.5mm audio output - S3 suspend/resume - Flashing with flashrom - Booting to Ubuntu Linux 20.10 and Windows 10 Not tested: - Thunderbolt functionality Change-Id: I5c992e603dbd57ae1b4ddc3a0f9bfc92d6acc813 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-12mb/*: drop LPC generic range for port 80Michael Niewöhner
Port 80 (actually 0x80-0x8f) is a fixed I/O range and thus does not have to be set up as generic range. Drop the entries from the devicetrees. Change-Id: I8a54d3c35a321a2d57bd846662f7339eff53e5a8 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-04-08soc/intel/{cannonlake,icelake}: Drop unhooked `SendVrMbxCmd`Angel Pons
This option's value is not used anywhere. Remove it. Change-Id: I0f30cddd30d459f48b51f377b111bbc04709c5f8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-06mb/system76: acpi: Remove unused EC defineTim Crawford
The define for color keyboard setting has never been used, as it was added as a Kconfig selection when ec/system76/ec was introduced. Change-Id: Ib83d4510c14ddf083660e42175ab093403792cac Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-03-24mb/system76/gaze15: Add System76 Gazelle 15Tim Crawford
Tested with TianoCore payload (UefiPayloadPkg). Working: - PS/2 keyboard, touchpad - Both DIMM slots - Both NVMe ports - SATA port - All USB ports - Webcam - Ethernet - Integrated graphics using Intel GOP driver - Internal microphone - Internal speakers - S3 suspend/resume - Flashing with flashrom - Booting to Ubuntu Linux 20.10 and Windows 10 Not working: - Discrete/Hybrid graphics This requires a new driver to work correctly, which will be added and enabled later. Change-Id: I10667fa26ac7c4b8eb67da11f3e963062bd0db47 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47822 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19mb/{clevo/cml-u,system76/lemp9}: Clarify `gen2_dec` useAngel Pons
This I/O range is for a PM channel on the EC, not the PCH PMC. Change-Id: I64422e537c1edcd0673cf87f16139fb117b10e75 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51604 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-11mb/system76/lemp9: Drop unneeded memcfg values and commentsAngel Pons
This mainboard uses a Comet Lake SoC and mixed-topology DDR4 memory. Drop LPDDR-specific DQ and DQS mappings and comment about Cannon Lake. Change-Id: Icb986d1c074e64b3cfad3897b69d35d108f64bff Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-12mb/system76/lemp9: Configure IRQs as level triggered for HID over I2CKarthikeyan Ramasubramanian
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: Ice096777077bd2e9cfbaf744371fc372c0c05606 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-28mb/system76/oryp5: Fix up DSDTPatrick Georgi
We started depending on dsdt_top.asl in dsdt.asl but this newly added board wasn't adapted yet, so have it catch up. Change-Id: If00280a33fd9e5c3ef1b3d07c41e81ed18013714 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50021 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28mb/system76/oryp5: Add System76 Oryx Pro 5Tim Crawford
Tested with TianoCore payload (UefiPayloadPkg). Working: - PS/2 keyboard, touchpad - Both DIMM slots - Both NVMe ports - SATA port - All USB ports - Webcam - Ethernet - Integrated graphics - Internal microphone - S3 suspend/resume - Flashing with flashrom - Booting to Ubuntu Linux and Windows Not working: - Discrete/Hybrid graphics - Internal speakers These two require new drivers to work correctly, which will be added and enabled later. Change-Id: Iae6e530dcd52df3642cdfe74b65bfff5aa0dd402 Signed-off-by: Tim Crawford <tcrawford@system76.com> Signed-off-by: Jeremy Soller <jeremy@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-27ACPI: Add top-level ASLKyösti Mälkki
Objects that are created with acpigen need to be declared with External () for the generation of dsdt.asl to pass iasl without errors. There are some objects that are common to all platforms, and some that should be declared only conditionally. Having a top-level ASL helps to achieve this. Change-Id: Ibaf1ab9941b82f99e5fa857c0c7e4b6192c74330 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-16mb/system76/lemp9: do early pad configuration in early bootstageMichael Niewöhner
Do early pad configuration in early bootblock before console init, to make the console work as early as possible. The board does not do any other gpio configuration in bootblock, so this should not influence behaviour in a negative way (e.g. breaking overrides). Change-Id: Ie122a441145383b820d96e32ce1581dfc27fa57b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2020-12-17soc/intel/cannonlake: Change mainboard_silicon_init_params argumentPatrick Rudolph
Use FSPS_UPD instead of FSP_S_CONFIG as argument as already done on xeon_sp and denverton_ns. This allows to set test config UPDs from mainboard code as well. Change-Id: I6d67264e22df32b9210ce88b99d6a7a4f6b97ffb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-12-08mb/*: Remove SATA mode config for CNL based mainboardsFelix Singer
SATA_AHCI is already the default mode for CNL based mainboards. Therefore, remove its configuration from all related devicetrees. Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains identical. Change-Id: I814e191243224a4b021cd7d4c1b611316f1fd1a4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-08soc/intel/cannonlake: Align SATA mode names with soc/sklFelix Singer
Align the SATA mode names with soc/skl providing a consistent API. Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains identical. Change-Id: I54b48462852d7fe0230dde0c272da3d12365d987 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-06mb/*: Remove unnecessary selectsFelix Singer
Remove SOC_INTEL_COMMON_BLOCK_HDA from mainboards Kconfig since it is selected by their SoC soc/intel/cannonlake. Change-Id: I9597746a217575b42f6325998b948e16b452231a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48289 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-12mb/*/Kconfig: Annotate closing endif with corresponding conditionPaul Menzel
It’s common to annotate the closing endif, so do it for these four files. Change-Id: Ia5d071e1f544c9dea5af9c6bc3c605d9a0c5c0f5 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-02mb/system76/lemp9: Enable battery charging thresholdsTim Crawford
Change-Id: I5131cf350d5b8c2a45f8d8245c0df26742c0d732 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45533 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02mb, soc/intel: Reorganize CNVi device entries in devicetreeFurquan Shaikh
This change reorganizes the CNVi device entries in mainboard devicetree/overridetree and SoC chipset tree to make it consistent with how other SoC internal PCI devices are represented i.e. without a chip driver around the SoC controller itself. Before: chip drivers/wifi/generic register "wake" = "..." device pci xx.y on end end After: device pci xx.y on chip drivers/wifi/generic register "wake" = "..." device generic 0 on end end end Change-Id: I22660047a3afd5994400341de0ca461bbc0634e2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-10-26mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`Michael Niewöhner
The dt option `speed_shift_enable` is obsolete now. Drop it. Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-10-13{src/mb,util/autoport}: Use macro for DSDT revisionElyes HAOUAS
Change-Id: I5a5f4e7067948c5cc7a715a08f7a5a3e9b391191 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-10-13mb, soc/intel: Switch to using drivers/wifi/generic for Intel WiFi devicesFurquan Shaikh
This change switches all mainboard devices to use drivers/wifi/generic instead of drivers/intel/wifi chip driver for Intel WiFi devices. There is no need for two separate chip drivers in coreboot to handle Intel and non-Intel WiFi devices since the differences can be handled at runtime using the PCI vendor ID. This also allows mainboard to easily multi-source WiFi chips and still use the same firmware image without having to distinguish between the chip drivers. BUG=b:169802515 BRANCH=zork Change-Id: Ieac603a970cb2c9bf835021d1fb0fd07fd535280 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-05soc/intel/common/block/acpi: Factor out common platform.aslSubrata Banik
This patch moves platform.asl into common block acpi directory to avoid duplicating the same ASL code block across SoC directory. TEST=Able to build and boot TGL, CNL and CML platform. 1) Dump and disassemble DSDT, verify _PIC method present inside common platform.asl is still there. 2) Verify no ACPI error seen while running 'dmesg` from console. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I5189b03d6abfaec39882d28b40a9bfa002128be3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-23treewide: rename GENERIC_SPD_BIN to HAVE_SPD_BIN_IN_CBFSMichael Niewöhner
The name GENERIC_SPD_BIN doesn't reflect anymore what that config is used for, so rename it to HAVE_SPD_BIN_IN_CBFS. Change-Id: I4004c48da205949e05101039abd4cf32666787df Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45147 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-22mb/system76/lemp9: gpio: convert gpio.h to a cleaner formatMichael Niewöhner
Convert gpio.h to a compacter, cleaner format by keeping gpios in a single line, where possible. This was done with the following fancy vim regex replacement commands. (Neither sed, nor awk multiline matching syntax are friends with me...) Just open src/mainboard/system76/lemp9/gpio.h with vim, type : before pasting each command, press enter and see how the format changes. g#^\t//#d %s/^\t\t/\t/ g/PAD_.*$\n\n[^/]/s/\n// g#// NC#d %s#^\t// \(.*\)\n\t// \(.*\)#\t// \1 \2#g %s#^\t// \(.*\)\n\t\(PAD_.*,\)#\t\2\t\t/* \1 */ %s#^// \(GP.*\)#\t/* ------- GPIO Group \1 ------- */# Finally some indents and multiline comments need to be fixed manually. Test: images built with TIMELESS do not differ. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I9054274dc4c8942935b6a4789bfc1547dd3d4017 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-09-22mb/system76/lemp9: convert inverted SCI/SMI macros to _LOW macroMichael Niewöhner
Convert PAD_CFG_GPI_S*I(..., INVERT) to PAD_CFG_GPI_S*I_LOW(...), which is better understandable. Change-Id: I147c82d738623bff54122ad5ef8ece028c562cab Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45488 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21mb/system76/lemp9: gpio: convert the remaining raw pads to macrosMichael Niewöhner
Convert the EC and touchpad interrupt pads from raw to macros. This was done with intelp2m. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I79d2cca0f300e6daf1c1923a1882e4cc1ffc3c8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/43648 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-20mb/system76/lemp9: move LPC options to the devicetreeMichael Niewöhner
Change-Id: I7b7acdc51c848541fb39926bc8de1115c026dd05 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45496 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-20mb/system76/lemp9: correct CBFS_SIZEMichael Niewöhner
The BIOS region size is 0xc00000, not 0xa00000. Correct this. Change-Id: I88cb0d4b9a590a32672054aa0db7f9a92070ff6d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-09-20mb/system76/lemp9: enable SATA ALPM capabilityMichael Niewöhner
Enable SATA Link Power Management capability to be able to save power. TEST: /sys/class/scsi_host/host*/link_power_management_policy exists. Change-Id: I88de28cfb266af3fcd6e498a08a24b46c992cb9d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45492 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-20mb/system76/lemp9: drop disabled options from devicetreeMichael Niewöhner
Drop all options with zero-value, since they already default to 0. Change-Id: I2a1a91778e83dc49c6dcf2d518cd3591f7ec4cfa Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45491 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-19mb/system76/lemp9: move subsystem id from Kconfig to devicetreeMichael Niewöhner
Change-Id: I21e7e53787b115f50093d7caa72285ce480cef52 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-21 10:58:48 +0000