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authorMichael Niewöhner <foss@mniewoehner.de>2021-04-10 22:51:15 +0200
committerMichael Niewöhner <foss@mniewoehner.de>2021-04-12 16:52:19 +0000
commitc5f1dc96bf0b18245d7986463ae56958c44d24f2 (patch)
treeed6b20f2b323d3ff835812aa98bf9450b177c4ec /src/mainboard/system76
parentc1ec940eba11d279912b24377a7cf8ab4b264aaa (diff)
mb/*: drop LPC generic range for port 80
Port 80 (actually 0x80-0x8f) is a fixed I/O range and thus does not have to be set up as generic range. Drop the entries from the devicetrees. Change-Id: I8a54d3c35a321a2d57bd846662f7339eff53e5a8 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/system76')
-rw-r--r--src/mainboard/system76/gaze15/devicetree.cb7
-rw-r--r--src/mainboard/system76/lemp9/devicetree.cb8
-rw-r--r--src/mainboard/system76/oryp5/devicetree.cb7
3 files changed, 9 insertions, 13 deletions
diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb
index e4ca948ff0..5165f61a66 100644
--- a/src/mainboard/system76/gaze15/devicetree.cb
+++ b/src/mainboard/system76/gaze15/devicetree.cb
@@ -194,10 +194,9 @@ chip soc/intel/cannonlake
device pci 1e.2 off end # GSPI #0
device pci 1e.3 off end # GSPI #1
device pci 1f.0 on # LPC Interface
- register "gen1_dec" = "0x000c0081"
- register "gen2_dec" = "0x00040069"
- register "gen3_dec" = "0x00fc0e01"
- register "gen4_dec" = "0x00fc0f01"
+ register "gen1_dec" = "0x00040069"
+ register "gen2_dec" = "0x00fc0e01"
+ register "gen3_dec" = "0x00fc0f01"
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb
index a0b6403a22..80f0ef4b9f 100644
--- a/src/mainboard/system76/lemp9/devicetree.cb
+++ b/src/mainboard/system76/lemp9/devicetree.cb
@@ -178,14 +178,12 @@ chip soc/intel/cannonlake
device pci 1e.3 off end # GSPI #1
device pci 1f.0 on # LPC Interface
# LPC configuration from lspci -s 1f.0 -xxx
- # Address 0x84: Decode 0x80 - 0x8F (Port 80)
- register "gen1_dec" = "0x000c0081"
# Address 0x88: Decode 0x68 - 0x6F (EC PM channel)
- register "gen2_dec" = "0x00040069"
+ register "gen1_dec" = "0x00040069"
# Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command)
- register "gen3_dec" = "0x00fc0E01"
+ register "gen2_dec" = "0x00fc0E01"
# Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug)
- register "gen4_dec" = "0x00fc0F01"
+ register "gen3_dec" = "0x00fc0F01"
chip drivers/pc80/tpm # TPM
device pnp 0c31.0 on end
end
diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb
index 6cf5c94ea8..2b08909b67 100644
--- a/src/mainboard/system76/oryp5/devicetree.cb
+++ b/src/mainboard/system76/oryp5/devicetree.cb
@@ -182,10 +182,9 @@ chip soc/intel/cannonlake
device pci 1e.2 off end # GSPI #0
device pci 1e.3 off end # GSPI #1
device pci 1f.0 on # LPC Interface
- register "gen1_dec" = "0x000c0081"
- register "gen2_dec" = "0x00040069"
- register "gen3_dec" = "0x00fc0e01"
- register "gen4_dec" = "0x00fc0f01"
+ register "gen1_dec" = "0x00040069"
+ register "gen2_dec" = "0x00fc0e01"
+ register "gen3_dec" = "0x00fc0f01"
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end