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2024-06-07mb/**/hda_verb: Use `AZALIA_PIN_CFG_NC(0)`Angel Pons
Replace `0x411111f0` with `AZALIA_PIN_CFG_NC(0)`, which evaluates to the same value and conveys additional information to the reader. Done with a bulk search and replace operation. Change-Id: Ibd84daec017bc1ab1ee4edd906fda80231c134cc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-06-03mb/system76: Add SPDX ID to devicetree filesTim Crawford
Change-Id: I55f2730f7277a3c699b86ded5864e9690d92d518 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82700 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06mb/system76: Exclude ramtop from CMOS checksumTim Crawford
Use the default position for ramtop and exclude it from the checksum. Fixes invalid checksum after caching ramtop causing things like disabling CSME to not work. Fixes: 10d2af04e754 ("mb/system76: Add space for ramtop in CMOS layout") Change-Id: If30df1e6f2735cf767856e42dfede3d17fe494eb Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81641 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18mb/*: Add SPDX headers for cmos.default filesMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ib7beed7218f317bc2352b65a6191ef1cdaa0742d Reviewed-on: https://review.coreboot.org/c/coreboot/+/80597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2024-02-18mb/samsung to mb/up: Add SPDX license headers to Kconfig filesMartin Roth
Change-Id: Ied455ff29b151fb5f4bca26a189b1d4104d8cede Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80595 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24mb/lenovo to mb/squared: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I4790adb41cb62c8c8dd44261a2926dfb6350955a Reviewed-on: https://review.coreboot.org/c/coreboot/+/80111 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-10-30mb/system76/cannonlake/dt: Use comma separated list for arraysFelix Singer
In order to improve the readability of the settings, use a comma separated list to assign values to their indexes instead of repeating the option name for each index. Don't convert the settings for PCIe root ports as they should stay in the device scope of them. While on it, remove superfluous comments related to modified lines. Change-Id: I92414efc9ddb849ceb8b9c4f0bc564bdbd92773b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78638 Reviewed-by: Tim Crawford <tcrawford@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-06mainboard: Add SPDX license headers to MakefilesMartin Roth
To help identify the licenses of the various files contained in the coreboot source, we've added SPDX headers to the top of all of the .c and .h files. This extends that practice to Makefiles. Any file in the coreboot project without a specific license is bound to the license of the overall coreboot project, GPL Version 2. This patch adds the GPL V2 license identifier to the top of all makefiles in the mainboard directory that don't already have an SPDX license line at the top. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic451e68b1ad9ccdf34484dd98bd7fca7e177ef22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68982 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-07-18{ec,mb}/system76: Replace color keyboard logicTim Crawford
System76 EC since system76/ec@9ac513128ad9 detects if the keyboard is white or RGB backlit via `RGBKB-DET#` at runtime. Remove the Kconfig for the selection and update the ACPI methods for the new functionality. Change-Id: I60d3d165a58e30d2afc8736c0eb64dd90c8227ca Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76152 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-03mb/system76: Add space for ramtop in CMOS layoutTim Crawford
Fixes building when `USE_OPTION_TABLE` is selected. Change-Id: I4fb017aa549b24eda6b9e0356bc1776d4044c95d Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-07-03mb/system76: Select CBFS SMBIOS hooksTim Crawford
Multiple users have requested to have the DMI values for product UUID and serial number be populated. Enable the drivers so that we may set them when flashing or updating firmware. Change-Id: I710363d9df626d51756a265f0099f26ef28411c2 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-07-03mb/system76: Select TPM read delay on all boardsTim Crawford
The Infineon chip occasionally fails Startup or Resume. Adding the delay makes it work more reliably. Change-Id: I4a8f98633154888e2167a3d55192b86e13ffcb62 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76095 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-04mb/system76: Add custom backlight levels for Intel GMATim Crawford
Add custom backlight levels for all models except: - addw1/addw2: Uses an OLED display - bonw14: Does not use the iGPU Change-Id: Ibea37f19acca0d718211fc41706019a92a240c70 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-03-04{ec,mb}/system76: Move smbios_system_wakeup_typeTim Crawford
Move the implementation of smbios_system_wakeup_type from the mainboards to the EC for all models that use System76 EC (everything except KBL). Change-Id: Iaace234ca87e8a05eaa006a438d2c9eb13ce4d76 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-01-30mb/*: Remove lapic from devicetreeArthur Heymans
The parallel mp code picks up lapics at runtime, so remove it from all devicetrees that use this codebase. Change-Id: I5258a769c0f0ee4bbc4facc19737eed187b68c73 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69303 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-12-29{ec,mb}/system76/acpi: Use Printf() for debug printsFelix Singer
Change-Id: Ia5ae30a1ee976b8059936027b28ac56f37279217 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71516 Reviewed-by: Tim Crawford <tcrawford@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24mb/system76: Reset Realtek codec before configuringTim Crawford
Perform a codec reset before configuring to avoid potential issues like oryp5 had before 86f410479ca9 ("mb/system76/oryp5: Reset HDA before configuring"). Inspecting proprietary firmware for multiple boards shows that this is always done as well. Change-Id: I64c1fd23f708f77a81fad0bc889f42d4df3f6e61 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66918 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2022-10-11mb/system76: Set SMBIOS wakeup type to power switchTim Crawford
Windows hardware tests require this field not be "Reserved". The System76 EC firmware does not report the wake type, so it is not possible to know if the system was powered on from the power switch or Wake-on-LAN. In the case WoL is used, this will report the wrong value. Change-Id: I4653c6bce2a5f0a88281fc810df5646e44f90674 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2022-08-16mb/**/dsdt.asl: Drop misleading "OEM revision" commentAngel Pons
It is highly unlikely that the "OEM revision" of the DSDT is 0x20110725 on mainboards with a chipset not yet released on 2011-07-25. Since this comment is most likely to have been copy-pasted from other boards, drop it from boards which use a chipset newer than Sandy/Ivy Bridge. Change-Id: If2f61d09082806b461878a76b286204ae56bf0eb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2022-07-23soc/intel/cannonlake: Set MAX_CPUS based on the SoC and PCHFelix Singer
Set the default value for MAX_CPUS in the SoC config and drop it from the mainboards where it is set to those values. Change-Id: Ib56fdcfe770ef736a2c5e183481d9f9966570e6d Signed-off-by: Felix Singer <felixsinger@posteo.net> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-16mb/system76/oryp5: Configure dGPU GPIOs in bootblockTim Crawford
Configure the dGPU power and reset pins in bootblock instead of ramstage. This fixes a conflict with our downstream driver, which configures these pins to enable dGPU power in romstage. Behavior remains unchanged without the driver as the dGPU is left powered off. Change-Id: Ica5ad5adc20fc2629d913b76a5a781fbd59a569d Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-07-16mb/system76/oryp5: Reset HDA before configuringTim Crawford
The oryp5 has several issues with audio output after a reboot: - The device is not in GNOME sound settings - The device is in GNOME sound settings, but there is no audio output - The speaker output is significantly louder than normal Reset the audio codec to resolve these issues. Tested on Pop!_OS 22.04 with Linux 5.17.15. Change-Id: I42f642820bba82142ff370930f0a25e9d1025588 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-07-16ec/system76/ec: Provide charging thresholds by defaultTim Crawford
Battery charging thresholds are a firmware implementation and not dependent on any hardware. It is expected that all boards using System76 EC firmware will select this option, so enable it by default. Leave it disabled on clevo/cml-u, which didn't have it selected. Change-Id: Id99d36eaf055a76b9e1eb732174017651de299a5 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-04-21tpm: Refactor TPM Kconfig dimensionsJes B. Klinke
Break TPM related Kconfig into the following dimensions: TPM transport support: config CRB_TPM config I2C_TPM config SPI_TPM config MEMORY_MAPPED_TPM (new) TPM brand, not defining any of these is valid, and result in "generic" support: config TPM_ATMEL (new) config TPM_GOOGLE (new) config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE) config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE) What protocol the TPM chip supports: config MAINBOARD_HAS_TPM1 config MAINBOARD_HAS_TPM2 What the user chooses to compile (restricted by the above): config NO_TPM config TPM1 config TPM2 The following Kconfigs will be replaced as indicated: config TPM_CR50 -> TPM_GOOGLE config MAINBOARD_HAS_CRB_TPM -> CRB_TPM config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE Signed-off-by: Jes B. Klinke <jbk@chromium.org> Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-21mb/system76/*: Enable measured bootTim Crawford
Tested by checking PCR-2 data is recorded in cbmem log. Change-Id: I70cb9a93de44e75f3a3ed24979c243fccea1213d Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-11-23mb/system76/*: Enable dGPU temp/fan reportingTim Crawford
Select the EC option on boards with dGPUs to report GPU temperature and fan data. Tested on system76/oryp6. The GPU fan speed is reported in sensors when the system is under load. system76_acpi-acpi-0 Adapter: ACPI interface CPU fan: 1985 RPM GPU fan: 2348 RPM CPU temp: +68.0°C GPU temp: +0.0°C Change-Id: Ieb45dc277c7eb11be1c50b9a9e3e20e3a88578b7 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-11-23mb/system76/*: Disable IME by CMOS optionTim Crawford
Add CMOS option to set IME mode. Default to "Disable" for CNL and TGL-H, and "Enable" for TGL-U. Not set for KBL, which uses ME_CLEANER. The HECI device must be enabled in devicetree for switching modes to function correctly. Change-Id: I3163dcb0a4af020c2cf6f94f2bb26380f17c253e Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-11-04mb/system76/*: Enable HECI deviceTim Crawford
The HECI device needs to be enabled to send the commands to have the CSME change between Soft Temporary Disable mode and Normal mode. Change-Id: I668507e3b522137bcc827aa615dab1fccd1709a0 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-11-02mb/system76/*: CMOS: Drop power_on_after_fail optionTim Crawford
Our boards do not boot if power_on_after_fail=Disable. Drop the option and use the default of powering on. Change-Id: Ia1857e52f838337048f79f8ca5c12d669cae321a Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-09-10cannonlake mainboards: Set PMC as hidden in devicetreeTim Wawrzynczak
FSP-S hides the PMC from the PCI bus when it runs, but there are still initialization steps coreboot programs for the PMC. Therefore, change all of the cannonlake mainboards to set the PMC as hidden in the devicetree, which means the device will be skipped during enumeration, but device callbacks are still issued as if the device were enabled. TEST=Ran full patch train on google/dratini, disassembled SSDT and the PEPD device matches what is in pep.asl. Also verified via dmesg that the INT33A1 device is still initialized by the kernel. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib4a20ce9075ce7653388a5d3e281fe774bf89355 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-03src/*: Specify type of `DIMM_MAX` onceAngel Pons
Specify the type of the `DIMM_MAX` Kconfig symbol once. Change-Id: I2e86baaa8bd50c7b82c399fde5dcea05da6b4307 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-09-02mb/system76/*: cmos.layout: Reserve century byteTim Crawford
Windows will write to the century byte (0x32), causing the option table checksum to be invalid and reset all options to their default values. Move options and checksum to start after the century byte. Change-Id: Ia395acacda1e251251c880587bbf61d7ee81ba3d Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-08-28soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by defaultFelix Singer
Since all mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, make it the default by changing its enum value to 0 and remove its configuration from all related devicetrees. If `common_soc_config.chipset_lockdown` is not configured with something else in the devicetree, then `CHIPSET_LOCKDOWN_COREBOOT` is used. Also, add a release note for the upcoming 4.15 release. Change-Id: I369f01d3da2e901e2fb57f2c83bd07380f3946a6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-12mb/system76/*: Add CMOS option tableTim Crawford
System76 uses several custom CMOS values downstream. Reduce our diff by providing a generic layout with the defaults: boot_option=Fallback debug_level=Debug power_on_after_fail=Enable Tested on galp3-c, gaze15, oryp5, oryp6. All boards boot multiple times with USE_OPTION_TABLE selected. Change-Id: Ie57b0e5713bba8ad46e1a4123a3ddd43e0eea964 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-07-26mb/*: Specify type of `MAINBOARD_PART_NUMBER` onceAngel Pons
Specify the type of the `MAINBOARD_PART_NUMBER` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I3692f9e82fe90af4d0da1d037018a20aa1b45793 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56554 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `MAINBOARD_DIR` onceAngel Pons
Specify the type of the `MAINBOARD_DIR` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: If1cc538b0c4938dac193699897b690e402b3c1e8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56553 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26src/*: Specify type of `CBFS_SIZE` onceAngel Pons
There's no need to specify the type of the `CBFS_SIZE` Kconfig symbol more than once. This is done in `src/Kconfig`, along with its prompt. Change-Id: I9e08e23e24e372e60c32ae8cd7387ddd4b618ddc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56552 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-23mb/system76/oryp5: Leave NC GPIOs unterminatedTim Crawford
Remove the unneeded pull up, as leaving them unterminated disconnects them from internal logic. Also replace use of PAD_CFG_TERM_GPO with PAD_CFG_GPO where no termination is used. Change-Id: Ia85ea39d46d7d9584b94726a7d601ca06826b1d1 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-22soc/intel/cannonlake: Set DIMM_SPD_SIZE to 512Felix Singer
All related mainboards are setting DIMM_SPD_SIZE to 512. Therefore, default to 512 in the SoC Kconfig and drop it from related mainboard Kconfigs. Change-Id: Idb6a0e42961eeb490afd76b4aa7d940961991733 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52513 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-15mb/system76/oryp5: Enable TAS5825M smart ampTim Crawford
Allows using the internal speakers of the oryp5. Smart AMP data was collected using a logic analyzer connected to the IC during system start on proprietary firmware. This data is then used to generate a C file [1]. [1]: https://github.com/system76/smart-amp Change-Id: I148f18ff3e754d913bdf907121b103c6de02ffc3 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47962 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-12mb/*: drop LPC generic range for port 80Michael Niewöhner
Port 80 (actually 0x80-0x8f) is a fixed I/O range and thus does not have to be set up as generic range. Drop the entries from the devicetrees. Change-Id: I8a54d3c35a321a2d57bd846662f7339eff53e5a8 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-04-06mb/system76: acpi: Remove unused EC defineTim Crawford
The define for color keyboard setting has never been used, as it was added as a Kconfig selection when ec/system76/ec was introduced. Change-Id: Ib83d4510c14ddf083660e42175ab093403792cac Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-01-28mb/system76/oryp5: Fix up DSDTPatrick Georgi
We started depending on dsdt_top.asl in dsdt.asl but this newly added board wasn't adapted yet, so have it catch up. Change-Id: If00280a33fd9e5c3ef1b3d07c41e81ed18013714 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50021 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28mb/system76/oryp5: Add System76 Oryx Pro 5Tim Crawford
Tested with TianoCore payload (UefiPayloadPkg). Working: - PS/2 keyboard, touchpad - Both DIMM slots - Both NVMe ports - SATA port - All USB ports - Webcam - Ethernet - Integrated graphics - Internal microphone - S3 suspend/resume - Flashing with flashrom - Booting to Ubuntu Linux and Windows Not working: - Discrete/Hybrid graphics - Internal speakers These two require new drivers to work correctly, which will be added and enabled later. Change-Id: Iae6e530dcd52df3642cdfe74b65bfff5aa0dd402 Signed-off-by: Tim Crawford <tcrawford@system76.com> Signed-off-by: Jeremy Soller <jeremy@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-15 14:23:48 +0000