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2024-08-01mb/starlabs/starbook/rpl: Merge and alphabetise FSP UPDsSean Rhodes
Change-Id: I3c4a963b233f549c7a76c76333af87c887550ac3 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-08-01mb/starlabs/*: Add the subsystem ids for HDASean Rhodes
The Windows drivers require the subsystem ID to match on the PCI device, so set these to allow the driver to install. Change-Id: I01b36554d5322018efc72734a8e749cc06263577 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83621 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-26mb/starlabs/starbook/rpl: Don't set tcss_aux_oriSean Rhodes
Not setting tcss_aux_ori in devicetree is the same as setting it to zero so remove it. Change-Id: Ia0e90179dd05b23f1f36935be51327250c5a8684 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-07-26mb/starlabs/starbook/cml: Drop superfluous devices from devicetreeFelix Singer
In order to clean up a bit, drop devices which are equivalent to the ones from chipset devicetree. Change-Id: I92765b404508901c7e84fad0bca30489cf69abac Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83456 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-18tgl,adl,rpl mainboards: Drop superfluous cpu_cluster deviceFelix Singer
The cpu_cluster device is defined in the chipset devicetree. So drop it from the mainboards. Change-Id: Ib84e7804c03f1c0779ab7053a09e397a267a3844 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83523 Reviewed-by: Tim Crawford <tcrawford@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-13cfl/cml/whl mainboards: Drop superfluous cpu_cluster deviceFelix Singer
The cpu_cluster device is defined in the chipset devicetree. So drop it from the mainboards. Change-Id: I65bfeaf0b8771c123c0615531c2cc608b222949b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83440 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-23skl mainboards: Move cpu_cluster device to chipset devicetreeFelix Singer
Change-Id: I7114612e686a0bf3cfc241f45fa62077fad16f5a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-06-08tree: Remove unused <option.h>Elyes Haouas
Change-Id: Ia3df14ebd365c00902b5d2ba300d8ade4c2d6c26 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2024-06-07mb/starlabs/*: Add Kconfig values for battery informationSean Rhodes
Add Kconfig strings for the battery: * Model * OEM * Technology Change-Id: Ibbce87ad54874f490af45c41f31956a7e9e996f3 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81401 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-07mb/starlabs/labtop/cml: Increase TCC OffsetSean Rhodes
These values were configured based on a default value of 110, but for CML, it's actually 100. Adjust it accordingly. Change-Id: Ibffeeab67a7277625db9bdedca36d759ff0e72f6 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81414 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-07mb/starlabs/starbook/kbl: Configure the TCC Offset based on Power ProfileSean Rhodes
Configure the TCC Offset based on the active power profile Change-Id: I58940441a7cefc7a2a07e5e9f7e8a15cb8730ef3 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-06-07mb/starlabs/starbook/kbl: Use function for getting power profileSean Rhodes
All other variants use a function and definitions to get the power profile. Make this board to the same. Change-Id: I07ce71e20bd71229bb0cd3438ab59140cd0d8b42 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81412 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-07mb/starlabs/starbook/cml: Switch to the merlin ECSean Rhodes
Change-Id: I27062c38c10df1d03f563b2f5391f79a3b6ee4fe Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81411 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-07mb/**/hda_verb: Use `AZALIA_PIN_CFG_NC(0)`Angel Pons
Replace `0x411111f0` with `AZALIA_PIN_CFG_NC(0)`, which evaluates to the same value and conveys additional information to the reader. Done with a bulk search and replace operation. Change-Id: Ibd84daec017bc1ab1ee4edd906fda80231c134cc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-06-06mb/starlabs/starbook: Prefer include <soc/gpio.h> via <gpio.h>Elyes Haouas
Change-Id: I972516443bc57e193aefd54516ca994087d92054 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2024-06-04mb/starlabs/lite: Prefer include <soc/gpio.h> via <gpio.h>Elyes Haouas
Change-Id: Ib8f7ac7e586390a1d25cbe84d6d4c3ba31ff078f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2024-04-11tree: Drop unused <string.h>Elyes Haouas
Change-Id: I0e216cbc4acf9571c65c345a1764e74485f89438 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81818 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-09tree: Drop unused <console/console.h>Elyes Haouas
Change-Id: Ib1a8fc50217c84e835080c70269ff50fc001392c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81811 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-22mb/starlabs/starbook: Correct alphabetisation of Kconfig optionsSean Rhodes
Change-Id: I7626fe9d4740e9f141a674fa457b0714fc38ed91 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-22mb/starlabs/starbook/adl: Set RP9 detection timeout to 50msSean Rhodes
Certain SSDs are not detected in the default time window, so change this to 50ms to allow these SSDs to be detected. Change-Id: I60e66096ef9ea0146a1bc72c5c74234353509439 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81398 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-22mb/starlabs/starbook/adl: Disable the Clock Request 4 GPIOSean Rhodes
The CPU port is not used so disable it. Change-Id: Ia150f99c4679323f08e44b0885af04113dfabd87 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-22mb/starlabs/starbook/{adl,rpl}: Correct the ClkReq GPIO commentsSean Rhodes
Change-Id: I8dc80c5bdde61f3c2dc5c9dc67fbc752de7a103f Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-22Revert "mb/starlabs/starbook/{adl,rpl}: Disable GpioOverride"Sean Rhodes
This reverts commit 8902dfa2bdf33b8ae69fa0d5161b28f67f8c0881. This was originally assumed to be an FSP/Descriptor/PMC mismatch but it turns out that the problem was coreboot incorrectly detecting ASPM support on devices. Revert so that a proper fix can be applied. Change-Id: I3f83e79c1b21a6c3799abed4a279b8bd59ac3570 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81395 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-22mb/starlabs/starbook/adl: Correct the layoutSean Rhodes
Adjust the size of the ME partition to match the descriptor Change-Id: Ibdec5121518452ec16cebcc4f2fb563355373be3 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81394 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-22mb/starlabs/starbook/{adl,rpl}: Disable CNViSean Rhodes
No variants were ever built with CNVi cards, so disable this device. Change-Id: I3725465eae0c7ade3dafa03add151353818ee761 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-02-19mb/starlabs/starbook: Always include the tcss.aslSean Rhodes
The tcss.asl doesn't just relate to tcss, it is required for core scheduling, so include it for all platforms. Change-Id: I781ba8756e06133799e8d6d91302968cc3ea0a56 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80485 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-19soc/intel/tigerlake: Drop redundant PcieRpEnableNico Huber
The PcieRpEnable option is redundant to our on/off setting in the devicetrees. Let's use the common coreboot infrastructure instead. Thanks to Nicholas for doing all the mainboard legwork! Change-Id: Iacfef5f032278919f1fcf49e31fa42bcbf1eaf20 Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79920 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18mb/*: Add SPDX headers for cmos.default filesMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ib7beed7218f317bc2352b65a6191ef1cdaa0742d Reviewed-on: https://review.coreboot.org/c/coreboot/+/80597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2024-02-18mb/samsung to mb/up: Add SPDX license headers to Kconfig filesMartin Roth
Change-Id: Ied455ff29b151fb5f4bca26a189b1d4104d8cede Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80595 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-15mb/starlabs/starbook/rpl: Configure PMC muxSean Rhodes
Configure PMC mux in devicetree. This allows PD controllers to be used for both video and power delivery. Tested on StarBook Mk VI with Ubuntu Lunar, by checking a USB-C PD display can supply power and display video output. Change-Id: I580b148b036e62fbcab50d1ca2ab1ed021cfed6b Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-02-15mb/starlabs/starbook/adl: Configure PMC muxSean Rhodes
Configure PMC mux in devicetree. This allows PD controllers to be used for both video and power delivery. Tested on StarBook Mk VI with Ubuntu Lunar, by checking a USB-C PD display can supply power and display video output. Change-Id: I9e49612d7f165a9c9604093535f7b141a4c7048c Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79426 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-14mb/starlabs/starbook/kbl: Remove tcc_offset entrySean Rhodes
The TCC offset is configured in devtree.c, so remove it from the devicetree. Change-Id: I044a68854cc142b057cf31b4e2456d2ad1d0dd3a Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-01-24mb/lenovo to mb/squared: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I4790adb41cb62c8c8dd44261a2926dfb6350955a Reviewed-on: https://review.coreboot.org/c/coreboot/+/80111 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-01-19mb/starlabs/starbook/cml: Use chipset dt reference namesFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous. Change-Id: Ia004de6606a1685822d5567123887c60d89e3119 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2024-01-11mb/starlabs/starbook/rpl: Enable C1eSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3a317d031e71f86afc50b229d1b97197552f4fa9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-11-13mb/starlabs/starbook/kbl: Use chipset dt reference name for LPCFelix Singer
Change-Id: I41b3ed4926fe77c5729672fd7a7bcb8ca0c5c216 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79033 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-26mb/starlabs/*/Kconfig: Fix default power state after failureMatt DeVillier
POWER_STATE_OFF_AFTER_FAILURE can't be directly selected since it's a choice, so instead set POWER_STATE_DEFAULT_ON_AFTER_FAILURE to n, as it's functionally equivalent. This fixes the warnings generated by the pre-commit hook Kconfig check. It is necessary to override and set default n in the mainboard Kconfig as it is set to default y in src/soc/intel/common/block/pmc/Kconfig. TEST=select starlabs/starbook_adl in menuconfig and verify the default power-on setting is S5/soft off. Change-Id: I3ce33517dcc0af693b8db8d1de2926117ad3c16b Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78627 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-24mb/starlabs/starbook/{adl,rpl}: Disable GpioOverrideSean Rhodes
Disable the GpioOverride UPD in FSP M, and comment out the Clock Request GPIOs to ensure that coreboot doesn't touch them. This solves behaviour that can only be described as weird: * Devices connected to Root Ports don't initialise * Hang seen when entering S5 * Hang when edk2 is reached Change-Id: Idf8d2112a1c44064af73bb54fd3e1a1a429e0649 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-10-20mb/starlabs: Set POWER_STATE_OFF_AFTER_FAILURESean Rhodes
This Kconfig option is used as a failback when `get_uint_option` fails. It will fail after coreboot is flashed, as the cfr code has not yet setup the options. Change the default to OFF, so when it does fallback, it's the correct behaviour. Change-Id: I5d06047fe23322520e9c84ded8f1941f6d716a51 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-10-20mb/starlabs/starbook: Include ACPI for GNA scoring acceleratorSean Rhodes
Change-Id: Id42d07aabfd08c6c7a38515f9cf4b749750deecd Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78202 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-20mb/starlabs/starbook/adl: Enable PchHdaSdiEnableSean Rhodes
This is required for the HDA device to work. Change-Id: I5fd3617c4cb1e69b7e0ecf6cddf4c143da99b927 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78201 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-04mb/starlabs/starbook/{adl,rpl}: Remove unnecessary entriesSean Rhodes
Certain devices are enabled in Alder Lakes chipset.cb, so remove them from the devicetree. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I929af0bed6c2e1024b4787424a8fe466edce5a36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78198 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-04mb/starlabs/starbook/{adl,rpl}: Enable the CNVi deviceSean Rhodes
Change-Id: I1b0052b569b575fec7893322dec0280c9f1ed79f Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78197 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-04mb/starlabs/starbook/rpl: Update the VBT to 251Sean Rhodes
Updating FSP to v4301.01 caused a strange flicker when connecting an external display. Update the VBT to 251 from 242 with the exact same settings to resolve this. Change-Id: I36bb2cc92e744e761ec6af9c026c429373c1750a Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-09-08mb/starlabs/starbook/rpl: Enable the PD interrupt GPIOSean Rhodes
Enable the PD interrupt GPIO, GPP_B11, so that HPD works when Thunderbolt is disabled. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie37976d58921b7a12dff16d93d7ac9bdd92edbea Reviewed-on: https://review.coreboot.org/c/coreboot/+/77673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-08mb/starlabs/starbook/rpl: Correct GPP_A19Sean Rhodes
A19 was incorrectly labelled as TCP0 HPD. It is not connected so configure it accordingly. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I5aea723c2e8c0758d413bbc4bfd0ce92b22d0c87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-08mb/starlabs/starbook/{adl,rpl}: Remove unnecessary entriesSean Rhodes
Certain devices are enabled in Alder Lakes chipset.cb, so remove them from the devicetree. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I929af0bed6c2e1024b4787424a8fe466edce5a36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-01mb/starlabs/starbook/rpl: Disable dynamic Tc-cold handshakeSean Rhodes
With the Tc-cold handshake, there's a fast flicker when connecting external displays. With it disabled, it's just one "flick", so use this as it's lesser of two evils. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie42b935d3e69beff6a1e503a8dee69554123b4f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-08-17mb/starlabs/starbook/rpl: Fix the Thunderbolt cmos optionSean Rhodes
For Thunderbolt to be disabled, `UsbTcPortEn` and `TcssXhciEn` also need to be disabled. Change-Id: Ie02c1e0ea7583bbd78e25c8184e2cdf2b6281741 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-08-11mb/starlabs/starbook: Add Raptor Lake StarBook Mk VI variantSean Rhodes
Tested using `edk2` from `github.com/starlabsltd/edk2/tree/uefipayload_vs`: * Windows 11 * Ubuntu 22.04 * Manjaro 22 No known issues. https://starlabs.systems/pages/starbook-specification Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I7c92bf92ab4de546c3633fae7e19a302409508ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/74444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-08-10mb/starlabs/starbook: Add support for VBOOTSean Rhodes
Add the required files to support VBOOT for when it is enabled. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I842b79d8e144414ce42b3d0d9dfd2b5180ecf70d Reviewed-on: https://review.coreboot.org/c/coreboot/+/74230 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-10mb/starlabs/starbook/adl: Update the VBTSean Rhodes
Adjust the Type-C output ports to "Integrated Displayport" to comply with FSP 4221. Change-Id: Ifcb4a086106f90c70926f44a7566330efd185544 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-08-10mb/starlabs/lite/glkr: Disable PSRSean Rhodes
Disable PSR in the VBT to avoid flickering on kernels later than 5.15. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3640fcea73e278e6c8968a4b0c9ba7cf04a2361f Reviewed-on: https://review.coreboot.org/c/coreboot/+/77134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-08-10mb/starlabs/lite/glk: Disable PSRSean Rhodes
Disable PSR in the VBT to avoid flickering on kernels later than 5.15. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I5b58f4d26fa0032a5aed3af0db71a5daf41fdd8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/76941 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-10mb/starlabs/starbook/adl: Enable CNVi Bluetooth UPDsSean Rhodes
Enable "CnviBtCore" and "CnviBtAudioOffload" to increase bluetooth performance. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ibafabfaa39ba46620a2e06b288c457267f041ab0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-08-10mb/starlabs/starbook/adl: Enable the crashlog PCI deviceSean Rhodes
Change-Id: I8dc97ca0fb310417a28e253f378511f510c3b4b3 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77124 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-10mb/starlabs/starbook/tgl: Enable the crashlog PCI deviceSean Rhodes
Change-Id: I88831f56a259d45e3ae1f66abd1d7aaeac4ede20 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-08-10mb/starlabs/starbook/tgl: Use the merlin ec codeSean Rhodes
Switch the TGL variant to use the "merlin" EC variant, and delete the no longer needed "TGL" EC variant. This is not a functional change. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Id4d305490b48c1c79ea52b0bbaa79b675412e0b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76332 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-10mb/starlabs/starbook/adl: Use the merlin ec codeSean Rhodes
Switch the ADL variant to use the "merlin" EC variant, and delete the no longer needed "ADL" EC variant. This is not a functional change. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I61e56cc95a26be60d7f10c89d26bce2d857ae81a Reviewed-on: https://review.coreboot.org/c/coreboot/+/76313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-08-10mb/starlabs/starbook/adl: Correct the FMAPSean Rhodes
Specify the size of the ME region so that it matches the IFD. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I51ba0a7646ab72d4dd22b99519708649c78b25b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-10mb/starlabs/starbook: Select VALIDATE_INTEL_DESCRIPTORSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I5dac42fb2239e7bc14dbe45442cc562927973b24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-07-28mb/starlabs/starbook: Adjust TCC Offset for all boardsSean Rhodes
Lower the TCC Offset by 10 degress. Change-Id: Ib80d3b73c41ec1196d8294c35b43333e0df218d5 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76374 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-06mainboard/starlabs/*: Remove the power_on_after_fail optionSean Rhodes
None of these boards have an RTC battery, so this option has no effect. Remove it. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9a55227f74c0b9ae9b56bdef4b8f53b2425b331c Reviewed-on: https://review.coreboot.org/c/coreboot/+/75450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-06mainboard/starlabs/starbook: Unselect RESIZABLE_BARSSean Rhodes
It is not needed, so remove it. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I606d0a76926e90e4ce321163400aa50ea961c2a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75342 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-06-19soc/intel/apollolake: Switch to snake case for ModPhyIfValueMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'ModPhyIfValue'. Change-Id: I4cdf68e65cea4ab316af969cd6a8d096b456518d Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75855 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19soc/intel/apollolake: Switch to snake case for DisableComplianceModeMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'DisableComplianceMode'. Change-Id: I9d5605134a753f161a66857c7f78844ae7490cd6 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-03mb/starlabs/starbook: Fix the ramtop CMOS entrySean Rhodes
The ramtop entry has to be 10 bytes long, and it was incorrectly set to 10 bits, instead of 10 bytes. Change this to 80. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I506f9d98a389dd859038fd270c5e344b65f514f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75420 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-02soc/intel/apollolake: Switch to snake case for SataPortsEnableMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'SataPortsEnable'. Change-Id: I0df35125360eb42a03d5445011d72842cb2b8d7e Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75553 Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-05-23mb/starlabs/starbook: Add ramtop to CMOS layoutSean Rhodes
Add `ramtop` to CMOS layout so SOC_INTEL_COMMON_BASECODE_RAMTOP can be used. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I88128d2c62bdc3246a3f30e768c353f0fe3faeb7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-29mb/starlabs/starbook: Let coreboot configure ASPMSean Rhodes
FSP is fractionally faster at configuring ASPM (1,118,688 vs 1,122,205) but coreboot's configuration results in lower power consumption of approximately 0.5W when idling - the reason why is unknown. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib15eaede956f0aa55118d093fdff0fd9487df250 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74520 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-28mb/starlabs/starbook/adl: Correct the number of NID entriesSean Rhodes
The number of NID entries was too high for the Realtek and Intel sound cards, preventing the verb table from loading. Now the values are correct; it loads as intended. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I79825313a4801c120a0a2a321cbabab7c728aa71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-04-28mb/starlabs/starbook/adl: Correct port for Hot PlugSean Rhodes
Commit 5103b87a4d7b ("mb/starlabs/starbook/adl: Add an option to enable Hot Plug") introduced an option to enable Hot Plug for the SSD. The port was set to 4 (RP5) which is the wireless card. Change this to 8 (RP9) which is the SSD. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I884f4997d73e31bd422477952466f168afad66a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74738 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-20soc/intel/tigerlake: Replace TcssD3ColdDisable with D3COLD_SUPPORTSean Rhodes
Remove the `TcssD3ColdDisable` option in devicetree, as it exists in Kconfig. The setting is only used on `starlabs/starbook` which selects D3COLD_SUPPORT so the UPDs will not change. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I50e49e900c96748edd5b678765e47cc0e0d9b280 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74476 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-20soc/intel/tigerlake: Replace SOC_INTEL_TIGERLAKE_S3 with D3COLD_SUPPORTSean Rhodes
The Kconfig option SOC_INTEL_TIGERLAKE_S3 suggests that it's doing something with S3, but it's actually disabling D3Cold support. Remove it, and instead use D3COLD_SUPPORT so it's clear what the option is doing. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Id43f3e5c8620d474831cc02fcecebd8aac961687 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74405 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-19soc/intel/alderlake: Rename SOC_INTEL_ALDERLAKE_S3 to D3COLD_SUPPORTSean Rhodes
The Kconfig option SOC_INTEL_ALDERLAKE_S3 suggests that it's doing something with S3, but it's actually disabling D3Cold support. Rename it to D3COLD_SUPPORT to make it clear what it's doing. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ifc3f19912ac7ee55be8ec7a491598140f9532675 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-04-12Revert "soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORT"Michael Niewöhner
This reverts commit 6bfca1b689e48be4f72e8fa401f3558d845fc282. Reason for revert: dependency for revert CB:73903 Change-Id: I56bab4d85d04e90cacfe77db59d0cde6a8a75949 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-04-12mb/starlabs/starbook/adl: Enable OverCurrent 3 GPIOSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9971209539aa7b74e55673141902b6ad0d698e4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/73985 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-12mb/starlabs/starbook/adl: Fix OC pin configSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I1c4bdab44f0d73546f52614917dccbe71f0911a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73984 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-04mb/starlabs/*: Add CMOS entries for the mirror flagSean Rhodes
Add the required CMOS entries for the mirror flag, so that it can be enabled from a defconfig. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I174ac896df050480ee90c8141c5536b628c98432 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73682 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-04mb/starlabs/starbook/adl: Add an option to enable Hot PlugSean Rhodes
Some third-party SSDs, from Samsung and WD, such as the 990 Pro and WD Black 850X aren't initialised by coreboot, seemingly as coreboot is too quick; debug builds work, and enabling hotplug does. Add a cmos option `pci_hot_plug`, defaulting to enabled to allow these SSDs to work. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I680211bc87153a5e6005d58040a94725c0973451 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-04-04mb/starlabs/starbook: Disable ASPM in corebootSean Rhodes
ASPM is already configured by FSP so disable it in coreboot to reduce boot time by a whopping 34ms. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I073c68dafa9baa90e253b5230f84b0de6a7e5c47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73982 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-04-04mb/starlabs/starbook/adl: Remove Soundwire workaroundSean Rhodes
This was added to solve Debian 10 not booting. Debian 10, which now isn't the latest stable version works, so remove the workaround that was included in the original port. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic11f355eb218ff3bad00fff83537c99c1b6985bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/72669 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-04Revert "mb/starlabs/*: Remove sleepstates.asl"Sean Rhodes
This reverts commit ac69ce91229dee68d4135c596f49cf9e5efbe1e9. Reason for revert: Removing breaks suspend in kernels > 6.2 and Windows. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3e90266e66192b328b9af51c5e614774a248ddf0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
2023-04-02soc/intel/alderlake: Add ADL-P 4+4 with 28W TDPPatrick Rudolph
Add the 28W TDP version of the ADL-P with MCHID 0x4629. Verified that all 28W SoCs have the same PL1/PL2 defined in Intel document #655258 "12th Generation Intel Core Processors Datasheet, Volume 1 of 2". Fixes the error seen in coreboot log: [ERROR] unknown SA ID: 0x4629, skipped power Limit Configuration Change-Id: Iad676f083dfd1cceb4df9435d467dc0f31a63f80 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-03-26mb/starlabs/*: Remove sleepstates.aslSean Rhodes
Remove the sleepstates.asl as it was written for SOCs pre-Skylake and not needed. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I46fe934c2a50b3d61575f66f0881ab6754fe8dc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-03-10mb/starlabs/starbook/adl: Enable ASPMSean Rhodes
Enable ASPM for RP5 (wireless) and RP9 (SSD). Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I428040caf171bdcfedc285cdeddc55bcbec40f3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/72753 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-10mb/starlabs/starbook/{tgl,adl}: Set DmiMaxLinkSpeed to 4Sean Rhodes
Set DmiMaxLinkSpeed to 4 in FSP to ensure that FSP always supports PCIe Gen 4 drives. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I0e31919122dacfbdc2486fa8216a28b479f3bd00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-09Revert "ec/starlabs/merlin: Add support for enabling the mirror flag"Sean Rhodes
This reverts commit b42ca4d0b2fafe7214396d30a1a833ac33cf85bc. Reason for revert: The mirror flag "0x01" is mirror once, which relies on the EC remembering that it's been mirrored. However, the EC forgets this if it's been without power for 20 minutes or so. Even if power is connected then, it'll instantly try to mirror and it can't charge whilst doing it. It can either result in incomplete EC firmware, or a loop where it's constantly trying to mirror. Change-Id: I79da9143cc63459e7e29431eff2cb14200424b37 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-09Revert "mb/starlabs/*: Enable the Mirror flag for boards that support"Sean Rhodes
This reverts commit 35354583cdc94ced026975ced5170e1c094b258e. Reason for revert: The mirror flag "0x01" is mirror once, which relies on the EC remembering that it's been mirrored. However, the EC forgets this if it's been without power for 20 minutes or so. Even if power is connected then, it'll instantly try to mirror and it can't charge whilst doing it. It can either result in incomplete EC firmware, or a loop where it's constantly trying to mirror. Change-Id: Ie82cbafd4bea2416526e2847738802a05ed45582 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-02mb/starlabs/starbook/adl: Enable the PchHdaAudioLinkHdaEnable UPDSean Rhodes
Enable the PchHdaAudioLinkHdaEnable UPD so that the sound works. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie3493af340a42035ee537d83b1542be1b87d8f9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/71979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2023-02-20soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORTSean Rhodes
Select NO_S0IX_SUPPORT for `starlabs/starbook` and `atlas/prodrive` so their configurations are unchanged. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I718952165daa6471f11e8025e745fe7c249d3b46 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72800 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-19treewide: Remove useless "_STA: Status" commentElyes Haouas
Change-Id: I99ded00fa6dadb494c1523d00063dbc1fde95614 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73093 Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-17treewide: Remove unuseful "_UID: Unique ID" commentElyes Haouas
Change-Id: I150a4ed94bcaead6eb45f1c4b4952ae6957e0940 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17treewide: Remove unuseful "_CID: Compatible ID" commentElyes Haouas
Change-Id: I7db69e2faf412b9c6732f6dfc362d5774094ef27 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17treewide: Remove unuseful "_HID: Hardware ID" commentElyes Haouas
Change-Id: I5eb1424e9e6c1fbf20cd0bf68fbb52e1ec97f905 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-04mb/starlabs/starbook/adl: Enable HPD GPIOSean Rhodes
Enable the HPD GPIO so that the USB-C port can be used for DisplayPort. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If93d08f64cf7b09bb47622bdc7f22280b8a48174 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72431 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-03soc/intel/apl: Move cpu cluster to chipset.cbArthur Heymans
Change-Id: I7eaf625e5acfcefdae7c81e186de36b42c06ee67 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-01-30mb/*: Remove lapic from devicetreeArthur Heymans
The parallel mp code picks up lapics at runtime, so remove it from all devicetrees that use this codebase. Change-Id: I5258a769c0f0ee4bbc4facc19737eed187b68c73 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69303 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-27mb/starlabs/starbook/adl: Fix the disable wireless CMOS optionSean Rhodes
The current CMOS option causes Linux to not boot, as the GRUB EFI loader will report an incorrect parameter. Update the CMOS option so that the corresponding UPD is changed when the wireless is set to disable, so that the root port for the wireless is also disabled. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I607d700319d6a58618ec95b3440e695c82dff196 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71896 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-27mb/starlabs/starbook/adl: Make Type-C USB a standard portSean Rhodes
Change the Type-C USB 2.0 interface to a standard port, as the Type-C macro will not work in Linux (dmesg says the cable is faulty), This makes the port work reliably in Linux, tested with: * Manjaro 21 * Ubuntu 22.04 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I6dbf31b6e4603685297e9e5203b0db6ac1b9e24a Reviewed-on: https://review.coreboot.org/c/coreboot/+/72387 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-15 02:00:34 +0000