diff options
| author | Sean Rhodes <sean@starlabs.systems> | 2023-09-05 15:35:37 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-10-04 09:37:09 +0000 |
| commit | de61edde1b340b245139b3dc89f1f205fb1a1994 (patch) | |
| tree | 7e0fc0922fcb5e33dedcb521ecd994bdce94619a /src/mainboard/starlabs | |
| parent | cc3b2db82f9479c4973b4ce6587dfda03c1fffde (diff) | |
mb/starlabs/starbook/{adl,rpl}: Remove unnecessary entries
Certain devices are enabled in Alder Lakes chipset.cb, so remove
them from the devicetree.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I929af0bed6c2e1024b4787424a8fe466edce5a36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78198
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/starlabs')
| -rw-r--r-- | src/mainboard/starlabs/starbook/variants/adl/devicetree.cb | 1 | ||||
| -rw-r--r-- | src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb | 1 |
2 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb index ed48757433..50c54b9637 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb @@ -93,7 +93,6 @@ chip soc/intel/alderlake device generic 0 on end end end - device ref heci1 on end device ref sata on register "sata_salp_support" = "1" register "sata_ports_enable[1]" = "1" diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb index 976f990c80..1eaab18938 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb @@ -113,7 +113,6 @@ chip soc/intel/alderlake device generic 0 on end end end - device ref heci1 on end device ref pcie_rp5 on # WiFi chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" |