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2023-07-28mb/starlabs/starbook: Adjust TCC Offset for all boardsSean Rhodes
Lower the TCC Offset by 10 degress. Change-Id: Ib80d3b73c41ec1196d8294c35b43333e0df218d5 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76374 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-06mainboard/starlabs/*: Remove the power_on_after_fail optionSean Rhodes
None of these boards have an RTC battery, so this option has no effect. Remove it. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9a55227f74c0b9ae9b56bdef4b8f53b2425b331c Reviewed-on: https://review.coreboot.org/c/coreboot/+/75450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-06mainboard/starlabs/starbook: Unselect RESIZABLE_BARSSean Rhodes
It is not needed, so remove it. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I606d0a76926e90e4ce321163400aa50ea961c2a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75342 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-06-19soc/intel/apollolake: Switch to snake case for ModPhyIfValueMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'ModPhyIfValue'. Change-Id: I4cdf68e65cea4ab316af969cd6a8d096b456518d Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75855 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19soc/intel/apollolake: Switch to snake case for DisableComplianceModeMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'DisableComplianceMode'. Change-Id: I9d5605134a753f161a66857c7f78844ae7490cd6 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-03mb/starlabs/starbook: Fix the ramtop CMOS entrySean Rhodes
The ramtop entry has to be 10 bytes long, and it was incorrectly set to 10 bits, instead of 10 bytes. Change this to 80. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I506f9d98a389dd859038fd270c5e344b65f514f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75420 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-02soc/intel/apollolake: Switch to snake case for SataPortsEnableMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'SataPortsEnable'. Change-Id: I0df35125360eb42a03d5445011d72842cb2b8d7e Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75553 Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-05-23mb/starlabs/starbook: Add ramtop to CMOS layoutSean Rhodes
Add `ramtop` to CMOS layout so SOC_INTEL_COMMON_BASECODE_RAMTOP can be used. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I88128d2c62bdc3246a3f30e768c353f0fe3faeb7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-29mb/starlabs/starbook: Let coreboot configure ASPMSean Rhodes
FSP is fractionally faster at configuring ASPM (1,118,688 vs 1,122,205) but coreboot's configuration results in lower power consumption of approximately 0.5W when idling - the reason why is unknown. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib15eaede956f0aa55118d093fdff0fd9487df250 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74520 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-28mb/starlabs/starbook/adl: Correct the number of NID entriesSean Rhodes
The number of NID entries was too high for the Realtek and Intel sound cards, preventing the verb table from loading. Now the values are correct; it loads as intended. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I79825313a4801c120a0a2a321cbabab7c728aa71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-04-28mb/starlabs/starbook/adl: Correct port for Hot PlugSean Rhodes
Commit 5103b87a4d7b ("mb/starlabs/starbook/adl: Add an option to enable Hot Plug") introduced an option to enable Hot Plug for the SSD. The port was set to 4 (RP5) which is the wireless card. Change this to 8 (RP9) which is the SSD. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I884f4997d73e31bd422477952466f168afad66a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74738 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-20soc/intel/tigerlake: Replace TcssD3ColdDisable with D3COLD_SUPPORTSean Rhodes
Remove the `TcssD3ColdDisable` option in devicetree, as it exists in Kconfig. The setting is only used on `starlabs/starbook` which selects D3COLD_SUPPORT so the UPDs will not change. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I50e49e900c96748edd5b678765e47cc0e0d9b280 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74476 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-20soc/intel/tigerlake: Replace SOC_INTEL_TIGERLAKE_S3 with D3COLD_SUPPORTSean Rhodes
The Kconfig option SOC_INTEL_TIGERLAKE_S3 suggests that it's doing something with S3, but it's actually disabling D3Cold support. Remove it, and instead use D3COLD_SUPPORT so it's clear what the option is doing. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Id43f3e5c8620d474831cc02fcecebd8aac961687 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74405 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-19soc/intel/alderlake: Rename SOC_INTEL_ALDERLAKE_S3 to D3COLD_SUPPORTSean Rhodes
The Kconfig option SOC_INTEL_ALDERLAKE_S3 suggests that it's doing something with S3, but it's actually disabling D3Cold support. Rename it to D3COLD_SUPPORT to make it clear what it's doing. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ifc3f19912ac7ee55be8ec7a491598140f9532675 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-04-12Revert "soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORT"Michael Niewöhner
This reverts commit 6bfca1b689e48be4f72e8fa401f3558d845fc282. Reason for revert: dependency for revert CB:73903 Change-Id: I56bab4d85d04e90cacfe77db59d0cde6a8a75949 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-04-12mb/starlabs/starbook/adl: Enable OverCurrent 3 GPIOSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9971209539aa7b74e55673141902b6ad0d698e4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/73985 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-12mb/starlabs/starbook/adl: Fix OC pin configSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I1c4bdab44f0d73546f52614917dccbe71f0911a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73984 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-04mb/starlabs/*: Add CMOS entries for the mirror flagSean Rhodes
Add the required CMOS entries for the mirror flag, so that it can be enabled from a defconfig. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I174ac896df050480ee90c8141c5536b628c98432 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73682 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-04mb/starlabs/starbook/adl: Add an option to enable Hot PlugSean Rhodes
Some third-party SSDs, from Samsung and WD, such as the 990 Pro and WD Black 850X aren't initialised by coreboot, seemingly as coreboot is too quick; debug builds work, and enabling hotplug does. Add a cmos option `pci_hot_plug`, defaulting to enabled to allow these SSDs to work. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I680211bc87153a5e6005d58040a94725c0973451 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-04-04mb/starlabs/starbook: Disable ASPM in corebootSean Rhodes
ASPM is already configured by FSP so disable it in coreboot to reduce boot time by a whopping 34ms. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I073c68dafa9baa90e253b5230f84b0de6a7e5c47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73982 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-04-04mb/starlabs/starbook/adl: Remove Soundwire workaroundSean Rhodes
This was added to solve Debian 10 not booting. Debian 10, which now isn't the latest stable version works, so remove the workaround that was included in the original port. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic11f355eb218ff3bad00fff83537c99c1b6985bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/72669 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-04Revert "mb/starlabs/*: Remove sleepstates.asl"Sean Rhodes
This reverts commit ac69ce91229dee68d4135c596f49cf9e5efbe1e9. Reason for revert: Removing breaks suspend in kernels > 6.2 and Windows. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3e90266e66192b328b9af51c5e614774a248ddf0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
2023-04-02soc/intel/alderlake: Add ADL-P 4+4 with 28W TDPPatrick Rudolph
Add the 28W TDP version of the ADL-P with MCHID 0x4629. Verified that all 28W SoCs have the same PL1/PL2 defined in Intel document #655258 "12th Generation Intel Core Processors Datasheet, Volume 1 of 2". Fixes the error seen in coreboot log: [ERROR] unknown SA ID: 0x4629, skipped power Limit Configuration Change-Id: Iad676f083dfd1cceb4df9435d467dc0f31a63f80 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-03-26mb/starlabs/*: Remove sleepstates.aslSean Rhodes
Remove the sleepstates.asl as it was written for SOCs pre-Skylake and not needed. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I46fe934c2a50b3d61575f66f0881ab6754fe8dc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-03-10mb/starlabs/starbook/adl: Enable ASPMSean Rhodes
Enable ASPM for RP5 (wireless) and RP9 (SSD). Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I428040caf171bdcfedc285cdeddc55bcbec40f3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/72753 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-10mb/starlabs/starbook/{tgl,adl}: Set DmiMaxLinkSpeed to 4Sean Rhodes
Set DmiMaxLinkSpeed to 4 in FSP to ensure that FSP always supports PCIe Gen 4 drives. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I0e31919122dacfbdc2486fa8216a28b479f3bd00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-09Revert "ec/starlabs/merlin: Add support for enabling the mirror flag"Sean Rhodes
This reverts commit b42ca4d0b2fafe7214396d30a1a833ac33cf85bc. Reason for revert: The mirror flag "0x01" is mirror once, which relies on the EC remembering that it's been mirrored. However, the EC forgets this if it's been without power for 20 minutes or so. Even if power is connected then, it'll instantly try to mirror and it can't charge whilst doing it. It can either result in incomplete EC firmware, or a loop where it's constantly trying to mirror. Change-Id: I79da9143cc63459e7e29431eff2cb14200424b37 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-09Revert "mb/starlabs/*: Enable the Mirror flag for boards that support"Sean Rhodes
This reverts commit 35354583cdc94ced026975ced5170e1c094b258e. Reason for revert: The mirror flag "0x01" is mirror once, which relies on the EC remembering that it's been mirrored. However, the EC forgets this if it's been without power for 20 minutes or so. Even if power is connected then, it'll instantly try to mirror and it can't charge whilst doing it. It can either result in incomplete EC firmware, or a loop where it's constantly trying to mirror. Change-Id: Ie82cbafd4bea2416526e2847738802a05ed45582 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-02mb/starlabs/starbook/adl: Enable the PchHdaAudioLinkHdaEnable UPDSean Rhodes
Enable the PchHdaAudioLinkHdaEnable UPD so that the sound works. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie3493af340a42035ee537d83b1542be1b87d8f9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/71979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2023-02-20soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORTSean Rhodes
Select NO_S0IX_SUPPORT for `starlabs/starbook` and `atlas/prodrive` so their configurations are unchanged. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I718952165daa6471f11e8025e745fe7c249d3b46 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72800 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-19treewide: Remove useless "_STA: Status" commentElyes Haouas
Change-Id: I99ded00fa6dadb494c1523d00063dbc1fde95614 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73093 Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-17treewide: Remove unuseful "_UID: Unique ID" commentElyes Haouas
Change-Id: I150a4ed94bcaead6eb45f1c4b4952ae6957e0940 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17treewide: Remove unuseful "_CID: Compatible ID" commentElyes Haouas
Change-Id: I7db69e2faf412b9c6732f6dfc362d5774094ef27 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17treewide: Remove unuseful "_HID: Hardware ID" commentElyes Haouas
Change-Id: I5eb1424e9e6c1fbf20cd0bf68fbb52e1ec97f905 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-04mb/starlabs/starbook/adl: Enable HPD GPIOSean Rhodes
Enable the HPD GPIO so that the USB-C port can be used for DisplayPort. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If93d08f64cf7b09bb47622bdc7f22280b8a48174 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72431 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-03soc/intel/apl: Move cpu cluster to chipset.cbArthur Heymans
Change-Id: I7eaf625e5acfcefdae7c81e186de36b42c06ee67 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-01-30mb/*: Remove lapic from devicetreeArthur Heymans
The parallel mp code picks up lapics at runtime, so remove it from all devicetrees that use this codebase. Change-Id: I5258a769c0f0ee4bbc4facc19737eed187b68c73 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69303 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-27mb/starlabs/starbook/adl: Fix the disable wireless CMOS optionSean Rhodes
The current CMOS option causes Linux to not boot, as the GRUB EFI loader will report an incorrect parameter. Update the CMOS option so that the corresponding UPD is changed when the wireless is set to disable, so that the root port for the wireless is also disabled. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I607d700319d6a58618ec95b3440e695c82dff196 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71896 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-27mb/starlabs/starbook/adl: Make Type-C USB a standard portSean Rhodes
Change the Type-C USB 2.0 interface to a standard port, as the Type-C macro will not work in Linux (dmesg says the cable is faulty), This makes the port work reliably in Linux, tested with: * Manjaro 21 * Ubuntu 22.04 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I6dbf31b6e4603685297e9e5203b0db6ac1b9e24a Reviewed-on: https://review.coreboot.org/c/coreboot/+/72387 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-26mb/starlabs/starbook/Kconfig: Move MAINBOARD_HAS_TPM2 to STARBOOK_SERIESElyes Haouas
Change-Id: I5f91ae1b5904405edd797b57fbeb46609301295c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72434 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-25mb/starlabs/starbook/adl: Enable pin widget 0x18Sean Rhodes
Enable pin 0x18 which is used for the 3.5mm combo jack microphone detection. Also, disable 0x17 as it is not used. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I05856627c073acaff49ea1ddc048a49a74b6268f Reviewed-on: https://review.coreboot.org/c/coreboot/+/71718 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-25mb/starlabs/starbook/adl: Change HDA verb hex values to lower caseSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I6a5c54ac46840fc1e03eb15b9ae2ddc34172ec08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72011 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-17mb/starlabs/starbook/adl: Fix alignmentSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4a3f871f2418438ef8e780a39935dfa2f86d8dbb Reviewed-on: https://review.coreboot.org/c/coreboot/+/71895 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-16Revert "mb/starlabs/starbook/adl: Enable the PchHdaAudioLinkHdaEnable UPD"Martin L Roth
This reverts commit 0e945a3426782e3c054a920ff8be3cd865f697ba. Reason for revert: Breaks build. Need to be merged after https://review.coreboot.org/c/coreboot/+/71715 which adds the register that this patch enables Signed-off-by: Martin L Roth <gaumless@gmail.com> Change-Id: I0ac3fb1a44e23e19c9711287f3a6a8402a6ffd79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71283 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-16mb/starlabs/starbook/adl: Enable the PchHdaAudioLinkHdaEnable UPDSean Rhodes
Enable the PchHdaAudioLinkHdaEnable UPD so that the sound works. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Id53c9a6495d584c374e89b76d1fd4258654b6f95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2023-01-07mb/starlabs: Remove the bios_version functionSean Rhodes
Remove smbios_mainboard_bios_version so that the default CONFIG_LOCALVERSION can be used. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ia94f8683a54a98f4e3b1f51521db7e3ccb56ba48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-12-27mainboard/acpi: Replace constant "One" with actual numberFelix Singer
Change-Id: Id1078b14a805eea53d2a7c5a8183a5413f26e115 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71521 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22mb/starlabs/*: Bind console serial output to EDK2_DEBUGSean Rhodes
Configure the UART port but only enable UART debug for EDK2 debug builds. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I54e1dc5768fd765254c7ede91eaa45842fed3bd6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69322 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-20mb/starlabs/starbook/adl: Set thermal trip based on power profileSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I07be0aa2144b7718e28f1f675978b4b4b92752ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/69492 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-17mb/starlabs/starbook: Add Alder Lake StarBook Mk VI variantBen-StarLabs
Tested using `edk2` from `github.com/starlabsltd/edk2/tree/uefipayload_202209`: * Windows 10 * Ubuntu 20.04 * MX Linux 19.4 * Manjaro 21 No known issues. https://starlabs.systems/pages/starbook-specification Signed-off-by: Ben-StarLabs <ben@starlabs.systems> Change-Id: Idc0c265a88b19cf9e89cc8ab3e8db9abd8cf8409 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65785 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-12-06mb/starlabs/lite/{glk,glkr}: Adjust THERMTRIP GPIOSean Rhodes
Modify the configuration of GPIO_74 (PMIC Thermal Trip Point) as in it's current configuration, it stops the laptop entering S5. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I0e31f095ff42a03e3ea1496fe67d69b0f1763a3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/67418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-11-17mb/starlabs/starbook/kbl: Drop redundant option codeAngel Pons
Commit 9bbc039c457774dbeb44ea37ecc6507144d49b61 ("soc/intel/skylake: Hook up FSP hyper-threading setting to option API") already hooks up the `hyper_threading` CMOS option in SoC code, so there's no need to do it from mainboard code. Change-Id: I602452266a8465cced12454f800ea023f382ba6f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69522 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-07mb/starlabs/*: Enable the Mirror flag for boards that support itSean Rhodes
Enable the mirror flag for CML and TGL. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I51678bdb8d876d238076e12c6315a53c5da59628 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-29mb/starlabs/*: Change the local version to KconfigSean Rhodes
Replace the string with a Kconfig option Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib11ddd04c44f47b94f4fc9eaed278d554d581b0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-10-15mb/starlabs/lite/{glk,glkr}: Enable PMCSean Rhodes
Enable PMC in devicetree so that resources are allocated properly for it. Tested on StarLite Mk III & IV, and both can power on correctly. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib4384b55751a9979e470dd04f6814d4ca170ff34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67409 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-15mb/starlabs/lite: Reset XHCI before entering S5Sean Rhodes
Reset the XHCI controller prior to S5 to avoid XHCI preventing shutdown. Linux needs to put the XHCI into D3 before shutting down but the powerstate commands do not perform a reset. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3be70443eb85a7dff8055c9de0ca2fd89f4fc88d Reviewed-on: https://review.coreboot.org/c/coreboot/+/67678 Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-13mb/starlabs/starbook/tgl: Remove PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4GSean Rhodes
PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is no longer needed so remove it. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I82841c2114ceb5e7a46ce228fce63d24822098d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68084 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-12mb/starlabs/starbook/tgl: Configure PMC muxSean Rhodes
Configure PMC mux in devicetree. Tested on StarBook Mk V with Ubuntu 22.04. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I297d5446e43357d97357f345668cf40dcd28502d Reviewed-on: https://review.coreboot.org/c/coreboot/+/68083 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-12mb/starlabs/starbook/tgl: Enable P2SBSean Rhodes
Enable the P2SB so that the SPI is discoverable by the OS. Change-Id: I49802f93a97a18ecc10f48d213619855728e1290 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67029 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-12mb/starlabs/starbook/tgl: Use chipset.cb aliasesSean Rhodes
Change-Id: Ie9655406c7afe7a22f131d35633a697c5bbde4e3 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-10-11mb/starlabs/starbook/kbl: Use chipset.cb aliasesSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I2da15db3d7fba4396c74800e531476c108cafe17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67421 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-11mb/starlabs/starbook/cml: Enable SRAMSean Rhodes
Enable SRAM in devicetree so that resources are allocated properly for it. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I1d7ee4f950b31f2be6fb7bd107b5fe54785ed81a Reviewed-on: https://review.coreboot.org/c/coreboot/+/67420 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-11mb/starlabs/starbook/cml: Enable P2SBSean Rhodes
Enable the P2SB so that the SPI is discoverable by the OS. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ied7a6ea706e6da86182c109ab4813fa3fcebb1f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67419 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-06mb/starlabs/lite/glkr: Enable configuring Fast Charging on the Lite Mk IVSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I714867d455c4e0d01d6cb1cb9dc64669fb41100c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-06mb/starlabs/lite: Add variant specific cmos.layout and cmos.defaultSean Rhodes
Add variant specific cmos files, which avoid options like "FastCharge" existing in platforms that don't support such options. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I04264cf72d47ef719acfd144d8bf9acb0ceccc11 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-06mb/starlabs/starbook: Add variant specific cmos.layout and cmos.defaultSean Rhodes
Add variant specific cmos files, which avoid options like "Thunderbolt" existing in platforms that don't support such options. This change also removes entries that were never used, including: * smi_handler * usb_always_on Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I359e5c5bbf29eb474f2d3bc42a8e80afc0a5d38a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-20mb/starlabs/starbook/kbl: Correct USB port for BluetoothSean Rhodes
Previously, the Bluetooth interface worked when port 9 was enabled. Now, it works with port 5 enabled, which matches the schematic. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If783e60c8120adcd6522676cb3343ed46bf39d78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-09-13mb/starlabs/starbook/tgl: Tidy up the layoutSean Rhodes
Tidy up the layout to remove unnecessary sizes. This change also makes the flash start at 0x0 and increases the size of the FMAP to 0x1000. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I46663003857eb50271c6ad1da6c4e56c8f4bb6c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-09mb/*/{device,override}tree: Set touchpads to use detect (vs probed) flagMatt DeVillier
Historically, ChromeOS devices have worked around the problem of OEMs using several different parts for touchpads/touchscreens by using a ChromeOS kernel-specific 'probed' flag (rejected by the upstream kernel) to indicate that the device may or may not be present, and that the driver should probe to confirm device presence. Since c636142b, coreboot now supports detection for i2c devices at runtime when creating the device entries for the ACPI/SSDT tables, rendering the 'probed' flag obsolete for touchpads. Switch all touchpads in the tree from using the 'probed' flag to the 'detect' flag. Touchscreens require more involved power sequencing, which will be done at some future time, after which they will switch over as well. TEST: build/boot at least one variant for each baseboard in the tree. Verify touchpad works under Linux and Windows. Verify only a single touchpad device is present in the ACPI tables. Change-Id: I47c6eed37eb34c044e27963532e544d3940a7c15 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67305 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-08mb/starlabs/lite/{glk,glkr}: Enable SRAMSean Rhodes
Enable SRAM in devicetree so that resources are allocated properly for it. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ibdd2ee455f5bf6cd95bba6bab8689da664bfcf54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-08-24mb/starlabs/lite: Enable P2SBSean Rhodes
Enable the P2SB so that the SPI is discoverable by the OS. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9c12161d4868deae5b8900cfa2f42517a9f0b7e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-21mb/starlabs/*: Disable INTEL_LPSS_UART_FOR_CONSOLESean Rhodes
Disable INTEL_LPSS_UART_FOR_CONSOLE to stop debug output on UART 2. This decreases boot time on all boards by around 60%. TGL before: Total Time: 10,110,807 TGL after: Total Time: 3,851,641 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I8f8d5cd46e87e7dafe0669b4a29c872b1789eb60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-21mb/starlabs/starbook/kbl: Update verb tableSean Rhodes
The ALC269 does not support the hardware equaliser, so remove the entries related to this, as they have no effect. Revert to the ALC269 defaults which work correctly with Linux. This also corrects the subsystem id from 0x10ec111e to 0x10ec10d0. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I82647f67730ec344591f7dbd759a421c116d4fdd Reviewed-on: https://review.coreboot.org/c/coreboot/+/66687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-19mb/starlabs/lite/glkr: Remove old comment from devicetreeSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib203451bb3da06efd1d3f6e48496b370d81f4b7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66196 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-19mb/starlabs/lite: Use chipset.cb aliasesSean Rhodes
GLKs chipset configures the devices, so use these aliases and remove the entries when they are identical. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic29e5305346c3b7fbf66b027754a9ddd16b16269 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66195 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-13mb/starlabs/starbook/tgl: Enable TPM Measured BootSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I251840b409dead62586cefe5856b6c544401ba30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-08-13mb/starlabs/starbook/kbl: Enable CRB_TPMSean Rhodes
Enable CRB_TPM to allow the use of the fTPM (Intel PTT). Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I7b69854ea636947480402ce12450f431028660a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-08-13payloads/tianocore: Rename TianoCore to edk2Sean Rhodes
coreboot uses TianoCore interchangeably with EDK II, and whilst the meaning is generally clear, it's not the payload it uses. EDK II is commonly written as edk2. coreboot builds edk2 directly from the edk2 repository. Whilst it can build some components from edk2-platforms, the target is still edk2. [1] tianocore.org - "Welcome to TianoCore, the community supporting" [2] tianocore.org - "EDK II is a modern, feature-rich, cross-platform firmware development environment for the UEFI and UEFI Platform Initialization (PI) specifications." Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4de125d92ae38ff8dfd0c4c06806c2d2921945ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/65820 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-25mb/starlabs/lite: Add support for VBOOTSean Rhodes
Add the required files to support VBOOT for when it is enabled. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I083107b21c23f42193fc88aa174ec22850f45bc8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65705 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-07-22mb/starlabs/lite: Simplify the flash layoutSean Rhodes
Remove the sections that coreboot doesn't need to know about. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ide6c0d44f1f9ad9b962d2b8e14ac91e87f5ca031 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65453 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-13mb/starlabs/lite/{glk/glkr}: Remove Bluetooth USB portSean Rhodes
This reverts commit 0225af3c2ba661de82e15f163258605917ca28cf as it has no effect as the USB interface is configured by FSP S. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I20ca355eb1e088d7a7c8eacbc888ffc90833194b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-07-07mb/starlabs: Rename LabTop to StarBookSean Rhodes
The LabTop was renamed to StarBook since the release of the Mk V. This change keeps the directory name more relevant, as there are more boards using the name StarBook. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3513fb56c1adf663ed7bcdade2cc52cd8c0d6f4b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65640 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-07-073rdparty/blobs: Advance submodule pointerSean Rhodes
This contains the following commits: * d55c315 mb/starlabs: Remove padding from logo * 6412d38 mb/starlabs/starbook/cml: Update EC from 1.03 to 1.07 * fb72ac5 mb/starlabs/starbook/tgl: Update EC from 1.00 to 1.03 * cda5eaa mb/starlabs: Rename labtop to starbook * f16020a Revert "soc/mediatek/mt8186: Update SPM firmware to pcm_suspend_v0215… This also changes starlabs/labtop Kconfig to use the new paths for the EC binaries from the above commits. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I83143118af422276ee335ad4ef9eca76f54a9fc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-07-05mb/starlabs/labtop/tgl: Nit - minor format changeSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I068c6e46d85d869afc72280509a03d5ff682b917 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65618 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-05mb/starlabs/labtop: Define CCD Port in KconfigSean Rhodes
Define the CCD (aka "Webcam") USB port in the devicetree as it is used in multiple places. It is used in devtree to disable it based on the CMOS setting "webcam", and in the devicetree to configure the port tuning. This also corrects the port that is disabled on CML, from usb2_port[6] to usb2_port[3]. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I16e368fc7965f978f2302633122ba63038603c1e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64704 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-05mb/starlabs/labtop/tgl: Organise USB ports by hardware portSean Rhodes
Group the USB ports by hardware ports, rather than separate USB 2.0 and 3.0 interfaces. This also removes usb3_port[2] as it is not connected and fixes the labelling of usb3_port[0] and usb3_port[1]. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I7923fc00c36687a7f89d863eb0ea4e01a036502d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-07-05mb/starlabs/lite/glk: Update VbtSean Rhodes
Update the Vbt to disable the fixed mode feature, to allow for bootloader resolutions higher than 1920x1080. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ibd9850dcaef97a58c6694ee594014e9f16ae7f96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-06-22mb/starlabs/lite/{glk/glkr}: Disable UFS deviceSean Rhodes
Disable 1d.0 UFS as it is not used. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib392bc64db440ea3d98ee62536d5395587a3f6aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/65046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-06-21mb/starlabs/lite/{glk/glkr}: Disable Sata Port 1Sean Rhodes
Disable Sata Port 1 as it is not used. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I93ecdaba5d1ce96ddcf3695edd7fb109054743e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-06-21mb/starlabs/lite/glkr: Don't configure GPIO's 147 through 156Sean Rhodes
These are configured by the TXE, so they do not need to be configured. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I13957992d637a53203b4328e39c0e6607e017891 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-21mb/starlabs/lite/glkr: Simplify GPIO macro'sSean Rhodes
Use shorter macro's to conifgure GPIO's. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I926aac8679f847cd963be07786e9fe2e4c63bda6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-21mb/starlabs/lite/glkr: Disconnect unused GPIO'sSean Rhodes
Disconnect GPIO's that are unused, or not connected. Also update comments that are vague or have errors. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I1b071ec1d194f76ee78066396bac8dfff5ec851b Reviewed-on: https://review.coreboot.org/c/coreboot/+/64651 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-20soc/intel/apollolake: Hook Up SataPortEnable to devicetreeSean Rhodes
Hook Up SataPortsEnable to the devicetree. As the default value is 0, set both [0] and [1] in all mainboards so they aren't affected. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ica8cf9484a6e6fe4362eabb8a9a59fcaf97c1bd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64524 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-20mb/starlabs/labtop: Configure tcc_offset based on power_profile settingsSean Rhodes
Set tcc_offset value based on the power_profile value, ranging from 10 to 20 degrees. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I66fb266c1730833ff6e2dbf8ea39f23ee0878590 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20mb/starlabs/lite/glk: Organise USB ports by hardware portSean Rhodes
Group the USB ports by hardware ports, rather than separate USB 2.0 and 3.0 interfaces. This change also corrects the daughterboard USB 3.0 port number. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib6a934a1e5e65fe387c63b78cbe80e45e97e0a8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/64796 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-20mb/starlabs/lite/glkr: Correct the daughterboard USB 3.0 port numberSean Rhodes
The daughterboard USB 3.0 was set to port 3, which is incorrect. This patch corrects that to port 4. This fixes an issue where USB 3.0 devices are not detected when plugged in to this port. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I50f86dee1b512d0dd20d07e3ee17ebfa5e537bc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20mb/starlabs/lite/glkr: Correct USB port numbersSean Rhodes
The USB ports for the Motherboard USB 3.0 and Type-C were labelled incorrectly. This change swaps the ports, so they are labelled correctly and also corrects the over-current pins that they use. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I80484dc8bdd68dd72b3848720c790d59237a9f8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20mb/starlabs/lite/glkr: Organise USB ports by hardware portSean Rhodes
Group the USB ports by hardware ports, rather than separate USB 2.0 and 3.0 interfaces. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I2a7f50ca2b2001e83211e8eba56bfa929ecdfd74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20mb/starlabs/lite: Enable enhanced C-statesSean Rhodes
Tested on the StarLite Mk III & Mk IV with Zorin 16.2 Core. This resulted in a reduction in power consumption of approximately 3%. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I7b5f4e01bc786db02184b722c74fda7d0ca055be Reviewed-on: https://review.coreboot.org/c/coreboot/+/64709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20mb/starlabs/lite: Configure MMIO window for ECSean Rhodes
The Nuvoton EC requires a window to be opened for updates, so open this window only if the Nuvoton EC is present. Change-Id: Iaa45aa58749c4d0bfc77e60b52eab2bcb270f3ee Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 09:52:07 +0000