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path: root/src/mainboard/siemens
AgeCommit message (Expand)Author
2019-09-25mb/siemens/mc_apl1: Sort the names of all variant mainboardsWerner Zeh
2019-09-25mb/siemens/mc_apl{2,4,5}: Enable VBOOTWerner Zeh
2019-09-16src/mainboard: Remove unused include <device/pci_ops.h>Elyes HAOUAS
2019-09-11src: Remove unneeded include <arch/interrupt.h>Elyes HAOUAS
2019-09-05mb/siemens/mc_apl5: Disable IGD if no EDID data availableMario Scheithauer
2019-07-18mb/siemens/{mc_apl1,...,mc_apl5}: Fix GPIO settingsMario Scheithauer
2019-07-18mb/siemens/mc_apl1: Disable all UHS-I SD-Card speed modesMario Scheithauer
2019-07-12mb/siemens/mc_apl3: Enable LPSS UART 1Mario Scheithauer
2019-07-11mb/siemens/{baseboard,mc_apl3,mc_apl4,mc_apl5}: Fix GPIO_168Mario Scheithauer
2019-07-11mb/siemens/{mc_apl1,...,mc_apl5}: Reduce eMMC bus speed modeMario Scheithauer
2019-07-08intel/fsp_broadwell_de: Remove redundant TSC_MONOTONIC_TIMERKyösti Mälkki
2019-07-08intel/fsp_baytrail: Move TSC_MONOTONIC_TIMERKyösti Mälkki
2019-06-21siemens/mc_apl5: Change PTN interface settingsMario Scheithauer
2019-06-21siemens/mc_apl5: Enable TPM supportMario Scheithauer
2019-06-06siemens/mc_apl5: Add own GPIO tableMario Scheithauer
2019-05-29src/mainboard: Add missing 'include <types.h>'Elyes HAOUAS
2019-05-06mb/siemens/mc_apl2: Limit SD-Card speed to DDR50Werner Zeh
2019-04-15mb/siemens/mc_apl4: Remove usage of external RTCWerner Zeh
2019-04-15mb/siemens/mc_apl1: Enable HDA in devicetree for all mainboard variantsWerner Zeh
2019-04-08siemens/mc_apl5: Remove reduced clock rate for I2C0Mario Scheithauer
2019-04-06src: Use include <delay.h> when appropriateElyes HAOUAS
2019-04-04siemens/mc_apl4: Provide CLK on APL Pin PMU_SUSCLKUwe Poeche
2019-03-21mb/siemens/mc_apl1: use comment in Kconfig.nameThomas Heijligen
2019-03-20src: Use 'include <string.h>' when appropriateElyes HAOUAS
2019-03-18src: Drop unused 'include <romstage_handoff.h>'Elyes HAOUAS
2019-03-15mb/mc_apl1/variants/mc_apl5: Drop unused '#include <lib.h>'Elyes HAOUAS
2019-03-12src: Drop unused 'include <arch/acpigen.h>'Elyes HAOUAS
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
2019-03-07src: Drop unused include <timestamp.h>Elyes HAOUAS
2019-03-06src: Drop unused include <arch/acpi.h>Elyes HAOUAS
2019-03-06mb/siemens/{mc_apl1,mc_tcu3}: Fix typo on "Display"Elyes HAOUAS
2019-03-04device/mmio.h: Add include file for MMIO opsKyösti Mälkki
2019-03-04arch/io.h: Drop unnecessary includeKyösti Mälkki
2019-03-04arch/io.h: Add missing includesKyösti Mälkki
2019-03-01device/pci: Fix PCI accessor headersKyösti Mälkki
2019-03-01mb/siemens/mc_bdx1: Enable TPM2 on LPCWerner Zeh
2019-02-13siemens/mc_apl4: Enable HW SPI TPM on mainboard mc_apl4Uwe Poeche
2019-02-13siemens/mc_apl2: Remove double entry from devicetreeMario Scheithauer
2019-02-05mb/siemens/mc_apl1: Enable VTD for mc_apl2 and mc_apl5Werner Zeh
2019-01-30siemens/mc_apl2: Change SERIRQ modeMario Scheithauer
2019-01-30siemens/mc_apl2: Correct whitespace of devicetreeMario Scheithauer
2019-01-30siemens/mc_apl2: Activate TPM supportMario Scheithauer
2019-01-16siemens/mc_apl4: Change UART_FOR_CONSOLE indexMario Scheithauer
2019-01-11siemens/mc_apl1: Use INTEL_LPSS_UART_FOR_CONSOLEMario Scheithauer
2019-01-06device: Use pcidev_on_root()Kyösti Mälkki
2018-12-28arch/x86: Drop spurious arch/stages.h includesKyösti Mälkki
2018-12-19mainboard: Remove useless include <device/pci_ids.h>Elyes HAOUAS
2018-12-17siemens/mc_apl4: Enable RTC RX6110SA on this mainboardUwe Poeche
2018-12-17siemens/mc_apl4: Enable LVDS Display on mc_apl4Uwe Poeche
2018-12-17siemens/mc_apl4: Add GPIO configurationUwe Poeche
2018-11-30cpu/intel/common: Use a common acpi/cpu.asl fileArthur Heymans
2018-11-29siemens/mc_apl5: Disable PCI clock outputs on XIO bridgesMario Scheithauer
2018-11-29siemens/mc_apl5: Set bus master bit for on-board PCI deviceMario Scheithauer
2018-11-29siemens/mc_apl5: Enable SDCARDMario Scheithauer
2018-11-28mb/*/*/Kconfig: Remove useless commentElyes HAOUAS
2018-11-27siemens/mc_apl5: Adjust the settings for the PCIe root portsMario Scheithauer
2018-11-26siemens/mc_apl1/variants/mc_apl*: Remove unneeded PTN readMario Scheithauer
2018-11-23siemens/mc_apl4: Set CPU clock to minimum ratioWerner Zeh
2018-11-23mb: Set coreboot as DSDT's manufacturer model IDElyes HAOUAS
2018-11-21ACPI: Fix DSDT's revision fieldElyes HAOUAS
2018-11-18siemens/mc_apl5: Add new mainboard variant mc_apl5Mario Scheithauer
2018-11-16mb/siemens/mc_apl1/variants/mc_apl*: Remove unused BOARD_SIEMENS_MC_APL*_VARElyes HAOUAS
2018-11-16src: Remove unneeded include <cbfs.h>Elyes HAOUAS
2018-11-16src: Remove unneeded include <lib.h>Elyes HAOUAS
2018-11-16mb/*/*/Kconfig: Use CONFIG_VARIANT_DIR for devicetreePeter Lemenkov
2018-11-16siemens/mc_apl4: Clean up ramstageMario Scheithauer
2018-11-16siemens/mc_apl4: Overwrite swizzle data for LPDDR4Mario Scheithauer
2018-11-12src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS
2018-11-12siemens/mc_apl4: Enable SDCARDMario Scheithauer
2018-11-12siemens/mc_apl4: Remove external RTC from I2C0Mario Scheithauer
2018-11-12siemens/mc_apl4: Enable all PCIe root portsMario Scheithauer
2018-11-12siemens/mc_apl4: Remove reduced clock rate for I2C0Mario Scheithauer
2018-11-12siemens/mc_apl4: Disable CLKREQ of PCIe root portsMario Scheithauer
2018-11-12siemens/mc_apl3: Disable PCI clock outputs on XIO bridgesMario Scheithauer
2018-11-12siemens/mc_apl3: Set Full Reset Bit into Reset Control RegisterMario Scheithauer
2018-11-12siemens/mc_apl3: Set bus master bit for on-board PCI deviceMario Scheithauer
2018-11-12siemens/mc_apl3: Remove the correction of the Tx signal for SATAMario Scheithauer
2018-11-12siemens/mc_apl3: Adjust Legacy IRQ routing for PCI devicesMario Scheithauer
2018-11-07siemens/mc_apl4: Add new mainboard variant mc_apl4Mario Scheithauer
2018-11-07siemens/mc_apl2: Adjust GPIO settings for mc_apl2Mario Scheithauer
2018-11-07siemens/mc_apl3: Disable I2C7 over devicetreeMario Scheithauer
2018-11-07siemens/mc_apl3: Enable all PCIe root portsMario Scheithauer
2018-11-07siemens/mc_apl3: Remove reduced clock rate for I2C0Mario Scheithauer
2018-11-07siemens/mc_apl3: Disable CLKREQ of PCIe root portsMario Scheithauer
2018-11-07siemens/mc_apl3: Adjust GPIO settings for mc_apl3Mario Scheithauer
2018-11-05mainboard: Remove unneeded include <console/console.h>Elyes HAOUAS
2018-10-30siemens/mc_apl3: Add new mainboard variant mc_apl3Mario Scheithauer
2018-10-23src: Remove unneeded whitespaceElyes HAOUAS
2018-10-17mb/*/*: Clean up FADT checksum assignmentJonathan Neuschäfer
2018-10-08Move compiler.h to commonlibNico Huber
2018-10-06soc/intel/common, mb/google, mb/siemens: Use lower case x for RXDFurquan Shaikh
2018-10-04mc_apl1: Set up SPI OPCODE menu before lockingWerner Zeh
2018-10-01siemens/mc_apl1: Activate clock spreading for PTN3460Mario Scheithauer
2018-09-27siemens/mc_apl1: Add new mainboard variant mc_apl2Mario Scheithauer
2018-09-27siemens/mc_apl1: Make the DDR memory swizzle data configurableMario Scheithauer
2018-08-31siemens/mc_apl1: Correct the Tx signal from SATA interfaceMario Scheithauer
2018-08-28siemens/mc_apl1: Extend circuit life by clock gating and power gatingMario Scheithauer
2018-08-27siemens/mc_apl1: Disable PCI clock outputs on XIO bridgeMario Scheithauer
2018-08-24siemens/mc_apl1: Select DDR50 mode for eMMCMario Scheithauer
2018-08-23siemens/mc_apl1: Make adjustments for the 1st redesign of this mainboardMario Scheithauer
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