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2021-12-23mb: Add space before closing comment block keywordPaul Menzel
Run the command below to fix all occurrences. $ git grep -l 'ramstage\*/' | xargs sed -i 's,ramstage\*/,ramstage */,' Change-Id: Ied155d325846fc0ef3e823e5708c6f74e3d7998f Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-18mb/siemens/chili: Reuse options from Kconfig.nameFelix Singer
Reuse the options from Kconfig.name for variant-specific selects. Change-Id: I35f51756180882d019a3ea8c555ccd18cd588f44 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-10mb/siemens/mc_ehl: Enable TPM in bootblockWerner Zeh
Enable TPM init in bootblock so that all further stages and other CBFS files are directly measured into PCRs immediately instead of being logged into a buffer and replayed to the TPM in ramstage. Change-Id: Ib3ac29aa72abe8e967660ae7e8416aeb8812de26 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-11-17mb/siemens/mc_ehl1: Send POST codes to NC FPGA via PCIWerner Zeh
This board does not have a LPC or eSPI connection to the NC FPGA anymore and therefore IO port 0x80 is not useable for POST codes anymore. Enable the feature of sending the POST codes to the NC FPGA via PCI so that the POST codes are visbile again in coreboot. Change-Id: I9043e4ec9a2ad6b946e373bb3dce9da3d42d00d1 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-11-15mb/siemens/mc_ehl2: Adjust PCIe clock source settings in devicetreeMario Scheithauer
With latest hardware revision all clock outputs will be used on this mainboard. For this reason set all clock source mappings to 'PCIE_CLK_FREE' to have a free running clock. Change-Id: Ic3f6fb4e24128742ed72dade7a4555c39fb722ae Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-11-15mb/siemens/mc_ehl: Disable HECI #2 deviceMario Scheithauer
HECI #2 is not used for CSE communication. Therefore, it is not necessary to set the parameter 'Heci2Enable' in devicetree. Change-Id: I7012e4d877a464699727ca775af3f9965e0602e9 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-11-04treewide: Replace bad uses of `find_resource`Angel Pons
The `find_resource` function will never return null (will die instead). In cases where the existing code already accounts for null pointers, it is better to use `probe_resource` instead, which returns a null pointer instead of dying. Change-Id: I329efcb42a444b097794fde4f40acf5ececaea8c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lance Zhao
2021-11-04mb/siemens/mc_ehl: Disable PMC low power modesWerner Zeh
All the mainboard variants of mc_ehl do not use the external switches for the bypass rails. Disable the matching UPDs and all the low power modes of the PMC. Change-Id: I08f4effe5c4d5845bed01dfe1bd1251c58012b7f Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58895 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-04mb/siemens/mc_ehl: Disable all P-StatesWerner Zeh
In order to get a reliable real-time performance disable all P-States for all mc_ehl based mainboard. Change-Id: I22857cc0f1476483ca82c1c872e4519e4b350ea9 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-11-04mb/siemens/mc_ehl: Disable C-States for CPU and packageWerner Zeh
Disable all C-states other than C0/C1 for CPU and package. Change-Id: I2c163f859dab4b0dc02896c70122e993cdd3db72 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-11-04mb/siemens/mc_ehl2: Clean up devicetreeMario Scheithauer
There are a bunch of devices in the devicetree that are disabled in FSP-S and not used on this board. Having them around in the devicetree, even if disabled, is not necessary and leads to a message in the log (left over static devices...check your devicetree). This commit cleans up devicetree.cb and removes all unused and disabled devices. Change-Id: I7486f9ba362c80b43b6c888a3b40a4c947218299 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58887 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-04mb/siemens/mc_ehl: Enable Row-Hammer preventionMario Scheithauer
As a prevention of Row-Hammer attacks enable the FSP-M parameter 'RhPrevention'. Change-Id: I52f68525e882aee26822d9b3c488639c00f27d17 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-11-04mb/siemens/mc_ehl2: Configure SD card detect pin in devicetreeMario Scheithauer
This configures GPIO GPP_G5 as an input pin for SD card detect. Change-Id: I708eb112fa054f2f88857001c409fb62493b6206 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-11-04mb/siemens/mc_ehl2: Clean up PCIe root port settings in devicetreeMario Scheithauer
PCIe root ports #4 (00:1c.3) and #6 (00:1c.5) are currently not used on this mainboard and are not routed either, so remove them from the devicetree completely. PCIe root port #7 (00:1c.6) is connected and used. Add the missing settings for L1 substates and latency reporting to disable these features for this port as well. Change-Id: I47e8528bea993ed527a0aecdbc93b94bbd9a7a49 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-11-04mb/siemens/mc_ehl2: Adjust PCIe clock settings in devicetreeMario Scheithauer
On mc_ehl2 there are currently four of the six PCIe clocks used to drive PCIe devices. None of the used clock output is dedicated to a special device. Therefore do not use a port mapping of the clocks to avoid a stopping clock once a device is missing and the matching root port is disabled. Instead set the mapping to 'PCIE_CLK_FREE' to have a free running clock. In addition, use the defined constant 'PCIE_CLK_NOTUSED' instead of the value 0xFF to disable the CLKREQ-feature and unused clocks. Change-Id: I81419887b7f463a937917b971465245c1cb46b94 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
2021-11-03mb/siemens/mc_ehl1: Adjust PCIe clock settings in devicetreeWerner Zeh
On mc_ehl1 there are three of the 6 PCIe clocks used to drive PCIe devices. None of the used clock output is dedicated to a special device (CLK0 drives several devices on the mainboard, CLK1 and CLK2 are connected to a PCIe switch). Therefore do not use a port mapping of the clocks to avoid a stopping clock once a device is missing and the matching root port is disabled. Instead set the mapping to 'PCIE_CLK_FREE' to have a free running clock. In addition, use the defined constant 'PCIE_CLK_NOTUSED' instead of the value 0xFF to disable the CLKREQ-feature and unused clocks. Change-Id: I2beea76ff8fefd79f476bef343d13495b45cdfcf Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58740 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-02mb/siemens/mc_ehl1: Clean up PCIe root port settings in devicetreeWerner Zeh
PCIe root ports #5 (00:1c.4) and #6 (00:1c.5) are not used on this mainboard and are not routed either, so remove them from the devicetree completely. PCIe root port #7 (00:1c.6) is connected and used. Add the missing settings for L1 substates and latency reporting to disable these features for this port as well. Change-Id: I06f59f0369ffcd958b5fe12bb3c646d37103811f Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58568 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-02mb/siemens/mc_ehl1: Clean up devicetreeWerner Zeh
There are a bunch of devices in the devicetree that are disabled in FSP-S and not used on this board. Having them around in the devicetree, even if disabled, is not necessary and leads to a message in the log (left over static devices...check your devicetree). This commit cleans up devicetree.cb and removes all unused and disabled devices. Change-Id: Ia5ffb382e3524e61b8583aca801063942fe2f247 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-10-27mb/siemens/chili: Drop redundant Kconfig selectAngel Pons
The `SMBIOS_PROVIDED_BY_MOBO` Kconfig option is already selected through the `SECUNET_DMI` option. So, there's no need to select both of them. Change-Id: I784df87893043a011906af8808aff27d636c7626 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58625 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-14mb/siemens/mc_ehl2: Adjust PCH serial IO settingsMario Scheithauer
Correct the PCH serial IO settings, suitable for this mainboard. Change-Id: I3c9915b2d52fbc6a15ac1e68c77bfb3983f7b1cd Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-10-14mb/siemens/mc_ehl2: Adjust USB settingsMario Scheithauer
Correct the USB settings, suitable for this mainboard. Change-Id: I691d91d2a76e27b8efdc18eeae737a78e9ae38fa Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-10-14mb/siemens/mc_ehl2: Enable PCI devicesMario Scheithauer
Correct the remaining PCI devices, differing from the ehl1 mainboard. Change-Id: I8112fa5ea86e879741061798530150701b759156 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-10-14mb/siemens/mc_ehl2: Set coreboot ready LEDMario Scheithauer
This mainboard has its own coreboot ready LED. The LED is switched on via GPIO GPP_F20. Change-Id: I3570d691e90d2cb6e11b856b876f0327da118522 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-10-12mb/siemens/mc_ehl: Remove unneeded 'half_populated' variableWerner Zeh
Since the DRAM population is fixed to both channels on all mc_ehl boards there is no need to have this 'half_populated' variable at all. Simply use a fixed 'false' in the call of 'memcfg_init()' and delete this variable here. Change-Id: I783c17e6d92322a8b0c094cce803108e718011fa Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-12mb/siemens/mc_ehl: Use SPD data from HW-Info in the first placeWerner Zeh
The preferred location for the SPD data on mc_ehl based boards is the HW-Info data structure. Inside this structure there is a field of 128 bytes available for the SPD data. So in order to use it construct a buffer in memory which is 256 bytes long (as FSP requests minimum 256 bytes for the SPD data) and where the upper 128 bytes are taken from HW-Info holding the needed timing parameters for LPDDR4. If there is a case where HW-Info is not accessible or where the contained SPD data is not valid (by checking the CRC in HW-Info SPD) fall back to fixed SPD data set in CBFS. Change-Id: I2b6a1bde0306ba84f5214b876eaf76ca12d8f058 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11mb/siemens/mc_ehl2: Adjust Legacy IRQ routing for PCI devicesMario Scheithauer
On this mainboard there is a legacy PCI device, which is connected to the PCIe root port via a PCIe-2-PCI bridge. This device only supports legacy interrupt routing. For this reason, we have to adjust the PIR8 register (0x3150) which is responsible for PCIe device 25h. The bridge is connected to PCIe root port 7. The following routing is required: INTA#->PIRQC#, INTB#->PIRQD#, INTC#->PIRQA#, INTD#-> PIRQB# TEST: - Boot into system software Change-Id: Id6bb8d00458c4d1e3fefd01ac3848078355868d9 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-10-11mb/siemens/mc_ehl: Add variant_mainboard_final()Mario Scheithauer
In upcoming patches, we need mainboard specific adjustments. Change-Id: Icf9d829b19b2d26a39ad34be4658064083e9da6d Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11mb/siemens/mc_ehl2: Enable LPC ComBMario Scheithauer
Enable LPC ComB on this mainboard. TEST: - Boot Linux and check with 'dmesg | grep tty' Change-Id: I7ec58685a723c177df18144011934b206e6425d0 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11mb/siemens/mc_ehl2: Disable INTEL_LPSS_UART_FOR_CONSOLEMario Scheithauer
This mainboard uses an eSPI-to-LPC bridge for console output. For this reason, the internal LPSS UART must be disabled. Change-Id: I86777cf719def331f4d257ddd94e9a87125ebce8 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11mb/siemens/mc_ehl2: Adjust GPIOsMario Scheithauer
Set the GPIOs according to the circuit diagram for this mainboard. Change-Id: I19dc24a16ee9f533b45879bf60fb441e24018cc8 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11mb/siemens/mc_ehl2: Disable SATA Port 0Mario Scheithauer
This mainboard has only SATA Port 1 available with no device sleep feature. Change-Id: I338833f2f9bcb407599cfc676ead0b8a9d7379bd Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11mb/siemens/mc_ehl2: Enable SD-CardMario Scheithauer
This mainboard has SD slot available and therefore it should be enabled. Change-Id: I0c97e2dc589bf6b89713a473925e42a20278f457 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-11mb/siemens/mc_ehl2: Move RTC RX6110SA from SMBus to I2C2Mario Scheithauer
This board has the RTC RX6110SA connected to the I2C2 instead of SMBus as in mc_ehl1. Set the bus speed for I2C2 to 100 kHz, since this RTC only supports the standard speed. TEST: - Console Log shows no errors for RX6110SA during I2C2 init - Finalize device for I2C 00:32 shows correct date and time Change-Id: I679c6397fa0d213a25eebaf8a9e0bda9941acd26 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-10-11mb/siemens/mc_ehl2: Update SPD for DDR4 devicesMario Scheithauer
Since this variant uses different DDR4 devices compared to mc_ehl1 in a memory down configuration, the SPD data file must be adapted. In a first configuration we use Micron MT53D512M32D2NP modules. Following values were adjusted according to this board characteristic and with help of Serial Presence Detect (SPD) for LPDDR3 and LPDDR4 SDRAM Modules JEDEC Spec and the Specification for this Micron modules itself: - SPD Byte 4 - only 4Gb density instead of 8Gb for mc_ehl1 - SPD Byte 5 - different Row and Column Address Bits - SPD Byte 29/30 - 4Gb LPDDR4 needs 130ns tRFCab - SPD Byte 31/32 - 4Gb LPDDR4 needs 60ns tRFCpb Change-Id: Icb25f418952f0c96117140863d0d9c897d814ac5 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-10-01mb/siemens/mc_ehl: Move UART_FOR_CONSOLE switch to variant levelWerner Zeh
There are currently two variants for mc_ehl where different UARTs are used for the console. Move the Kconfig switch UART_FOR_CONSOLE to the Kconfig of the variant and select the matching value there. Change-Id: I7152013a0e32ff151b92932a47953705e591dc0d Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58052 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-01mb/siemens/mc_ehl: Add a new variant mc_ehl2Werner Zeh
Add a new variant of the mc_ehl board called mc_ehl2. This patch just copies the files and renames things where needed. Following patches will adapt the needed features for this new variant. Change-Id: I3ec3c091017fd66fe6a09216203cdc7c9e833846 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-10-01mb/siemens/mc_ehl1: Enable LPSS UARTWerner Zeh
Enable LPSS UART for coreboot console on mc_ehl1. Change-Id: Id995953741d48fbbe2482ff7c0ef81cac5a31207 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-09-03src/*: Specify type of `DIMM_SPD_SIZE` onceAngel Pons
Specify the type of the `DIMM_SPD_SIZE` Kconfig symbol once. Change-Id: I619833dbce6d2dbe414ed9b37f43196b4b52730e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-28soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by defaultFelix Singer
Since all mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, make it the default by changing its enum value to 0 and remove its configuration from all related devicetrees. If `common_soc_config.chipset_lockdown` is not configured with something else in the devicetree, then `CHIPSET_LOCKDOWN_COREBOOT` is used. Also, add a release note for the upcoming 4.15 release. Change-Id: I369f01d3da2e901e2fb57f2c83bd07380f3946a6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-13mb/{kontron/bsl6,siemens/chili}: Add `inhibit_flashlock` nvram optionNico Huber
Change-Id: I8c5d6686bf7c694f9d594e3801c79cfd7fb3da80 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56342 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02mb/siemens/mc_ehl: Enable master bit in PCI config space if allowedWerner Zeh
Some legacy devices need to have the master bit set in the PCI config due to old drivers not setting it correctly. Set the master bit if the feature is enabled via Kconfig switch PCI_ALLOW_BUS_MASTER_ANY_DEVICE. For now, the PCI devices with the ID 110a:403e and 110a:403f needs this master bit to be set. Change-Id: Id3f6bda97e5f47d0613a1db8f8adac0b158ab8b1 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56632 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02mb/siemens/mc_ehl: Add code to wait for legacy devices before PCI scanWerner Zeh
Boards based on mc_ehl have, just like some mc_apl variants, legacy devices on the PCI bus which take longer to boot. In order to ensure that they will be enumerated correctly wait for them to come up before PCI scan starts. TEST=Checked that the new message is visible in the log. Change-Id: If2f935b69ddaa9364566deacfada5e7d41fcdabd Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56631 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29mb/siemens/mc_ehl1: Disable LTR for all PCIe root portsWerner Zeh
Latency Tolerance Reporting is yet another PCIe power management feature which can have a bad influence on realtime performance. Disable this feature for all PCIe root ports. Change-Id: I38023e095ca55efd2178ad944f651fee1f1c34cd Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-07-29mb/siemens/mc_ehl1: Disable L1 substates for PCIe root portsWerner Zeh
L1 substates of a PCIe link are meant to save some power when the link is not active but have the drawback that the PCIe latency is increased as PLLs are switched on and off as needed. In order to get a better realtime performance, disable all substates for every PCIe root port. Change-Id: Ic5bc8410709d0f0094810bc11a7723e88c30e397 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-07-29mb/siemens/mc_ehl1: Enable Intel I210 MACPHY driverWerner Zeh
This variant uses I210 MACPHYs so enable the I210 driver in order to set the needed MAC addresses. In addition add the function to retrieve a valid MAC address for the given MACPHY. Change-Id: Id1d59349db1b86cfdd71bbe27577c0530e8f0b51 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56567 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29mb/siemens/mc_ehl: Enable Siemens NC-FPGA driverWerner Zeh
All the boards based on the mc_ehl baseboard have the NC-FPGA available. Enable the appropriate driver on baseboard level. Change-Id: I40b76a837b7ddb70ceba3135996b1c1080170c4d Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56566 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29mb/siemens/mc_ehl: Enable SIEMENS_HWILIBWerner Zeh
All variants based on mc_ehl will use the Siemens HWILIB. Select the Kconfig switch on baseboard level. Change-Id: I940f84a4a7449487fe78c793f8dbb1c1b49fa54b Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56565 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29mb/siemens/mc_ehl1: Enable In Band ECCWerner Zeh
Enable IBECC for mc_ehl1 to provide a memory failure protection. Change-Id: If8f81d6bacb77dc38e231c1cedf22831de8a38a9 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56564 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29mb/siemens/mc_ehl1: Disable System Agent dynamic frequency supportWerner Zeh
In favor of better realtime performance disable dynamic frequency support in the System Agent for mc_ehl1. Change-Id: I0e62bcf2e5efa97d89bf7192f1536747a02ad992 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56563 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29mb/siemens/mc_ehl: Enable measured bootWerner Zeh
Enable measured boot for all boards based on mc_ehl baseboard. Change-Id: I3aff943305c024d1f25d2127e6f60495828da3eb Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-07-29mb/siemens/mc_ehl: Enable LPC TPMWerner Zeh
All the boards based on the mc_ehl baseboard have a TPM which is connected to SPI but mapped into the address space of the x86 so that it acts like a LPC attached TPM. Enable the TPM driver so that it will be used. In addition add the needed entry in devicetree. Change-Id: I301d0ed4a108bac45d95eced120e7ba280945d9c Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-07-29mb/siemens/mc_ehl: Add external RTC RX6110SAWerner Zeh
All the mainboards based on mc_ehl use the external RTC RX6110SA. Enable the driver in Kconfig for all boards based on mc_ehl. In addition, as mc_ehl1 has the RTC attached to the SMBus, add the devicetree entry on behalf of the SMBus device 00:1f.4 for this variant. Change-Id: Ie1f45d0e6f9063c00253fe58a6268d40de91cf63 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56523 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `VARIANT_DIR` onceAngel Pons
Specify the type of the `VARIANT_DIR` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: Iea2f992a59e41e00fec3cdc9d6a13b5f3ab0a437 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56558 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `FMDFILE` onceAngel Pons
Specify the type of the `FMDFILE` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I810bd3fe8d42102586db6c2c58b7037a60189257 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56557 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `DEVICETREE` onceAngel Pons
Specify the type of the `DEVICETREE` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: If68f11a5ceaa67a3e8218f89e1138c247ebb9a25 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56555 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `MAINBOARD_PART_NUMBER` onceAngel Pons
Specify the type of the `MAINBOARD_PART_NUMBER` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I3692f9e82fe90af4d0da1d037018a20aa1b45793 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56554 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `MAINBOARD_DIR` onceAngel Pons
Specify the type of the `MAINBOARD_DIR` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: If1cc538b0c4938dac193699897b690e402b3c1e8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56553 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26src/*: Specify type of `CBFS_SIZE` onceAngel Pons
There's no need to specify the type of the `CBFS_SIZE` Kconfig symbol more than once. This is done in `src/Kconfig`, along with its prompt. Change-Id: I9e08e23e24e372e60c32ae8cd7387ddd4b618ddc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56552 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-23mb/siemens/mc_ehl1: Add GPIO configurationWerner Zeh
Provide a valid GPIO configuration based on the mainboard wiring. Change-Id: I36f0e8292a405b4bac74fbc5fde62e5e414387e7 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56519 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-23mb/siemens/mc_ehl1: Remove SD-Card card detect GPIO in devicetreeWerner Zeh
Since there is no SD card interface on this mainboard do not set the card detect GPIO. Change-Id: Ibe6799c5c540538f97d1726ec16e79f3edbb16fd Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56489 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-23mb/siemens/mc_apl{1,2,3,5,6}: Use PCI_ALLOW_BUS_MASTER_ANY_DEVICEWerner Zeh
Use the Kconfig switch PCI_ALLOW_BUS_MASTER_ANY_DEVICE instead of PCI_ALLOW_BUS_MASTER to enable PCIe bus master bit as requested in CB:56441 during review. Change-Id: I433dbae0d9b15e41d1d0750298868341ce3d6b46 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-07-22mb/siemens/mc_ehl1: Disable GSPI in devicetreeWerner Zeh
Since this mainboard does not use GSPI at all, disable all GSPI ports. Change-Id: I60254e9f4047537d86c972151ec9e33552332959 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-07-22mb/siemens/mc_ehl1: Adjust I2C bus enablement in devicetreeWerner Zeh
This mainboard uses I2C1 and I2C4 buses only. Disable all the others as they are not connected at all. Change-Id: I4743f6ea6b9a9987ad63b60f56ee9a597a08284b Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-07-22mb/siemens/mc_ehl1: Disable power management features for SATAWerner Zeh
Features like DevSLP and Aggressive Link Power Management are not supported on this mainboard and are therefore disabled. Change-Id: I3bc650ea78be8587889fb7abfe7075cd9a122198 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-07-22mb/siemens/mc_ehl1: Adjust PCIe settings in devicetreeWerner Zeh
This board does not use CLKREQ-signaling for PCIe, so disable the pin assignments. In addition only three clock outputs are used for PCIe, therefore disable all others to improve EMI. Change-Id: I545f890fa55a109df7f44d2c82170874fb769009 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56455 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-22mb/siemens/mc_ehl1: Adjust USB port settings in devicetreeWerner Zeh
There are in total three USB ports that are used on mc_ehl1: - Port 1: Type A connector connected to USB2/USB3 port 0 - Port 2: Type A connector connected to USB2/USB3 port 1 - Onboard: connected to USB2 port 2 None of the ports supports overcurrent reporting. Adjust the appropriate UPDs in devicetree to match the hardware configuration. Change-Id: I220637b8e9f03efccacd0955e82cfc0c7a6f53ee Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56454 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-22mb/siemens/mc_ehl1: Remove display related UPDs from devicetreeWerner Zeh
Since mc_ehl1 does not have a display attached nor have a display connector available (pure headless design), remove display related settings from the devicetree. Change-Id: Id31c09fcfba15f55eed19134bd0c2fb887bd2478 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56453 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-21mb/siemens/mc_apl{1,2,3,5,6}: Set PCI bus master bit only if allowedWerner Zeh
Take Kconfig switch PCI_ALLOW_BUS_MASTER into account and set the PCI bus master bit for legacy devices only if it is allowed. Change-Id: I7798a767d528419bb093f301140ab68cc8b9c5ae Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-07-20mb/siemens/mc_ehl: Move SPD data to variant directoryWerner Zeh
Since the variants can have different memory move the SPD related content to the variant directory. Change-Id: I38aa5e7514437bfcc61c38d64f0ba6f19350810d Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56036 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14mb/siemens/chili: Drop ineffective `SaGv` settingAngel Pons
SaGv is only available on ULT/ULX processors, which use PCH-LP. Given that the Siemens Chili board selects `SOC_INTEL_CANNONLAKE_PCH_H`, it does not use ULT/ULX processors, and thus does not support SaGv. Drop the `SaGv` setting from the devicetrees, as it has no effect. Change-Id: I5be518cce08206ad149efd1665e44a7111b24202 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56205 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-13mb/siemens/chili: Use CHIPSET_LOCKDOWN_COREBOOTFelix Singer
Currently, internal flashing is not possible due to FSP lockdown. Thus let coreboot do chipset lockdown. Change-Id: Iee4f6986e5edfe1bf6c84fe132bcb47b15bb81f5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56198 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-07mb/siemens/mc_ehl: Switch to 16 MB ROM and provide a flashmapWerner Zeh
There is a 16 MB flash chip on mc_ehl. Set the ROM size accordingly and provide a flashmap for partitioning. Select the used flashmap on variant level to allow different layouts for different variants. Change-Id: I694729ad98f91e27308220903c49e7cb7fc436b4 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-07-07mb/siemens/mc_ehl: Clean up KconfigWerner Zeh
Remove Kconfig switches that are not needed for mc_ehl based mainboards. Change-Id: If231f37f06c6763d52a821799e87fdb3010af0aa Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-07-05mb/siemens/mc_ehl: Provide a proper scheme for variantsWerner Zeh
There will be more variants of this mainboard so prepare the scheme for Kconfig to handle the variants properly. Change-Id: If1cf418836d77a45955ee55d30ba670db8ff2533 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-07-05mb/siemens/mc_ehl: Add new mainboard based on elkhartlake_crbWerner Zeh
Add a new mainboard called mc_ehl which is based on Intel's 'elkhartlake_crb'. This commit simply copies the mainboard directory and adjusts the naming to match the new board's name. Follow-up commits will introduce the needed changes for the new mainboard. Change-Id: Ia7c0616098046d975aa698910ac81f435d7882cb Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-06-29Kconfig: Escape variablesPatrick Georgi
New kconfig parsers interpret $(var) themselves, leading to empty fields. Old kconfig understands \$(var), so use that. Change-Id: I927fc9dc7a66211bfe51d4324cf7c51b555ea3a8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55912 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-04mb/siemens/mc_apl2: Disable unused I2C controllersWerner Zeh
Only I2C controller 3 is used on this mainboard. Disable all other controllers. Change-Id: Id06d98787a0574a5b3a8dc2e86858dfcc7154606 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-06-04mb/siemens/mc_apl{1,2,3,5,6}: Provide I2C timings for 400 kHzWerner Zeh
The I2C bus at which the external RTC is attached to is operated at standard speed (100 kHz) at coreboot runtime. The OS can choose to run it at fast speed since it uses its own driver and controller setup. Report additional bus timings for fast mode so that OS can do it right. Change-Id: I82e11e5dde8ad1047713f105c5a6d020eebf1ffd Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55089 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-30mb/siemens/mc_apl{1,2,3,5,6}: Disable ACPI-support for RX6110Werner Zeh
Already released Linux versions did not have the needed ACPI-extension in the RTC driver. If the ACPI-Support is enabled for the RTC, this older Linux will not be able to use this device as it will be claimed by the PNP-drivers. As there is no way to avoid that an older Linux kernel meets a newer coreboot in the field, we need to disable the ACPI support for the RTC for the mc_apl-based mainboards. Change-Id: I9f9939ba3234dc3654a4ef8a498649453941ebdf Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55004 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-30mb/siemens/mc_apl1: Move gpio.c from baseboard to mc_apl1Mario Scheithauer
Variant mc_apl1 is the only one that uses gpio.c from baseboard. For this reason, gpio.c is moved from baseboard to mc_apl1. Change-Id: Ie2ba8181dfe887df9abbbd648f2cbdc6ffc65530 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-05-30mb/siemens/{mc_apl2,...,mc_apl6}: Do early UART pad configurationMario Scheithauer
With commit 405f229689 (soc/intel/*: drop UART pad configuration from common code) the UART pad configuration was dropped from common SoC code. Through a second commit 5ff17ed393 (mb/siemens/mc_apl1: do UART pad configuration at board-level) the UART pad configuration was made for mc_apl1 baseboard. This change is also needed for all other mc_apl boards. Change-Id: If78726d9b141e4e7580cca3267f49c1a5b95d7fa Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-05-06src: Retype option API to use unsigned integersAngel Pons
The CMOS option system does not support negative integers. Thus, retype and rename the option API functions to reflect this. Change-Id: Id3480e5cfc0ec90674def7ef0919e0b7ac5b19b3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-05-02mb/siemens/mc_apl{1,2,3,5,6}: Tune I2C frequencyWerner Zeh
All the boards in the patch have a constraint for the I2C bus to operate on 100 kHz. Provide dedicated values for rise time, fall time and data hold time on mainboard level to get a proper timing which takes the bus load into account. Giving these values the driver computes the needed timings correctly. TEST=Measure I2C frequency on all boards while coreboot accesses external RTC and make sure it is 100 kHz. Change-Id: Iab634190bda5fa2a4fdf2ebaa1e45ac897d84deb Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52721 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-22soc/intel/cannonlake: Set DIMM_SPD_SIZE to 512Felix Singer
All related mainboards are setting DIMM_SPD_SIZE to 512. Therefore, default to 512 in the SoC Kconfig and drop it from related mainboard Kconfigs. Change-Id: Idb6a0e42961eeb490afd76b4aa7d940961991733 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52513 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21mainboard: Use read_int_option()Angel Pons
Change-Id: I9273b90b6a21b8f52fa42d9ff03a9b56eec9fcbf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-16mb/siemens/mc_apl1/variants/mc_apl2/mainboard.c: Clean includesElyes HAOUAS
Change-Id: I14ec7d6faa20542707a1b6041e1ce358ce4a537a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-02-15src/mb: Remove unused <console/console.h>Elyes HAOUAS
Change-Id: I6e0f33172fbcecebddfccdf64c22685636a23936 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50524 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11src/mainboard: Remove unneeded whitespace before tabElyes HAOUAS
Change-Id: I37f12f5cb35ea1a6ad33edb114688ce1619030a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10mb/siemens/mc_apl2: Switch I2C bus for RX6110SAMario Scheithauer
With a new HW revision of this board, the connection of the external RTC RX6110SA was changed from I2C bus 0 to I2C bus 3. Change-Id: I10dd44949973ea490b3c7e4ad83d56ce2e566adf Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-02mb/siemens/mc_apl1: do UART pad configuration at board-levelMichael Niewöhner
UART pad configuration should not be done in common code, because that may cause short circuits, when the user sets a wrong UART index. Thus, add the corresponding pads to the early UART gpio table for the board as a first step. Common UART pad config code then gets dropped in CB:48829. Also switch to `bootblock_mainboard_early_init` to configure the pads in early bootblock before console initialization, to make the console work as early as possible. The board does not do any other gpio configuration in bootblock, so this should not influence behaviour in a negative way (e.g. breaking overrides). Change-Id: Iac8a6e386b708ae5c4dbf0677bfe05f1358bf8fd Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49442 Tested-by: siemens-bot Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-27ACPI: Add top-level ASLKyösti Mälkki
Objects that are created with acpigen need to be declared with External () for the generation of dsdt.asl to pass iasl without errors. There are some objects that are common to all platforms, and some that should be declared only conditionally. Having a top-level ASL helps to achieve this. Change-Id: Ibaf1ab9941b82f99e5fa857c0c7e4b6192c74330 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-21mb/siemens/chili: do UART pad configuration at board-levelMichael Niewöhner
UART pad configuration should not be done in common code, because that may cause short circuits, when the user sets a wrong UART index. Thus, add the corresponding pads to a bootblock gpio table for the board as a first step. Common UART pad config code then gets dropped in CB:48829. Change-Id: Iad40b6315a29e7aea612a3e1a169372d296d1d6c Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49443 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-20mb/siemens/{mc_apl1,...,mc_apl6}: Configure FSP-S UPDsMario Scheithauer
Until now some FSP-S parameters were configured for Siemens APL mainboards via the Binary Configuration Tool (BCT). For simplification, the original APL FSP binary should now be used. For this purpose, the corresponding FSP-S parameters are set via devicetree, respectively via mainboard_silicon_init_params accordingly. The following parameters are affected: - Disable CPU power states (C-states) - Set lowest Max Pkg Cstate - PkgC0C1 - Disable PCIe Hot Plug for all enabled RPs - Disable PCIe Transmitter Half Swing for all RPs - Disable PCIe Active State Power Management (ASPM) for all RPs - Disable PCIe L1 Substates for all RPs TEST: - Compare old with new coreboot log on mc_apl5, found no differences - Boot Linux v4.4 and check output of 'lspci' Change-Id: I5af627defd6426140cc9a74bb18db400a8971d72 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-01-15mb/siemens/mc_apl1: do LPC/eSPI pad configuration at board-levelMichael Niewöhner
Do LPC/eSPI pad configuration at board-level to match other platforms. Early gpio configuration was done in romstage, while LPC pads were configured in bootblock. Instead of adding another dedicated gpio table for bootblock, move early gpio configuration completely to bootblock on these boards. This won't hurt, since there is no code touching the pads in between. The soc code gets dropped in CB:49410. Change-Id: I2a614afb305036b0581eac8ed6a723a3f80747b3 Tested-by: Mario Scheithauer <mario.scheithauer@siemens.com> Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-01-05mb/siemens/chili: Rework KconfigFelix Singer
Rework Kconfig file so that each variant has its own config option with their specific selects / configuration and move common selects to a seperate config option, which is used as base for each variant. Built chili/base with BUILD_TIMELESS=1, coreboot.rom remains the same. Change-Id: I5e2a09db80232457b2f78ad9b100c468d281f753 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-27mb/siemens/chili/base: Add SMBIOS slot descriptionsFelix Singer
Add SMBIOS slot descriptions for M.2 ports and remove duplicate comments. Change-Id: Ieff03ad3167aec054cdc6b67ddc20fc64394e347 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-08mb/siemens/chili/base: Fix state of PCI devicesFelix Singer
The PCI devices P2SB and PMC are hidden by the FSP and cannot be unhidden, because the FSP locks their configuration. Thus, setting them to `on` is not correct. Therefore, set their state to hidden. Change-Id: Ib7c019cd7f389b2e487829e5550cc236ee5645b7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48388 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08mb/siemens/chili: Remove unnecessary device declarationsFelix Singer
Change-Id: I193aea7c92f340bd80a41a3777bcddc3f1339620 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-06mb/siemens/chili: Move mainboard/gpio.h to variant/gpio.hFelix Singer
Move mainboard/gpio.h to variant/gpio.h and rename its methods to make clear that these methods are implemented on variant level. Change-Id: Ib4e7ec948ca4d019ad82ebc5abe39fc408281cf4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48299 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30mb/siemens/chili: Configure GPIOs in gpio.cFelix Singer
Get rid of variant_gpio_table() and configure GPIOs in gpio.c instead of passing data around. Change-Id: Ib158d6bdbcbceb3c1dc4f47fc7c3e098b9c7e5c4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47974 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-12 06:33:46 +0000