diff options
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2021-08-24 11:45:39 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-10-11 12:48:55 +0000 |
| commit | 6deadeeeca7931807b2fc915d7ea263606f1a1e1 (patch) | |
| tree | c6d5e5cebf1c4d4812d77b07fddd2c5d8fc4456b /src/mainboard/siemens | |
| parent | 5cb62f1aa3ff6a96592152add83f9c52cc42f4b8 (diff) | |
mb/siemens/mc_ehl2: Disable SATA Port 0
This mainboard has only SATA Port 1 available with no device sleep
feature.
Change-Id: I338833f2f9bcb407599cfc676ead0b8a9d7379bd
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Diffstat (limited to 'src/mainboard/siemens')
| -rw-r--r-- | src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 21f462612a..062ac5ff83 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -87,7 +87,7 @@ chip soc/intel/elkhartlake # Storage (SATA/SDCARD/EMMC) related UPDs register "SataSalpSupport" = "0" - register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[0]" = "0" register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[0]" = "0" register "SataPortsDevSlp[1]" = "0" |