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path: root/src/mainboard/siemens/mc_ehl/variants
AgeCommit message (Expand)Author
2021-11-17mb/siemens/mc_ehl1: Send POST codes to NC FPGA via PCIWerner Zeh
2021-11-15mb/siemens/mc_ehl2: Adjust PCIe clock source settings in devicetreeMario Scheithauer
2021-11-15mb/siemens/mc_ehl: Disable HECI #2 deviceMario Scheithauer
2021-11-04mb/siemens/mc_ehl2: Clean up devicetreeMario Scheithauer
2021-11-04mb/siemens/mc_ehl2: Configure SD card detect pin in devicetreeMario Scheithauer
2021-11-04mb/siemens/mc_ehl2: Clean up PCIe root port settings in devicetreeMario Scheithauer
2021-11-04mb/siemens/mc_ehl2: Adjust PCIe clock settings in devicetreeMario Scheithauer
2021-11-03mb/siemens/mc_ehl1: Adjust PCIe clock settings in devicetreeWerner Zeh
2021-11-02mb/siemens/mc_ehl1: Clean up PCIe root port settings in devicetreeWerner Zeh
2021-11-02mb/siemens/mc_ehl1: Clean up devicetreeWerner Zeh
2021-10-14mb/siemens/mc_ehl2: Adjust PCH serial IO settingsMario Scheithauer
2021-10-14mb/siemens/mc_ehl2: Adjust USB settingsMario Scheithauer
2021-10-14mb/siemens/mc_ehl2: Enable PCI devicesMario Scheithauer
2021-10-14mb/siemens/mc_ehl2: Set coreboot ready LEDMario Scheithauer
2021-10-11mb/siemens/mc_ehl2: Adjust Legacy IRQ routing for PCI devicesMario Scheithauer
2021-10-11mb/siemens/mc_ehl: Add variant_mainboard_final()Mario Scheithauer
2021-10-11mb/siemens/mc_ehl2: Enable LPC ComBMario Scheithauer
2021-10-11mb/siemens/mc_ehl2: Disable INTEL_LPSS_UART_FOR_CONSOLEMario Scheithauer
2021-10-11mb/siemens/mc_ehl2: Adjust GPIOsMario Scheithauer
2021-10-11mb/siemens/mc_ehl2: Disable SATA Port 0Mario Scheithauer
2021-10-11mb/siemens/mc_ehl2: Enable SD-CardMario Scheithauer
2021-10-11mb/siemens/mc_ehl2: Move RTC RX6110SA from SMBus to I2C2Mario Scheithauer
2021-10-11mb/siemens/mc_ehl2: Update SPD for DDR4 devicesMario Scheithauer
2021-10-01mb/siemens/mc_ehl: Move UART_FOR_CONSOLE switch to variant levelWerner Zeh
2021-10-01mb/siemens/mc_ehl: Add a new variant mc_ehl2Werner Zeh
2021-10-01mb/siemens/mc_ehl1: Enable LPSS UARTWerner Zeh
2021-08-28soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by defaultFelix Singer
2021-07-29mb/siemens/mc_ehl1: Disable LTR for all PCIe root portsWerner Zeh
2021-07-29mb/siemens/mc_ehl1: Disable L1 substates for PCIe root portsWerner Zeh
2021-07-29mb/siemens/mc_ehl1: Enable Intel I210 MACPHY driverWerner Zeh
2021-07-29mb/siemens/mc_ehl1: Enable In Band ECCWerner Zeh
2021-07-29mb/siemens/mc_ehl1: Disable System Agent dynamic frequency supportWerner Zeh
2021-07-29mb/siemens/mc_ehl: Enable LPC TPMWerner Zeh
2021-07-29mb/siemens/mc_ehl: Add external RTC RX6110SAWerner Zeh
2021-07-26mb/*: Specify type of `FMDFILE` onceAngel Pons
2021-07-23mb/siemens/mc_ehl1: Add GPIO configurationWerner Zeh
2021-07-23mb/siemens/mc_ehl1: Remove SD-Card card detect GPIO in devicetreeWerner Zeh
2021-07-22mb/siemens/mc_ehl1: Disable GSPI in devicetreeWerner Zeh
2021-07-22mb/siemens/mc_ehl1: Adjust I2C bus enablement in devicetreeWerner Zeh
2021-07-22mb/siemens/mc_ehl1: Disable power management features for SATAWerner Zeh
2021-07-22mb/siemens/mc_ehl1: Adjust PCIe settings in devicetreeWerner Zeh
2021-07-22mb/siemens/mc_ehl1: Adjust USB port settings in devicetreeWerner Zeh
2021-07-22mb/siemens/mc_ehl1: Remove display related UPDs from devicetreeWerner Zeh
2021-07-20mb/siemens/mc_ehl: Move SPD data to variant directoryWerner Zeh
2021-07-07mb/siemens/mc_ehl: Switch to 16 MB ROM and provide a flashmapWerner Zeh
2021-07-05mb/siemens/mc_ehl: Add new mainboard based on elkhartlake_crbWerner Zeh
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-23 06:43:06 +0000