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2018-11-29siemens/mc_apl5: Disable PCI clock outputs on XIO bridgesMario Scheithauer
On this mainboard there are legacy PCI device, which are connected to different PCIe root ports via PCIe-2-PCI bridges. This patch disables the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridges. Change-Id: Id36e39c4568f5dd241cd864d2e75365abd0f2a91 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/29882 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-29siemens/mc_apl5: Set bus master bit for on-board PCI deviceMario Scheithauer
There is an on-board PCI device where bus master has to be enabled in PCI configuration space. As there is no need for a complete PCI driver for this device just set the bus master bit in mainboard_final(). Change-Id: I4ab40e34253c20adaacfdf42050314e06547eefb Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/29881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-29siemens/mc_apl5: Enable SDCARDMario Scheithauer
This mainboard also has a SD slot. Change-Id: I969e8ecb27aee4c8be212e67dfe6bd807ecd3b2f Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/29879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-27siemens/mc_apl5: Adjust the settings for the PCIe root portsMario Scheithauer
This mainboard has four connected PCIe devices. The required root ports are switched on and configured. Change-Id: I82b13e1d245a172762ebd689ae136a762027033f Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/29810 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-26siemens/mc_apl1/variants/mc_apl*: Remove unneeded PTN readMario Scheithauer
An additional read of PTN configuration data at the end of the ptn3460_init function is not necessary. Change-Id: I5f7f647242e94b1af13757d00e80ed9813d435d0 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/29799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-11-23siemens/mc_apl4: Set CPU clock to minimum ratioWerner Zeh
The power budget for this mainboard is very limited while the performance demand is low. Set the CPU clock to the lowest value to enable maximum efficiency and thus lowest power dissipation. Change-Id: I23c7c5393deb676b94f2b0ac25e21a7a44cd8cb3 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/29773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-23mb: Set coreboot as DSDT's manufacturer model IDElyes HAOUAS
Field 'OEMID' & "OEM Table ID" are related to DSDT table not to mainboard. So use macro to set them respectvely to "COREv4" and "COREBOOT". Change-Id: I060e07a730e721df4a86128ee89bfe168c69f31e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: David Guckian
2018-11-21ACPI: Fix DSDT's revision fieldElyes HAOUAS
DSDT revision is =1 for ACPI v1 and =2 for greater ACPI version. This will cause the AML interpreter to use 32-bit integers and math if the version is 1, and 64-bit if the version is >=2. Current spec version is 2 for ACPI 6.2-a. Change-Id: I77372882d5c77b7ed52dcdd88028403df6f6fa7f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29626 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-18siemens/mc_apl5: Add new mainboard variant mc_apl5Mario Scheithauer
This mainboard is based on mc_apl1. In a first step, it contains a copy of mc_apl1 directory with minimum changes. Special adaptations for mc_apl5 mainboard will follow in separate commits. Change-Id: Icdbb116a822ffa7a3bfb7026a5d1164db56a0c46 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-16mb/siemens/mc_apl1/variants/mc_apl*: Remove unused BOARD_SIEMENS_MC_APL*_VARElyes HAOUAS
Change-Id: I6e911556abc7b7ac3573c5807b6453eecaff7e10 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2018-11-16src: Remove unneeded include <lib.h>Elyes HAOUAS
Change-Id: I801849fb31fe6958e3d9510da50e2e2dd351a98d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16mb/*/*/Kconfig: Use CONFIG_VARIANT_DIR for devicetreePeter Lemenkov
Change-Id: Ic9620cfa1630c7c085b6c244ca80dc023a181e30 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-16siemens/mc_apl4: Clean up ramstageMario Scheithauer
Currently, there is nothing for this mainboard to do in ramstage. Change-Id: Id74a5f3f0a0583dc6bc81044913b8bb83d3b0b93 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-16siemens/mc_apl4: Overwrite swizzle data for LPDDR4Mario Scheithauer
This mainboard is equipped with LPDDR4 modules. The corresponding memory swizzle data must be set for this purpose. Change-Id: I4017de0713f0df5e614086912fc39d8eb6562702 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Uwe Pöche <uwe.poeche@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-12siemens/mc_apl4: Enable SDCARDMario Scheithauer
This mainboard also has a SD slot. Change-Id: Id56bc1be60ec8c2be0e5543d1d8851610b7248e0 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-12siemens/mc_apl4: Remove external RTC from I2C0Mario Scheithauer
This mainboard also has an external RTC chip, but not on this bus. The topic is currently in clarification and will be published with a later patch. In a first step we enable all I2C busses. Change-Id: I9ec9631ed15ab30cc6a4594531521f4a1419ad00 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-12siemens/mc_apl4: Enable all PCIe root portsMario Scheithauer
Enable all PCIe root ports for this mainboard. Change-Id: I7f6feb2f0d4c45f32d9454838e67e1a244b2712b Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-12siemens/mc_apl4: Remove reduced clock rate for I2C0Mario Scheithauer
There is no device on I2C0 which requires a lower clock rate. Change-Id: Ib7c4e3251545b2d32368dd56206e3b4844a24800 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-12siemens/mc_apl4: Disable CLKREQ of PCIe root portsMario Scheithauer
All PCIe root ports of this mainboard do not have an associated CLKREQ signal. Therefore the ports are marked with "CLKREQ_DISABLED". Change-Id: I834b3b0c77223d81c950e27ccfff8e9aeece2aa4 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-12siemens/mc_apl3: Disable PCI clock outputs on XIO bridgesMario Scheithauer
On this mainboard there are legacy PCI device, which are connected to different PCIe root ports via PCIe-2-PCI bridges. This patch disables the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridges. Change-Id: I2212c1080b72a656b5c8e68b040108a7adbec608 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-12siemens/mc_apl3: Set Full Reset Bit into Reset Control RegisterMario Scheithauer
This mainboard provides customer hardware reset button. A feature of this button is that it holds the APL in reset state as long as the reset button is pressed. After releasing the reset button the APL should restart again without the need for a power cycle. When Bit 3 in Reset Control Register (I/O port CF9h) is set to 1 and then the reset button is pressed the PCH will drive SLP_S3 active (low). Change-Id: Ib842f15b6ba14851d7f9b1b97c83389adc61f50b Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-12siemens/mc_apl3: Set bus master bit for on-board PCI deviceMario Scheithauer
There is an on-board PCI device where bus master has to be enabled in PCI configuration space. As there is no need for a complete PCI driver for this device just set the bus master bit in mainboard_final(). Change-Id: I1ef4a7774d4ca75c230063debbc63d03486fed6f Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-12siemens/mc_apl3: Remove the correction of the Tx signal for SATAMario Scheithauer
For this mainboard the correction of transmit voltage swing from SATA interface is not necessary. Change-Id: I900d0d44b88585c223182d85c78cf3ff1e3e9159 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-12siemens/mc_apl3: Adjust Legacy IRQ routing for PCI devicesMario Scheithauer
On this mainboard there is a legacy PCI device, which is connected to the PCIe root port via a PCIe-2-PCI bridge. This device only supports legacy interrupt routing. For this reason we have to adjust the PIR6 register (0x314c) which is responsible for PCIe device 13h and 14h. This means that the interrupt routing will also be the same for both PCIe devices. The bridge is connected to PCIe root port 2 and 3 over two lanes (Device 13.0 and 13.1). The following routing is required: INTA#->PIRQD#, INTB#->PIRQA#, INTC#->PIRQB#, INTD#->PIRQC# Change-Id: I5028c26769a2122b1c609ad7789c9949e3cb7a87 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29513 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-07siemens/mc_apl4: Add new mainboard variant mc_apl4Mario Scheithauer
This mainboard is based on mc_apl1. In a first step, it concerns a copy of mc_apl1 directory with minimum changes. Special adaptations for mc_apl4 mainboard will follow in separate commits. Change-Id: I3dfdccc8198f3a23a45d319ede6080803a46f7f6 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-11-07siemens/mc_apl2: Adjust GPIO settings for mc_apl2Mario Scheithauer
This mainboard variant requires GPIO adaptations to match the hardware. Change-Id: I16387358d6c6fa15efd16f7ba7f6b89740477e9d Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-07siemens/mc_apl3: Disable I2C7 over devicetreeMario Scheithauer
Disable I2C7 because there is no device connected. Change-Id: Ie9877d40b06f4a849163a873fd308ff03995fcdc Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-07siemens/mc_apl3: Enable all PCIe root portsMario Scheithauer
Enable all PCIe root ports for this mainboard. Change-Id: I62c7ba5048b4c2288bb502a78b9621edda333f2a Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-11-07siemens/mc_apl3: Remove reduced clock rate for I2C0Mario Scheithauer
There is no device on I2C0 which requires a lower clock rate. Change-Id: Ib9ad4d9026267d2079e95245994d84c163b28dbb Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-11-07siemens/mc_apl3: Disable CLKREQ of PCIe root portsMario Scheithauer
All PCIe root ports of this mainboard do not have an associated CLKREQ signal. Therefore the ports are marked with "CLKREQ_DISABLED". Change-Id: I59c1132c6d273ccefeb1be6243577e1ae5064ef4 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-11-07siemens/mc_apl3: Adjust GPIO settings for mc_apl3Mario Scheithauer
This mainboard variant requires GPIO adaptations to match the hardware. Change-Id: I4ba475e7d387f46ed5f41b7a691c7933edbc50c5 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-30siemens/mc_apl3: Add new mainboard variant mc_apl3Mario Scheithauer
This mainboard is based on mc_apl1. In a first step, it concerns a copy of mc_apl1 directory with minimum changes. Special adaptations for mc_apl3 mainboard will follow in separate commits. Change-Id: I963ec63bccf71296c3fdabfcf9f3009c2febc791 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-10-08Move compiler.h to commonlibNico Huber
Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-06soc/intel/common, mb/google, mb/siemens: Use lower case x for RXDFurquan Shaikh
In order to make the macro name consistent for all PAD_CFG1_IOSSTATE_* macros, this change uses lower case x for *RXD*. It helps avoid confusion when using the macros. Change-Id: I6b1ce259ed184bcf8224dff334fcf0a0289f1788 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28924 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-04mc_apl1: Set up SPI OPCODE menu before lockingWerner Zeh
In order to enable the OS SPI driver to use the software interface of this controller the OPCODE menu has to be set up properly before locking the controller. This is done on baseboard level so that all variants will get this done as well. Change-Id: I0bf0619ff0610c00325f03d13b6794aee8a62504 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/28834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2018-10-01siemens/mc_apl1: Activate clock spreading for PTN3460Mario Scheithauer
In order to minimize Electromagnetic Interference (EMI) on the LVDS interface driven by PTN3460, clock spreading must be activated for mc_apl1 mainboard. The modulation ratio is set to 1 % of the nominal frequency. Change-Id: Ie457fcdbb6239dc0b25e2c35ad7a310ee80383f9 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28761 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-27siemens/mc_apl1: Add new mainboard variant mc_apl2Mario Scheithauer
This mainboard is based on mc_apl1. In a first step, it contains a copy of mc_apl1 directory with minimum changes. Special adaptations for mc_apl2 mainboard will follow in separate commits. Change-Id: I0af60ab0dfe556dd95da2cf1a49c685a8f0ae4eb Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-09-27siemens/mc_apl1: Make the DDR memory swizzle data configurableMario Scheithauer
In preparation for a future MC Apollo Lake board which will be equipped with LPDDR4 modules, it is necessary to make the swizzle data configurable. Starting from the mc_apl1 baseboard, which is equipped with DDR3L memory and therefore does not need swizzle data, the structures are initialized with zero. Change-Id: I4954d0a00d1d5fc28a8dda45a9fb27f98d5c3f1e Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-08-31siemens/mc_apl1: Correct the Tx signal from SATA interfaceMario Scheithauer
Because of an incorrect transmit voltage swing, the signal must be adjusted. The factor of slices for full swing level can be corrected via the High Speed I/O Transmit Control Register 3. Change-Id: I116802cd2a944658fc3022e948eba43cebe52bb4 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
2018-08-28siemens/mc_apl1: Extend circuit life by clock gating and power gatingMario Scheithauer
The firmware of devices connected to LPC should deassert the LPC CLKRUN# signal when there is no bus activity on LPC. Necessary changes: - Enable LPC CLKRUN# - Enable LPC PCE (Power Control Enable) - Enable LPC CCE (Clock Control Enable) - Remove I/O decoding range on LPC for COM 3 - Disable I/O UART driver Change-Id: I2fd80e3fdcf23658f97b8182a77df7e09ddf25d6 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-27siemens/mc_apl1: Disable PCI clock outputs on XIO bridgeMario Scheithauer
This patch disables the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridge. Change-Id: I0b9cf51a713f4ab46e71d250397486d136c26177 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-08-24siemens/mc_apl1: Select DDR50 mode for eMMCMario Scheithauer
To increase the lifetime of the circuit, it is necessary to reduce the eMMC speed to DDR50 mode. Change-Id: I40658b44a99e6600ed00950a1a177961f0055e7a Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-08-23siemens/mc_apl1: Make adjustments for the 1st redesign of this mainboardMario Scheithauer
For the 1st redesign of mc_apl1 mainboard some adjustments are necessary: - The FPGA is now connected directly via a PCIe Root Port - Internal Apollo Lake UARTs are now used - Adjusting GPIO settings Change-Id: I8917a52325306f24d1c39a88dac47b0cee760d57 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-08-23siemens/mc_apl1: Move board specific things to mc_apl1 variantMario Scheithauer
A FPGA is not necessarily available in further mc_apl1 variants. So we move the loading of the driver and the notify function to the mc_apl1 variant. Setting the CPU to Max Non-Turbo Ratio is also not absolutely necessary for further variants. Change-Id: I9f8438407f231df08e1ad04655bb6f747257e268 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-06-06soc/intel/common/block: Add common chip config blockSubrata Banik
Adding common chip config structure which will be used to return data to common code. When common code requires soc data, code used to fetch entire soc config structure. With this change, common code will only get the data/structure which is required by common code and not entire config. For now, adding i2c, gspi and lockdown configuration which will be used by common code. BUG=none BRANCH=b:78109109 TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check values are returned properly using common structure. Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/26189 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-08mb/siemens: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: If67ea25a9e1363dde8aefe62b92ee7a61f0458b0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2018-04-27siemens/mc_apl1: Move board specific things to mc_apl1 variantMario Scheithauer
The following things are specific characteristic of mc_apl1 board variant: - initialization for the eDP to LVDS converter - enable decoding address range for COM 3 - legacy IRQ routing for PCI devices - wait function for old legacy devices - set coreboot ready LED Change-Id: I5c853e6caae6cc880ead436f232cabddeee6d09a Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/25822 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-26siemens/mc_apl1: Provide baseboard and variant conceptsMario Scheithauer
Siemens will provide further boards based on Apollo Lake. These differ only slightly. To avoid copying the complete directory of the reference board we simply create variants that only contain the differences, like google/reef does. To further the ability of multiple variant boards to share code provide a place to land the split-up changes. This patch provides the tooling by using a new Kconfig value, VARIANT_DIR, as well as the Make plumbing. The directory layout with a single variant mc_apl1 (which is also the baseboard) looks like this: variants/baseboard - code variants/baseboard/include/baseboard - headers variants/mc_apl1 - code variants/mc_apl1/include/variant - headers New boards would then be added under their board name within the 'variants' directory. No split has been done with providing different logic yet. This is purely an organizational change. Change-Id: Ia3c1f45daee3b9690a448b82edbeec552ee05973 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/25785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-04-24compiler.h: add __weak macroAaron Durbin
Instead of writing out '__attribute__((weak))' use a shorter form. Change-Id: If418a1d55052780077febd2d8f2089021f414b91 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-13siemens/mc_apl1: Fix accuracy issue with IDT PMICMario Scheithauer
Due to an accuracy issue on IMON in the IDT PMIC, the reported system power consumption was higher than the actual consumption. To prevent this problem, a logic must be implemented in mainboard_init(). This logic consists of slope and offset as constants for Vcc and Vnn, which need to be programmed by coreboot. This fix compensates for the accuracy issue. Change-Id: I77faf95951d03ac6ce97a6721dba6e8466122a25 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/25585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-04-11siemens/mc_apl1: Make DRAM configuration more flexibleMario Scheithauer
By storing the FSP-M DRAM configuration parameter in the hwinfo block, one becomes more flexible in case of a change of the DRAM type. The configuration data from hwinfo block is a one-to-one representation of the FSPM_UPD data starting with parameter 'Package' (offset 0x4d) and ending before parameter 'Ch0_Bit_swizzling' (offset 0x88). Change-Id: I58c1df0954a436710ecb59487ece07a0832b0de6 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/25586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-03-16soc/intel/apollolake and mainboards: Use pcie_rp_clkreq_pin arrayFurquan Shaikh
This change uses an array pcie_rp_clkreq_pin for accepting CLKREQ# from mainboards instead of defining a separate property for each root port. This allows us to use memcpy to copy the entire array into FSP params as well as new properties for PCIe root ports can be added as arrays in future CLs. BUG=b:74633273 BRANCH=reef,coral Change-Id: Ifa05f1e38fcfd95063ec327712e472cdbd12dbb7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-07siemens/mc_apl1: Select CONFIG_NC_FPGA_NOTIFY_CB_READYMario Scheithauer
For internal measurements this mainboard needs a marking inside the NC FPGA when coreboot is ready and payload has been loaded. Change-Id: I37908b21e2a077dec7fa99b0db6d1fd9b6878341 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/22356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-11-03siemens/mc_apl1: Enable I2C0 with 100kHzMario Scheithauer
The default setting for I2Cx is 400kHz. On this mainboard there is a device on I2C0 which requires a lower clock rate to work correctly. For this reason we set the frequency to 100kHz. Change-Id: I637a58a0c89ead55ca1176d6aecdfaba5897d64f Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/22140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-03siemens/mc_apl1: Set coreboot ready LEDMario Scheithauer
This mainboard has its own coreboot ready LED. The LED is switched on via GPIO CNV_RGI_DT. Change-Id: I179d013746c1334337dc9e6b7f09ac54eff0cd77 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/22136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-11-03siemens/mc_apl1: Add legacy IRQ routing for PCI devicesMario Scheithauer
On this mainboard there are PCI devices, which are connected to the PCIe root port via a PCIe-2-PCI bridge. One of the devices only supports legacy interrupt routing. For this reason we have to adjust the PIR6 register (0x314c) which is responsible for PCIe device 13h and 14h. This means that the interrupt routing will also be the same for both PCIe devices. The bridge is connected to PCIe root port 4 (Device 14.0). The following routing is required: INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#->PIRQA# Change-Id: I5464c9a2669773bc1e6cd4b4d29d1be838dbfa27 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/22139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-09-26Use stopwatch_wait_until_expired where applicableJonathan Neuschäfer
Change-Id: I4d6c6810b91294a7e401a4a1a446218c04c98e55 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2017-09-21siemens/mc_apl1: Move SCI to IRQ 10Mario Scheithauer
IRQ 9 is used for different purpose on this mainboard so move SCI away to IRQ 10. Change-Id: I7f055447f5d92bc4696b38e8103a7aebde95d9d3 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/21586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-14siemens/mc_apl1: Add delay to wait for legacy devicesWerner Zeh
There are old legacy onboard devices which are too slow for a coreboot boot with log level BIOS_ERR. In this case coreboot is so fast that these devices do not have enough time to become visible on the PCI bus and this in turn leads to missing resource allocation for this devices. The most generic way to work around this problem on existing hardware is to introduce a delay right before the PCI enumeration starts. The needed delay time depends on the hardware and will therefore be get from hwinfo. Change-Id: Ia91babc81e3a347bbc498c3def97b2ea70e10922 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/21518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2017-09-08siemens/mc_apl1: Disable internal UARTsMario Scheithauer
APL internal UARTs are not used on this mainboard. Change-Id: I39118262fc6f37b45785538a3f2d1d31d42cbe86 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/21406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-09-08siemens/mc_apl1: Set bus master bit for on-board PCI deviceMario Scheithauer
There is one on-board PCI device where bus master has to be enabled in PCI configuration space. As there is no need for a complete PCI driver for this device just set the bus master bit in mainboard_final(). Change-Id: I45202937eba11da3bea14fef6ebed70599804335 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/21405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-08-18include/device: Split i2c.h into threeNico Huber
Split `i2c.h` into three pieces to ease reuse of the generic defi- nitions. No code is changed. * `i2c.h` - keeps the generic definitions * `i2c_simple.h` - holds the current, limited to one controller driver per board, devicetree independent I2C interface * `i2c_bus.h` - will become the devicetree compatible interface for native I2C (e.g. non-SMBus) controllers Change-Id: I382d45c70f9314588663e1284f264f877469c74d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-15soc/intel/common/block: Add LPC Common code and use it for APLRavi Sarawadi
Add LPC common code to be shared across Intel platforms. Also add LPC library functions to be shared across platforms. Use common LPC code for Apollo Lake soc. Update existing Apollolake mainboard variants {google,intel,siemens} to use new common LPC header file. Change-Id: I6ac2e9c195b9ecda97415890cc615f4efb04a27a Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/20659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27siemens/mc_apl1: Select skip RAPL configurationMario Scheithauer
The mc_apl1 mainboard needs to disable the RAPL algorithm for a constant power management of the processor package. An active RAPL algorithm leads to negative effects with our real time software. Change-Id: I09ca56a034fd3896a000e64cac35f12fb507a682 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/20760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-20siemens/mc_apl1: Activate ECC for DRAMMario Scheithauer
This mainboard is equipped with DDR3L modules which support ECC. The BWG says that for activating ECC the FSP-M parameter MemoryDown must be set to 5. Change-Id: Idc68df1e2bae2396c9b9788d4a026a75b7d9119b Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/20634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-07-20siemens/mc_apl1: Include platform.aslMario Scheithauer
The OS of this mainboard needs the _PIC method for the selection of the type of interrupt routing. Change-Id: Ic82ba1b368aff0030422d9602ebc882247a2191b Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/20618 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-07-18siemens/mc_apl1: Disable SDCARDMario Scheithauer
SDCARD is not used on this mainboard. Change-Id: I28d23cdb3652bf736b19daf67c7057c396230e24 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/20611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-13Rename __attribute__((packed)) --> __packedStefan Reinauer
Also unify __attribute__ ((..)) to __attribute__((..)) and handle ((__packed__)) like ((packed)) Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/15921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-30mb/siemens/mc_apl1: Set up RTC backup mode to primary cellWerner Zeh
Set RX6110SA RTC backup mode to primary cell. This mode reduces the backup current consumption of the RTC. Change-Id: I7c0c26a0ed5d8f48587acc917f8bb1c5c2b8869a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/20414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-23siemens/mc_apl1: Enable decoding for COM 3 on LPCMario Scheithauer
It does not work to enable the LPC range in the function mainboard_init() because the LPC bus driver closes the range during PCI enumeration again. For this reason, enabling decoding of the address range for COM 3 will be done at a later point in time - mainboard_final(). Change-Id: I452bca4e430b1ea75e4a327591da84500491fe84 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/20295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-06-23siemens/mc_apl1: Disable XDCIMario Scheithauer
With enabled XDCI support we are not able to use USB port 0 over XHCI driver. For this reason, we disable XDCI into devicetree.cb. Change-Id: I1ed721d9ffd44a920a6f1f16855d5b7ceb1b17c5 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/20296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-06-13siemens/mc_apl1: Enable decoding for COM 3 on LPCMario Scheithauer
Since this mainboard provides 3 COM ports on LPC, enable decoding of the corresponding address range for COM 3. Change-Id: I15c0748fce67eef46401c314f441aa45f5e3c5fa Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/20162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-06-13siemens/mc_apl1: Use Siemens NC FPGA driverMario Scheithauer
- use Siemens NC FPGA driver for backlight brightness and PWM control - set Dsave time for board reset after falling edge of signal xdsave Change-Id: I5077d4af162e54a3993e5e0d784a8356f51bd0c9 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/20161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-17siemens/mc_apl1: Program eMMC DLL settingsMario Scheithauer
Program eMMC DLL settings for mc_apl1 mainboard, after that system can boot up with eMMC successfully. Change-Id: I3d60f66ec5c7e09540ccda59f244aac6f78bf954 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/19712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-05-17siemens/mc_apl1: Select external 8250 UARTMario Scheithauer
The mainboard siemens/mc_apl1 uses an external I/O port for console output. For this reason we need to activate the 8250 LPC UART. Change-Id: Ib5616a116aec6135191bdce95f9f9566ce13d6f1 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/19694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-11siemens/mc_apl1: Add usage of external RTC RX6110 SAMario Scheithauer
This mainboard contains an external RTC chip RX6110 SA. Enable usage of this chip and set some initialization values to device tree. Change-Id: I5aceb4401f0bb059ef893dfe7d157716c82e4a76 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/19647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-05-11siemens/mc_apl1: Correct GPIO settingsMario Scheithauer
- set GPIO_183 to high level for enabling the power of SD card - delete all GPIOs for JTAG interface because they lead to problems with Lauterbach debug hardware Change-Id: I24bfff479601933c43e3dcbfa3baa49510831703 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/19623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-05-05mainboard/siemens/mc_apl1: remove unnecessary headerAaron Durbin
soc/i2c.h does not need to be included in this compilation unit. Change-Id: Ife11642d2e69af7235c93fc54bba38853b046169 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-04-04siemens/mc_apl1: Activate PTN3460 eDP to LVDS bridge ICMario Scheithauer
This mainboard uses a LVDS connection for LCD panels. Apollo Lake SoC provides a display controller with three independent pipes (1x eDP and 2x DP/HDMI). PTN3460 is an embedded DisplayPort to LVDS bridge device that enables connectivity between an eDP source and LVDS display panel (http://www.nxp.com/documents/data_sheet/PTN3460.pdf). The bridge contains an On-chip Extended Display Identification Data (EDIT) emulation for EDIT data structures. This patch sets up PTN3460 to be used with the appropriate LCD panel. Change-Id: Ib8fa79bb608f1842f26c1af3d7bf4bb0513fa94d Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/19043 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-29siemens/mc_apl1: Adjust gpio settingsMario Scheithauer
Adjust gpio settings according to the hardware layout. Change-Id: I2f440e863c2e6f59298c500ac5aefa3b7386bcdf Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/18995 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-03-15siemens/mc_apl1: Clean up the codeMario Scheithauer
This patch make some general adaptations in relation to commit 6a489237 (mainboard/intel/leafhill: Clean up). - add necessary defaults to Kconfig - remove irrelevant entries from FMD file - include romstage file for better understanding Change-Id: I190d648a7ffeca11acc6560db85ff03c78e85b21 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/18808 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-02-20siemens/mc_apl1: Set MAC address for all available i210 MACsMario Scheithauer
This mainboard uses two i210 Ethernet controller. Therfore we enable the usage of the i210 driver and have to provide a function to search for a valid MAC address for all i210 devices by using Siemens hwilib. Change-Id: I36246cdef987fcece15a297ebb2f41561fca1f69 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/18380 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-02-15siemens/mc_apl1: Make basic settings for booting the mainboardMario Scheithauer
This commit makes a basic adjustment for GPIOs, device tree, flash map and MRC settings. With these basic settings the mainboard boots into Linux lubuntu 4.8.0-22-generic using SeaBIOS. More adjustments will follow. Change-Id: Ia920d236814f2e6a9b777dd1e4b4feef0ddf7721 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/18292 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-02-02siemens/mc_apl1: Add new mainboardMario Scheithauer
This mainboard is based on Intel's Leafhill CRB with Apollo Lake silicon. In a first step, it concerns only a copy of intel/leafhill directory with minimum changes. Special adaptations for MC APL1 mainboard will follow in separate commits. Change-Id: If0b8a2bc21c99c3be4e6043e8febfb1b91ff0a63 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/18272 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Brenton Dong <brenton.m.dong@intel.com>
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