siemens/mc_apl1: Make adjustments for the 1st redesign of this mainboard

For the 1st redesign of mc_apl1 mainboard some adjustments are
necessary:

- The FPGA is now connected directly via a PCIe Root Port
- Internal Apollo Lake UARTs are now used
- Adjusting GPIO settings

Change-Id: I8917a52325306f24d1c39a88dac47b0cee760d57
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/28270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

2 files changed, 84 insertions, 84 deletions

diff --git a/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c b/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c
index 10eb3d386d..02d0601482 100644
--- a/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c
+++ b/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c
@@ -28,70 +28,70 @@ static const struct pad_config gpio_table[] = {
 	/* Southwest Community */
 
 	/* PCIE_WAKE[0:3]_N */
-	PAD_CFG_NF(GPIO_205, UP_20K, DEEP, NF1),	/* PCIE_WAKE0_N */
-	PAD_CFG_NF(GPIO_206, UP_20K, DEEP, NF1),	/* PCIE_WAKE1_N */
-	PAD_CFG_NF(GPIO_207, UP_20K, DEEP, NF1),	/* PCIE_WAKE2_N */
-	PAD_CFG_NF(GPIO_208, UP_20K, DEEP, NF1),	/* PCIE_WAKE3_N */
+	PAD_CFG_NF(GPIO_205, NONE, DEEP, NF1),		/* PCIE_WAKE0_N */
+	PAD_CFG_NF(GPIO_206, NONE, DEEP, NF1),		/* PCIE_WAKE1_N */
+	PAD_CFG_NF(GPIO_207, NONE, DEEP, NF1),		/* PCIE_WAKE2_N */
+	PAD_CFG_NF(GPIO_208, NONE, DEEP, NF1),		/* PCIE_WAKE3_N */
 
 	/* EMMC interface. */
 	PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1),	/* EMMC_CLK */
-	PAD_CFG_NF(GPIO_157, UP_20K, DEEP, NF1),	/* EMMC_D0 */
-	PAD_CFG_NF(GPIO_158, UP_20K, DEEP, NF1),	/* EMMC_D1 */
-	PAD_CFG_NF(GPIO_159, UP_20K, DEEP, NF1),	/* EMMC_D2 */
-	PAD_CFG_NF(GPIO_160, UP_20K, DEEP, NF1),	/* EMMC_D3 */
-	PAD_CFG_NF(GPIO_161, UP_20K, DEEP, NF1),	/* EMMC_D4 */
-	PAD_CFG_NF(GPIO_162, UP_20K, DEEP, NF1),	/* EMMC_D5 */
-	PAD_CFG_NF(GPIO_163, UP_20K, DEEP, NF1),	/* EMMC_D6 */
-	PAD_CFG_NF(GPIO_164, UP_20K, DEEP, NF1),	/* EMMC_D7 */
-	PAD_CFG_NF(GPIO_165, UP_20K, DEEP, NF1),	/* EMMC_CMD */
+	PAD_CFG_NF(GPIO_157, NONE, DEEP, NF1),		/* EMMC_D0 */
+	PAD_CFG_NF(GPIO_158, NONE, DEEP, NF1),		/* EMMC_D1 */
+	PAD_CFG_NF(GPIO_159, NONE, DEEP, NF1),		/* EMMC_D2 */
+	PAD_CFG_NF(GPIO_160, NONE, DEEP, NF1),		/* EMMC_D3 */
+	PAD_CFG_NF(GPIO_161, NONE, DEEP, NF1),		/* EMMC_D4 */
+	PAD_CFG_NF(GPIO_162, NONE, DEEP, NF1),		/* EMMC_D5 */
+	PAD_CFG_NF(GPIO_163, NONE, DEEP, NF1),		/* EMMC_D6 */
+	PAD_CFG_NF(GPIO_164, NONE, DEEP, NF1),		/* EMMC_D7 */
+	PAD_CFG_NF(GPIO_165, NONE, DEEP, NF1),		/* EMMC_CMD */
 	PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1),	/* EMMC_RCLK */
 
 	/* SDIO -- unused */
 	PAD_CFG_GPI(GPIO_166, DN_20K, DEEP),		/* SDIO_CLK */
-	PAD_CFG_GPI(GPIO_167, DN_20K, DEEP),		/* SDIO_D0 */
+	PAD_CFG_GPI(GPIO_167, NONE, DEEP),		/* SDIO_D0 */
 	/* Configure SDIO to enable power gating. */
-	PAD_CFG_GPI(GPIO_168, DN_20K, DEEP),		/* SDIO_D1 */
-	PAD_CFG_GPI(GPIO_169, DN_20K, DEEP),		/* SDIO_D2 */
-	PAD_CFG_GPI(GPIO_170, DN_20K, DEEP),		/* SDIO_D3 */
-	PAD_CFG_GPI(GPIO_171, DN_20K, DEEP),		/* SDIO_CMD */
+	PAD_CFG_GPI(GPIO_168, NONE, DEEP),		/* SDIO_D1 */
+	PAD_CFG_GPI(GPIO_169, NONE, DEEP),		/* SDIO_D2 */
+	PAD_CFG_GPI(GPIO_170, NONE, DEEP),		/* SDIO_D3 */
+	PAD_CFG_GPI(GPIO_171, NONE, DEEP),		/* SDIO_CMD */
 
 	/* SDCARD */
 	/* Pull down clock by 20K. */
 	PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1),	/* SDCARD_CLK */
-	PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1),	/* SDCARD_D0 */
-	PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1),	/* SDCARD_D1 */
-	PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1),	/* SDCARD_D2 */
-	PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1),	/* SDCARD_D3 */
+	PAD_CFG_NF(GPIO_173, NONE, DEEP, NF1),		/* SDCARD_D0 */
+	PAD_CFG_NF(GPIO_174, NONE, DEEP, NF1),		/* SDCARD_D1 */
+	PAD_CFG_NF(GPIO_175, NONE, DEEP, NF1),		/* SDCARD_D2 */
+	PAD_CFG_NF(GPIO_176, NONE, DEEP, NF1),		/* SDCARD_D3 */
 	/* Card detect is active LOW with external pull up. */
-	PAD_CFG_NF(GPIO_177, UP_20K, DEEP, NF1),	/* SDCARD_CD_N */
-	PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1),	/* SDCARD_CMD */
+	PAD_CFG_NF(GPIO_177, NONE, DEEP, NF1),		/* SDCARD_CD_N */
+	PAD_CFG_NF(GPIO_178, NONE, DEEP, NF1),		/* SDCARD_CMD */
 	/* CLK feedback, internal signal, needs 20K pull down. */
 	PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1),	/* SDCARD_CLK_FB */
-	PAD_CFG_GPI(GPIO_186, UP_20K, DEEP),		/* SDCARD_LVL_WP */
+	PAD_CFG_GPI(GPIO_186, NONE, DEEP),		/* SDCARD_LVL_WP */
 	/* EN_SD_SOCKET_PWR_L for SD slot power control. Default on. */
 	PAD_CFG_GPO(GPIO_183, 1, DEEP),			/* SDIO_PWR_DOWN_N */
 
 	/* SMBus */
-	PAD_CFG_GPI(SMB_ALERTB, UP_20K, DEEP),		/* SMB_ALERT _N */
-	PAD_CFG_NF(SMB_CLK, UP_20K, DEEP, NF1),		/* SMB_CLK */
-	PAD_CFG_NF(SMB_DATA, UP_20K, DEEP, NF1),	/* SMB_DATA */
+	PAD_CFG_GPI(SMB_ALERTB, NONE, DEEP),		/* SMB_ALERT _N */
+	PAD_CFG_NF(SMB_CLK, NONE, DEEP, NF1),		/* SMB_CLK */
+	PAD_CFG_NF(SMB_DATA, NONE, DEEP, NF1),		/* SMB_DATA */
 
 	/* LPC */
-	PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1),	/* LPC_SERIRQ */
+	PAD_CFG_NF(LPC_ILB_SERIRQ, NONE, DEEP, NF1),	/* LPC_SERIRQ */
 	PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1),	/* LPC_CLKOUT0 */
 	PAD_CFG_GPI(LPC_CLKOUT1, UP_20K, DEEP),		/* LPC_CLKOUT1 */
-	PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1),		/* LPC_AD0 */
-	PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1),		/* LPC_AD1 */
-	PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1),		/* LPC_AD2 */
-	PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1),		/* LPC_AD3 */
-	PAD_CFG_GPI(LPC_CLKRUNB, UP_20K, DEEP),		/* LPC_CLKRUN_N */
-	PAD_CFG_NF(LPC_FRAMEB, UP_20K, DEEP, NF1),	/* LPC_FRAME_N */
+	PAD_CFG_NF(LPC_AD0, NONE, DEEP, NF1),		/* LPC_AD0 */
+	PAD_CFG_NF(LPC_AD1, NONE, DEEP, NF1),		/* LPC_AD1 */
+	PAD_CFG_NF(LPC_AD2, NONE, DEEP, NF1),		/* LPC_AD2 */
+	PAD_CFG_NF(LPC_AD3, NONE, DEEP, NF1),		/* LPC_AD3 */
+	PAD_CFG_GPI(LPC_CLKRUNB, NONE, DEEP),		/* LPC_CLKRUN_N */
+	PAD_CFG_NF(LPC_FRAMEB, NONE, DEEP, NF1),	/* LPC_FRAME_N */
 
 	/* West Community */
 
 	/* I2C0 - I2C Level Shifter */
-	PAD_CFG_NF(GPIO_124, UP_2K, DEEP, NF1),		/* LPSS_I2C0_SDA */
-	PAD_CFG_NF(GPIO_125, UP_2K, DEEP, NF1),		/* LPSS_I2C0_SCL */
+	PAD_CFG_NF(GPIO_124, NONE, DEEP, NF1),		/* LPSS_I2C0_SDA */
+	PAD_CFG_NF(GPIO_125, NONE, DEEP, NF1),		/* LPSS_I2C0_SCL */
 
 	/* I2C[1:7] -- unused */
 	PAD_CFG_GPI(GPIO_126, UP_20K, DEEP),		/* LPSS_I2C1_SDA */
@@ -122,10 +122,10 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI(GPIO_155, DN_20K, DEEP),		/* ISH_GPIO_9 */
 
 	/* PCIE_CLKREQ[0:3]_N */
-	PAD_CFG_NF(GPIO_209, UP_20K, DEEP, NF1),
-	PAD_CFG_NF(GPIO_210, UP_20K, DEEP, NF1),
-	PAD_CFG_NF(GPIO_211, UP_20K, DEEP, NF1),
-	PAD_CFG_NF(GPIO_212, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPIO_209, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPIO_210, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPIO_211, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPIO_212, NONE, DEEP, NF1),
 
 	/* OSC_CLK_OUT_0 - RES_CLK_CPU_FPGA */
 	PAD_CFG_NF(OSC_CLK_OUT_0, DN_20K, DEEP, NF1),
@@ -136,10 +136,10 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI(OSC_CLK_OUT_4, DN_20K, DEEP),
 
 	/* PMU Signals */
-	PAD_CFG_GPI(PMU_AC_PRESENT, DN_20K, DEEP),	/* PMU_AC_PRESENT */
+	PAD_CFG_GPI(PMU_AC_PRESENT, NONE, DEEP),	/* PMU_AC_PRESENT */
 	PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1),	/* PMU_BATLOW_N */
 	PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1),	/* PMU_PLTRST_N */
-	PAD_CFG_NF(PMU_PWRBTN_B, UP_20K, DEEP, NF1),	/* PMU_PWRBTN_N */
+	PAD_CFG_NF(PMU_PWRBTN_B, NONE, DEEP, NF1),	/* PMU_PWRBTN_N */
 	PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1),	/* PMU_RSTBTN_N */
 	/* PMU_SLP_S0_N */
 	PAD_CFG_NF_IOSSTATE(PMU_SLP_S0_B, NONE, DEEP, NF1, IGNORE),
@@ -156,25 +156,25 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI(GPIO_187, DN_20K, DEEP),		/* HV_DDI0_DDC_SDA */
 	PAD_CFG_GPI(GPIO_188, DN_20K, DEEP),		/* HV_DDI0_DDC_SCL */
 	/* DDI1 SDA and SCL - Display-Port */
-	PAD_CFG_NF(GPIO_189, UP_20K, DEEP, NF1),	/* HV_DDI1_DDC_SDA */
-	PAD_CFG_NF(GPIO_190, UP_20K, DEEP, NF1),	/* HV_DDI1_DDC_SCL */
+	PAD_CFG_NF(GPIO_189, NONE, DEEP, NF1),		/* HV_DDI1_DDC_SDA */
+	PAD_CFG_NF(GPIO_190, NONE, DEEP, NF1),		/* HV_DDI1_DDC_SCL */
 
 	/* MIPI I2C -- unused */
 	PAD_CFG_GPI(GPIO_191, DN_20K, DEEP),		/* MIPI_I2C_SDA */
 	PAD_CFG_GPI(GPIO_192, DN_20K, DEEP),		/* MIPI_I2C_SCL */
 
 	/* Panel 0 control -- unused */
-	PAD_CFG_GPI(GPIO_193, DN_20K, DEEP),		/* PNL0_VDDEN */
-	PAD_CFG_GPI(GPIO_194, DN_20K, DEEP),		/* PNL0_BKLTEN */
-	PAD_CFG_GPI(GPIO_195, DN_20K, DEEP),		/* PNL0_BKLTCTL */
+	PAD_CFG_TERM_GPO(GPIO_193, 0, DN_20K, DEEP),	/* PNL0_VDDEN */
+	PAD_CFG_TERM_GPO(GPIO_194, 0, DN_20K, DEEP),	/* PNL0_BKLTEN */
+	PAD_CFG_TERM_GPO(GPIO_195, 0, DN_20K, DEEP),	/* PNL0_BKLTCTL */
 
 	/* Panel 1 control -- unused */
-	PAD_CFG_NF(GPIO_196, DN_20K, DEEP, NF1),	/* PNL1_VDDEN */
-	PAD_CFG_NF(GPIO_197, DN_20K, DEEP, NF1),	/* PNL1_BKLTEN */
-	PAD_CFG_NF(GPIO_198, DN_20K, DEEP, NF1),	/* PNL1_BKLTCTL */
+	PAD_CFG_GPI(GPIO_196, DN_20K, DEEP),		/* PNL1_VDDEN */
+	PAD_CFG_GPI(GPIO_197, DN_20K, DEEP),		/* PNL1_BKLTEN */
+	PAD_CFG_GPI(GPIO_198, DN_20K, DEEP),		/* PNL1_BKLTCTL */
 
 	/* DDI[0:1]_HPD -- unused */
-	PAD_CFG_GPI(GPIO_199, UP_20K, DEEP),		/* XHPD_DP */
+	PAD_CFG_GPI(GPIO_199, NONE, DEEP),		/* XHPD_DP */
 	PAD_CFG_GPI(GPIO_200, DN_20K, DEEP),		/* unused */
 
 	/* MDSI signals -- unused */
@@ -182,12 +182,12 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI(GPIO_202, DN_20K, DEEP),		/* MDSI_C_TE */
 
 	/* USB overcurrent pins. */
-	PAD_CFG_NF(GPIO_203, UP_20K, DEEP, NF1),	/* USB_OC0_N */
-	PAD_CFG_NF(GPIO_204, UP_20K, DEEP, NF1),	/* USB_OC1_N */
+	PAD_CFG_NF(GPIO_203, NONE, DEEP, NF1),		/* USB_OC0_N */
+	PAD_CFG_NF(GPIO_204, NONE, DEEP, NF1),		/* USB_OC1_N */
 
 	/* PMC SPI -- almost entirely unused. */
 	PAD_CFG_GPI(PMC_SPI_FS0, UP_20K, DEEP),
-	PAD_CFG_NF(PMC_SPI_FS1, UP_20K, DEEP, NF2),	/* XHPD_EDP_APL */
+	PAD_CFG_NF(PMC_SPI_FS1, NONE, DEEP, NF2),	/* XHPD_EDP_APL */
 	PAD_CFG_GPI(PMC_SPI_FS2, UP_20K, DEEP),
 	PAD_CFG_GPI(PMC_SPI_RXD, DN_20K, DEEP),
 	PAD_CFG_GPI(PMC_SPI_TXD, DN_20K, DEEP),
@@ -195,16 +195,16 @@ static const struct pad_config gpio_table[] = {
 
 	/* PMIC Signals unused signals related to an old PMIC interface. */
 	PAD_CFG_GPO(PMIC_PWRGOOD, 1, DEEP),		/* PMIC_PWRGOOD */
-	PAD_CFG_GPI(PMIC_RESET_B, NONE, DEEP),		/* PMIC_RESET_B */
-	PAD_CFG_GPI(GPIO_213, DN_20K, DEEP),		/* NFC_OUT_RESERVE */
-	PAD_CFG_GPI(GPIO_214, DN_20K, DEEP),		/* NFC_EN */
+	PAD_CFG_GPI(PMIC_RESET_B, DN_20K, DEEP),	/* PMIC_RESET_B */
+	PAD_CFG_TERM_GPO(GPIO_213, 0, DN_20K, DEEP),	/* NFC_OUT_RESERVE */
+	PAD_CFG_TERM_GPO(GPIO_214, 0, DN_20K, DEEP),	/* NFC_EN */
 	PAD_CFG_GPI(GPIO_215, DN_20K, DEEP),		/* NFC_IN_RESERVE */
 	/* THERMTRIP_N */
 	PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1),
-	PAD_CFG_GPO(PMIC_STDBY, 1, DEEP),		/* unused */
-	PAD_CFG_NF(PROCHOT_B, UP_20K, DEEP, NF1),	/* PROCHOT_N */
-	PAD_CFG_NF(PMIC_I2C_SCL, UP_1K, DEEP, NF1),	/* PMIC_I2C_SCL */
-	PAD_CFG_NF(PMIC_I2C_SDA, UP_1K, DEEP, NF1),	/* PMIC_I2C_SDA */
+	PAD_CFG_GPO(PMIC_STDBY, 0, DEEP),		/* unused */
+	PAD_CFG_NF(PROCHOT_B, NONE, DEEP, NF1),		/* PROCHOT_N */
+	PAD_CFG_NF(PMIC_I2C_SCL, NONE, DEEP, NF1),	/* PMIC_I2C_SCL */
+	PAD_CFG_NF(PMIC_I2C_SDA, NONE, DEEP, NF1),	/* PMIC_I2C_SDA */
 
 	/* I2S1 -- unused */
 	PAD_CFG_GPI(GPIO_74, DN_20K, DEEP),		/* I2S1_MCLK */
@@ -271,7 +271,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI(GPIO_120, DN_20K, DEEP),		/* GP_SSP_2_FS1 */
 	PAD_CFG_GPI(GPIO_121, DN_20K, DEEP),		/* GP_SSP_2_FS2 */
 	PAD_CFG_GPI(GPIO_122, DN_20K, DEEP),		/* GP_SSP_2_RXD */
-	PAD_CFG_GPI(GPIO_123, UP_20K, DEEP),		/* GP_SSP_2_TXD */
+	PAD_CFG_GPI(GPIO_123, NONE, DEEP),		/* GP_SSP_2_TXD */
 
 	/* North Community */
 
@@ -296,8 +296,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI(GPIO_16, DN_20K, DEEP),	/* TRACE_1_DATA6_VNN */
 	PAD_CFG_GPI(GPIO_17, DN_20K, DEEP),	/* TRACE_1_DATA7_VNN */
 
-	PAD_CFG_GPI(GPIO_18, UP_20K, DEEP),	/* TRACE_2_CLK_VNN */
-	PAD_CFG_GPI(GPIO_19, UP_20K, DEEP),	/* TRACE_2_DATA0_VNN */
+	PAD_CFG_GPI(GPIO_18, DN_20K, DEEP),	/* TRACE_2_CLK_VNN */
+	PAD_CFG_GPI(GPIO_19, DN_20K, DEEP),	/* TRACE_2_DATA0_VNN */
 	PAD_CFG_GPI(GPIO_20, DN_20K, DEEP),	/* TRACE_2_DATA1_VNN */
 	PAD_CFG_GPI(GPIO_21, DN_20K, DEEP),	/* TRACE_2_DATA2_VNN */
 	PAD_CFG_GPI(GPIO_22, DN_20K, DEEP),	/* TRACE_2_DATA3_VNN */
@@ -311,8 +311,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI(GPIO_29, DN_20K, DEEP),	/* TRIGIN_0 */
 
 	PAD_CFG_GPI(GPIO_30, DN_20K, DEEP),	/* ISH_GPIO_12 */
-	PAD_CFG_GPI(GPIO_31, DN_20K, DEEP),	/* ISH_GPIO_13 */
-	PAD_CFG_GPI(GPIO_32, DN_20K, DEEP),	/* ISH_GPIO_14 */
+	PAD_CFG_GPO(GPIO_31, 1, DEEP),		/* ISH_GPIO_13 */
+	PAD_CFG_GPI(GPIO_32, NONE, DEEP),	/* ISH_GPIO_14 */
 	PAD_CFG_GPI(GPIO_33, DN_20K, DEEP),	/* ISH_GPIO_15 */
 
 	/* PWM[0:3] -- unused */
@@ -326,7 +326,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI(GPIO_39, DN_20K, DEEP),	/* LPSS_UART0_TXD - unused */
 	PAD_CFG_GPI(GPIO_40, DN_20K, DEEP),	/* LPSS_UART0_RTS - unused */
 	PAD_CFG_GPI(GPIO_41, UP_20K, DEEP),	/* LPSS_UART0_CTS - unused */
-	PAD_CFG_GPI(GPIO_42, UP_20K, DEEP),	/* LPSS_UART1_RXD - unused */
+	PAD_CFG_GPI(GPIO_42, NONE, DEEP),	/* LPSS_UART1_RXD - unused */
 	PAD_CFG_GPI(GPIO_43, DN_20K, DEEP),	/* LPSS_UART1_TXD - unused */
 	PAD_CFG_GPI(GPIO_44, UP_20K, DEEP),	/* LPSS_UART1_RTS - unused */
 	PAD_CFG_GPI(GPIO_45, UP_20K, DEEP),	/* LPSS_UART1_CTS - unused */
@@ -390,20 +390,20 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_GPO(GPIO_152, 0, DEEP),		/* PERST# */
 
 	/* SMBus */
-	PAD_CFG_NF(SMB_CLK, UP_20K, DEEP, NF1),		/* SMB_CLK */
-	PAD_CFG_NF(SMB_DATA, UP_20K, DEEP, NF1),	/* SMB_DATA */
+	PAD_CFG_NF(SMB_CLK, NONE, DEEP, NF1),		/* SMB_CLK */
+	PAD_CFG_NF(SMB_DATA, NONE, DEEP, NF1),		/* SMB_DATA */
 
 	/* LPC */
-	PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1),	/* LPC_SERIRQ */
-	PAD_CFG_NF(LPC_CLKOUT0, UP_20K, DEEP, NF1),	/* LPC_CLKOUT0 */
+	PAD_CFG_NF(LPC_ILB_SERIRQ, NONE, DEEP, NF1),	/* LPC_SERIRQ */
+	PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1),	/* LPC_CLKOUT0 */
 	/* LPC_CLKOUT1 - unused */
 	PAD_CFG_GPI(LPC_CLKOUT1, DN_20K, DEEP),
-	PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1),		/* LPC_AD0 */
-	PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1),		/* LPC_AD1 */
-	PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1),		/* LPC_AD2 */
-	PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1),		/* LPC_AD3 */
-	PAD_CFG_GPI(LPC_CLKRUNB, UP_20K, DEEP),		/* LPC_CLKRUN_N */
-	PAD_CFG_NF(LPC_FRAMEB, UP_20K, DEEP, NF1),	/* LPC_FRAME_N */
+	PAD_CFG_NF(LPC_AD0, NONE, DEEP, NF1),		/* LPC_AD0 */
+	PAD_CFG_NF(LPC_AD1, NONE, DEEP, NF1),		/* LPC_AD1 */
+	PAD_CFG_NF(LPC_AD2, NONE, DEEP, NF1),		/* LPC_AD2 */
+	PAD_CFG_NF(LPC_AD3, NONE, DEEP, NF1),		/* LPC_AD3 */
+	PAD_CFG_GPI(LPC_CLKRUNB, NONE, DEEP),		/* LPC_CLKRUN_N */
+	PAD_CFG_NF(LPC_FRAMEB, NONE, DEEP, NF1),	/* LPC_FRAME_N */
 };
 
 const struct pad_config *__weak
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
index 4d9c655434..a273a5983f 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
@@ -8,7 +8,7 @@ chip soc/intel/apollolake
 
 	# Disable unused clkreq of PCIe root ports
 	register "pcie_rp_clkreq_pin[0]" = "3" # PCIe-PCI-Bridge
-	register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[1]" = "2" # FPGA
 	register "pcie_rp_clkreq_pin[2]" = "0" # MACPHY
 	register "pcie_rp_clkreq_pin[3]" = "1" # MACPHY
 	register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
@@ -73,7 +73,7 @@ chip soc/intel/apollolake
 		device pci 13.2 off end	# - RP 4 - PCIe-A 2
 		device pci 13.3 off end	# - RP 5 - PCIe-A 3
 		device pci 14.0 on  end	# - RP 0 - PCIe-B 0 - PCIe-PCI-Bridge
-		device pci 14.1 off end	# - RP 1 - PCIe-B 1
+		device pci 14.1 on  end	# - RP 1 - PCIe-B 1 - FPGA
 		device pci 15.0 on  end	# - XHCI
 		device pci 15.1 off end	# - XDCI
 		device pci 16.0 on	# - I2C 0
@@ -98,10 +98,10 @@ chip soc/intel/apollolake
 		device pci 17.1 off end	# - I2C 5
 		device pci 17.2 off end	# - I2C 6
 		device pci 17.3 on  end	# - I2C 7
-		device pci 18.0 off end	# - UART 0
-		device pci 18.1 off end	# - UART 1
-		device pci 18.2 off end	# - UART 2
-		device pci 18.3 off end	# - UART 3
+		device pci 18.0 on  end	# - UART 0
+		device pci 18.1 on  end	# - UART 1
+		device pci 18.2 on  end	# - UART 2
+		device pci 18.3 on  end	# - UART 3
 		device pci 19.0 off end	# - SPI 0
 		device pci 19.1 off end	# - SPI 1
 		device pci 19.2 off end	# - SPI 2