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path: root/src/mainboard/siemens/mc_apl1/variants
AgeCommit message (Expand)Author
2018-11-16siemens/mc_apl4: Clean up ramstageMario Scheithauer
2018-11-16siemens/mc_apl4: Overwrite swizzle data for LPDDR4Mario Scheithauer
2018-11-12siemens/mc_apl4: Enable SDCARDMario Scheithauer
2018-11-12siemens/mc_apl4: Remove external RTC from I2C0Mario Scheithauer
2018-11-12siemens/mc_apl4: Enable all PCIe root portsMario Scheithauer
2018-11-12siemens/mc_apl4: Remove reduced clock rate for I2C0Mario Scheithauer
2018-11-12siemens/mc_apl4: Disable CLKREQ of PCIe root portsMario Scheithauer
2018-11-12siemens/mc_apl3: Disable PCI clock outputs on XIO bridgesMario Scheithauer
2018-11-12siemens/mc_apl3: Set Full Reset Bit into Reset Control RegisterMario Scheithauer
2018-11-12siemens/mc_apl3: Set bus master bit for on-board PCI deviceMario Scheithauer
2018-11-12siemens/mc_apl3: Remove the correction of the Tx signal for SATAMario Scheithauer
2018-11-12siemens/mc_apl3: Adjust Legacy IRQ routing for PCI devicesMario Scheithauer
2018-11-07siemens/mc_apl4: Add new mainboard variant mc_apl4Mario Scheithauer
2018-11-07siemens/mc_apl2: Adjust GPIO settings for mc_apl2Mario Scheithauer
2018-11-07siemens/mc_apl3: Disable I2C7 over devicetreeMario Scheithauer
2018-11-07siemens/mc_apl3: Enable all PCIe root portsMario Scheithauer
2018-11-07siemens/mc_apl3: Remove reduced clock rate for I2C0Mario Scheithauer
2018-11-07siemens/mc_apl3: Disable CLKREQ of PCIe root portsMario Scheithauer
2018-11-07siemens/mc_apl3: Adjust GPIO settings for mc_apl3Mario Scheithauer
2018-10-30siemens/mc_apl3: Add new mainboard variant mc_apl3Mario Scheithauer
2018-10-08Move compiler.h to commonlibNico Huber
2018-10-06soc/intel/common, mb/google, mb/siemens: Use lower case x for RXDFurquan Shaikh
2018-10-01siemens/mc_apl1: Activate clock spreading for PTN3460Mario Scheithauer
2018-09-27siemens/mc_apl1: Add new mainboard variant mc_apl2Mario Scheithauer
2018-09-27siemens/mc_apl1: Make the DDR memory swizzle data configurableMario Scheithauer
2018-08-31siemens/mc_apl1: Correct the Tx signal from SATA interfaceMario Scheithauer
2018-08-28siemens/mc_apl1: Extend circuit life by clock gating and power gatingMario Scheithauer
2018-08-27siemens/mc_apl1: Disable PCI clock outputs on XIO bridgeMario Scheithauer
2018-08-24siemens/mc_apl1: Select DDR50 mode for eMMCMario Scheithauer
2018-08-23siemens/mc_apl1: Make adjustments for the 1st redesign of this mainboardMario Scheithauer
2018-08-23siemens/mc_apl1: Move board specific things to mc_apl1 variantMario Scheithauer
2018-06-06soc/intel/common/block: Add common chip config blockSubrata Banik
2018-04-27siemens/mc_apl1: Move board specific things to mc_apl1 variantMario Scheithauer
2018-04-26siemens/mc_apl1: Provide baseboard and variant conceptsMario Scheithauer
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