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variants
Age
Commit message (
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Author
2018-10-30
siemens/mc_apl3: Add new mainboard variant mc_apl3
Mario Scheithauer
2018-10-08
Move compiler.h to commonlib
Nico Huber
2018-10-06
soc/intel/common, mb/google, mb/siemens: Use lower case x for RXD
Furquan Shaikh
2018-10-01
siemens/mc_apl1: Activate clock spreading for PTN3460
Mario Scheithauer
2018-09-27
siemens/mc_apl1: Add new mainboard variant mc_apl2
Mario Scheithauer
2018-09-27
siemens/mc_apl1: Make the DDR memory swizzle data configurable
Mario Scheithauer
2018-08-31
siemens/mc_apl1: Correct the Tx signal from SATA interface
Mario Scheithauer
2018-08-28
siemens/mc_apl1: Extend circuit life by clock gating and power gating
Mario Scheithauer
2018-08-27
siemens/mc_apl1: Disable PCI clock outputs on XIO bridge
Mario Scheithauer
2018-08-24
siemens/mc_apl1: Select DDR50 mode for eMMC
Mario Scheithauer
2018-08-23
siemens/mc_apl1: Make adjustments for the 1st redesign of this mainboard
Mario Scheithauer
2018-08-23
siemens/mc_apl1: Move board specific things to mc_apl1 variant
Mario Scheithauer
2018-06-06
soc/intel/common/block: Add common chip config block
Subrata Banik
2018-04-27
siemens/mc_apl1: Move board specific things to mc_apl1 variant
Mario Scheithauer
2018-04-26
siemens/mc_apl1: Provide baseboard and variant concepts
Mario Scheithauer