| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-08-28 | siemens/mc_apl1: Extend circuit life by clock gating and power gating | Mario Scheithauer |
| 2018-08-27 | siemens/mc_apl1: Disable PCI clock outputs on XIO bridge | Mario Scheithauer |
| 2018-08-24 | siemens/mc_apl1: Select DDR50 mode for eMMC | Mario Scheithauer |
| 2018-08-23 | siemens/mc_apl1: Make adjustments for the 1st redesign of this mainboard | Mario Scheithauer |
| 2018-08-23 | siemens/mc_apl1: Move board specific things to mc_apl1 variant | Mario Scheithauer |
| 2018-06-06 | soc/intel/common/block: Add common chip config block | Subrata Banik |
| 2018-04-27 | siemens/mc_apl1: Move board specific things to mc_apl1 variant | Mario Scheithauer |
| 2018-04-26 | siemens/mc_apl1: Provide baseboard and variant concepts | Mario Scheithauer |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |