| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-11-12 | siemens/mc_apl3: Disable PCI clock outputs on XIO bridges | Mario Scheithauer |
| 2018-11-12 | siemens/mc_apl3: Set Full Reset Bit into Reset Control Register | Mario Scheithauer |
| 2018-11-12 | siemens/mc_apl3: Set bus master bit for on-board PCI device | Mario Scheithauer |
| 2018-11-12 | siemens/mc_apl3: Remove the correction of the Tx signal for SATA | Mario Scheithauer |
| 2018-11-12 | siemens/mc_apl3: Adjust Legacy IRQ routing for PCI devices | Mario Scheithauer |
| 2018-11-07 | siemens/mc_apl3: Disable I2C7 over devicetree | Mario Scheithauer |
| 2018-11-07 | siemens/mc_apl3: Enable all PCIe root ports | Mario Scheithauer |
| 2018-11-07 | siemens/mc_apl3: Remove reduced clock rate for I2C0 | Mario Scheithauer |
| 2018-11-07 | siemens/mc_apl3: Disable CLKREQ of PCIe root ports | Mario Scheithauer |
| 2018-11-07 | siemens/mc_apl3: Adjust GPIO settings for mc_apl3 | Mario Scheithauer |
| 2018-10-30 | siemens/mc_apl3: Add new mainboard variant mc_apl3 | Mario Scheithauer |
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index : coreboot.git | |
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