coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2019-07-18	mb/siemens/{mc_apl1,...,mc_apl5}: Fix GPIO settings	Mario Scheithauer
2019-07-11	mb/siemens/{baseboard,mc_apl3,mc_apl4,mc_apl5}: Fix GPIO_168	Mario Scheithauer
2018-10-08	Move compiler.h to commonlib	Nico Huber
2018-10-06	soc/intel/common, mb/google, mb/siemens: Use lower case x for RXD	Furquan Shaikh
2018-09-27	siemens/mc_apl1: Make the DDR memory swizzle data configurable	Mario Scheithauer
2018-08-28	siemens/mc_apl1: Extend circuit life by clock gating and power gating	Mario Scheithauer
2018-08-23	siemens/mc_apl1: Make adjustments for the 1st redesign of this mainboard	Mario Scheithauer
2018-04-27	siemens/mc_apl1: Move board specific things to mc_apl1 variant	Mario Scheithauer
2018-04-26	siemens/mc_apl1: Provide baseboard and variant concepts	Mario Scheithauer