| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-04-26 | siemens/mc_apl1: Provide baseboard and variant concepts | Mario Scheithauer |
| 2018-03-16 | soc/intel/apollolake and mainboards: Use pcie_rp_clkreq_pin array | Furquan Shaikh |
| 2017-11-03 | siemens/mc_apl1: Enable I2C0 with 100kHz | Mario Scheithauer |
| 2017-09-21 | siemens/mc_apl1: Move SCI to IRQ 10 | Mario Scheithauer |
| 2017-09-08 | siemens/mc_apl1: Disable internal UARTs | Mario Scheithauer |
| 2017-07-18 | siemens/mc_apl1: Disable SDCARD | Mario Scheithauer |
| 2017-06-30 | mb/siemens/mc_apl1: Set up RTC backup mode to primary cell | Werner Zeh |
| 2017-06-23 | siemens/mc_apl1: Disable XDCI | Mario Scheithauer |
| 2017-05-17 | siemens/mc_apl1: Program eMMC DLL settings | Mario Scheithauer |
| 2017-05-11 | siemens/mc_apl1: Add usage of external RTC RX6110 SA | Mario Scheithauer |
| 2017-02-15 | siemens/mc_apl1: Make basic settings for booting the mainboard | Mario Scheithauer |
| 2017-02-02 | siemens/mc_apl1: Add new mainboard | Mario Scheithauer |
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index : coreboot.git | |
| my copy of coreboot | gitea |
| aboutsummaryrefslogtreecommitdiff |