coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-11-03	mb/purism/librem_whl: rename to librem_cnl	Matt DeVillier
2020-10-26	mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`	Michael Niewöhner
2020-10-13	{src/mb,util/autoport}: Use macro for DSDT revision	Elyes HAOUAS
2020-10-05	soc/intel/common/block/acpi: Factor out common platform.asl	Subrata Banik
2020-09-28	mb/purism/librem_whl: Drop 3Gbps SATA limit; enable and set SATA tuning params	Matt DeVillier
2020-09-06	mb/*: devicetree: drop now unneeded USBx_PORT_EMPTY	Michael Niewöhner
2020-09-04	soc/intel/cnl: Enable HECI3 depending on devicetree	Felix Singer
2020-08-23	soc/intel/cnl: Configure FSP option PcieRpSlotImplemented	Nico Huber
2020-08-21	mb/purism/librem_whl: Convert GPIOs to macros	Matt DeVillier
2020-08-18	mb/purism/librem_whl: Add new board Librem Mini (WHL-U)	Matt DeVillier