| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-07-11 | skylake: Remove "IshEnable" | li feng |
| 2018-06-14 | src: Get rid of unneeded whitespace | Elyes HAOUAS |
| 2018-06-06 | soc/intel/common/block: Add common chip config block | Subrata Banik |
| 2018-06-05 | soc/intel/skylake: Add option to skip coreboot MP init | Subrata Banik |
| 2018-04-06 | purism/librem_skl: Add AC/DC LoadLine to VR Config | Youness Alaoui |
| 2018-04-06 | purism/librem_skl: Set TCC Activation at 95C | Youness Alaoui |
| 2018-04-06 | purism/librem_skl: Enable VMX and Intel SpeedStep in devicetree | Youness Alaoui |
| 2018-04-06 | purism/librem_skl: Enable TPM support | Youness Alaoui |
| 2018-03-28 | soc/intel/skylake: Limit xDCI feature when VBOOT is enabled | Duncan Laurie |
| 2018-03-26 | purism/librem13v1, librem13v2, liberm15v3: Fix EC LPC I/O port | Youness Alaoui |
| 2017-10-26 | purism/librem_skl: add new variant Librem 15 v3 | Matt DeVillier |
| 2017-10-26 | purism/librem13v2: convert to variant setup | Matt DeVillier |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |