index
:
coreboot.git
macbookair5_2
macbookpro10_1
main
master
mbp101_medisable
mbp101_medisable_1
mbp82
x230
my copy of coreboot
User &
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
mainboard
/
purism
/
librem_cnl
/
variants
/
librem_mini
/
devicetree.cb
Age
Commit message (
Expand
)
Author
2020-12-15
mb/purism/librem_mini: Adjust PL1/2 levels
Matt DeVillier
2020-12-08
mb/*: Remove SATA mode config for CNL based mainboards
Felix Singer
2020-12-08
soc/intel/cannonlake: Align SATA mode names with soc/skl
Felix Singer
2020-11-09
mb/purism/librem_mini: Fix USB_OC mapping in devicetree
Matt DeVillier
2020-11-09
mb/purism/librem_mini: drop PcieRpSlotImplemented from LAN PCIe
Matt DeVillier
2020-11-09
mb/purism/librem_mini: Update smbios_slot_desc for M.2/WLAN
Matt DeVillier
2020-11-09
mb/purism/librem_mini: Fix PCIe clock source mapping in devicetree
Matt DeVillier
2020-11-04
mb/purism/librem_cnl: Set SaGv to FixedHigh
Angel Pons
2020-11-04
mb/purism_librem_mini: Add child device, slot descriptions to PCIe RPs
Matt DeVillier
2020-11-04
mb/purism/librem_mini: Reorganize devicetree
Matt DeVillier
2020-11-04
mb/purism/librem_mini: drop unused HeciEnabled register
Matt DeVillier
2020-11-04
mb/purism/librem_mini: Increase TDP/PL2 setting
Matt DeVillier
2020-11-04
mb/purism/librem_mini: Drop devicetree settings which default to 0
Matt DeVillier
2020-11-04
mb/purism/librem_mini: drop SendVrMbxCmd from devicetree
Matt DeVillier
2020-11-03
mb/purism/librem_cnl: Adjust in preparation for new variants
Matt DeVillier