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2024-09-01tree: Use boolean for s0ix_enableElyes Haouas
Change-Id: Id0ab5e641684e03da555a127808c0def5a53cbe6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-29tree: Remove unused <string.h>Elyes Haouas
Change-Id: I9ed1a82fcd3fc29124ddc406592bd45dc84d4628 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-05-29tree: Use <stdio.h> for snprintfElyes Haouas
<stdio.h> header is used for input/output operations (such as printf, scanf, fopen, etc.). Although some input/output functions can manipulate strings, they do not need to directly include <string.h> because they are declared independently. Change-Id: Ibe2a4ff6f68843a6d99cfdfe182cf2dd922802aa Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82665 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-30soc/intel/alderlake: Default to 512 for DIMM_SPD_SIZEFelix Singer
Alderlake and Raptorlake SoCs support DDR4 and DDR5, which have a total SPD size of 512 bytes. Set this as the default and remove the setting from mainboard Kconfigs. Change-Id: I8703ec25454a0cd55a3de70f73d2117285a833ae Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82115 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18mb/opencellular to mb/roda: Add SPDX license headers to Kconfig filesMartin Roth
Change-Id: Ia2100d26027a7f71739d5445f781b52c517ed966 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80594 Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-24mb/lenovo to mb/squared: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I4790adb41cb62c8c8dd44261a2926dfb6350955a Reviewed-on: https://review.coreboot.org/c/coreboot/+/80111 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-01-11mb/prodrive/atlas: Update the VBT blob for ADL-P MR5 FSPLean Sheng Tan
Update the VBT version from 249 to 251. It is the same VBT settings as the previous one, but update it based on ADL-P MR5 FSP so it will work with MR5 GOP driver to fix the error "no graphic HOB found". Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I64229da1cb438de826e54dfc97d47d145fb4f0c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79020 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-03mb/prodrive: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: Iface0fd1d44649c6d9773940818e028e3d3a4292 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-05-12mb/prodrive/atlas: Shorten FSP-M UPD statementsAngel Pons
Replace `memupd->FspmConfig.` with `mcfg->` for the sake of brevity. Change-Id: If2e7cccca955b0c1e07c1ecf100d29a923107856 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75136 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
2023-05-12mb/prodrive/atlas: Make default SN/PN not emptyAngel Pons
If reading the serial/part number fails, returning an empty string is very confusing. Instead, return "INVALID" to make problems obvious. Change-Id: I3c174ca76d51b44456c7b68f4fcffb4c8f9379be Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
2023-05-01mb/prodrive/atlas: Enable/disable sleep states based on ECArthur Heymans
With the profile ATLAS_PROF_REALTIME_PERFORMANCE it is desired to not have the option to be able to enter sleep. The reason is that Microsoft Windows goes to sleep after 30min of inactivity by default. TEST: See that Microsoft Windows 11 has no 'Sleep' option in the start menu. Change-Id: I424db7e712a705c628aa3a10a486d3313404987a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74421 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-19soc/intel/alderlake: Rename SOC_INTEL_ALDERLAKE_S3 to D3COLD_SUPPORTSean Rhodes
The Kconfig option SOC_INTEL_ALDERLAKE_S3 suggests that it's doing something with S3, but it's actually disabling D3Cold support. Rename it to D3COLD_SUPPORT to make it clear what it's doing. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ifc3f19912ac7ee55be8ec7a491598140f9532675 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-04-12Revert "soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORT"Michael Niewöhner
This reverts commit 6bfca1b689e48be4f72e8fa401f3558d845fc282. Reason for revert: dependency for revert CB:73903 Change-Id: I56bab4d85d04e90cacfe77db59d0cde6a8a75949 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-03-30mb/prodrive/atlas: Rework EEPROM layout structuresAngel Pons
To avoid having to calculate the length of a struct separately, rework the code to give the struct a tag name, so that `sizeof()` can be used instead. This involves refactoring the `get_emi_eeprom_vpd()` function to return a struct instead of a union, so callers can no longer access the EEPROM data as an array of bytes without additional code, but this array view is only used inside `get_emi_eeprom_vpd()` when reading the data from EMI. Change-Id: Id1bc40939631baa131b5f60eadbfe42838294ebe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-24mb/prodrive/atlas: Configure some FSP settingsAngel Pons
Program some FSP settings as requested by Prodrive. Change-Id: I04548e5eddc8a6be3a03b5dd9062470b4ef85adb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-24mb/prodrive/atlas: Implement initial VPD supportAngel Pons
Atlas stores VPD (Vital Product Data) in an I2C EEPROM, which is only connected to the EC. In order for the host (x86) to be able to access the VPD, the EC reads the EEPROM contents into a buffer in EC RAM and provides the host with read-only access to this EC RAM buffer through EMI (Embedded Memory Interface) 0. The VPD layout is designed to be extensible yet backwards compatible. The code in coreboot uses the revision field to know which fields are valid, and will populate the rest with fallback values. Use the serial number and part number in VPD to populate SMBIOS tables. Change-Id: I2d3d70fee22548daa73ef98af56c98e950dc5e9d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-24mb/prodrive/atlas: Add support to read from EC EMIAngel Pons
Implement initial support for EMI (Embedded Memory Interface), which Microchip describes as "a standard run-time mechanism for the system host to communicate with the Embedded Controller (EC) and other logical components". EMI allows the host to access regions of EC memory without requiring any assistance from the EC. For now, Atlas only uses EMI 0. This change enables EMI 0, subsequent commits will read data from it. Change-Id: Ia899ae71e97f9fc259397dfb5fb84ca06545f5d8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-23mb/prodrive/atlas: Add workaround for CLKREQ pinsMaximilian Brune
Intel Client PCIe* controller expects each device should drive the SRCCLKREQ#. If the GPIO is set to native mode for a device, which does not support SRCCLKREQ#, then during RTD3 exit link would not be established. Because controller samples the SRCCLKREQ# before detecting the device and break L1 as the system might enter L1SS as controller detects SRCCLKREQ# as de-asserted. As a workaround the Pins must not be configured in Native Mode (CLKREQ native function). Therefore here they are not configured at all. source: 689882 (intel document ID) So apparently hardware doesn't sample SRCCLKREQ Pin if it's not configured as such. That workaround suggestion however also brought a patch to FSP, which in turn causes the same bug (even if SRCLKREQ are not configured). Usually in order to make use of root port power saving features (e.g. clock gating), the Root port must either be disabled or a CLKREQ Pin must be configured. The patch however removed that check before enabling power management for the rootport. Workaround (until FSP is fixed): pretend to FSP that the rootports have a CLKREQ Pin attached, by supplying them in the FSP UPDs. That will cause FSP to configure the CLKREQ Pin and enable power management for said rootport, but it will not crash on L1 entry/exit. That has been done on the Atlas board (as workaround) for a short period of time (before applying FSP Fix) like this: // RP 5 (the rootport you want to fix) - memupd->FspmConfig.PcieClkSrcUsage[2] = 4; // e.g. choose a clkreq pin that is not routed out - memupd->FspmConfig.PcieClkSrcClkReq[2] = 0; Furthermore disable CpuPcieRpClockReqMsgEnable FSP-M options to prevent the same issue, but for CPU root ports. If not done the following will happen in coreboot: [DEBUG] PCI: 00:06.2 scanning... [SPEW ] do_pci_scan_bridge for PCI: 00:06.2 [DEBUG] PCI: pci_scan_bus for bus 02 [DEBUG] PCI: 02:00.0 [1344/5410] enabled [INFO ] PCIe: Common Clock Configuration already enabled [INFO ] PCIE CLK PM is not supported by endpoint [INFO ] ASPM: Enabled L1 [EMERG] CPU Index 9 - APIC 32 Unexpected Exception:18 @ 10:76aeb93f - Halting [EMERG] Code: 0 eflags: 00000046 cr2: 00000000 [EMERG] eax: 00000000 ebx: 00000009 ecx: 00000000 edx: 00000000 [EMERG] edi: 00000009 esi: 76b218c4 ebp: 00000000 esp: 76b29100 [EMERG] 0x76aeb8f8: c4 2c 5b 5e 5f 5d c3 56 [EMERG] 0x76aeb900: 53 83 ec 14 65 a1 00 00 This patch is only a workaround for the issue and it will be reverted as soon as FSP is fixed. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I324bc6ab158d4b3b5ae9d3bade21076b44bc8892 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-21mb/prodrive/atlas: Configure PCIe CLKREQMaximilian Brune
Intel Client PCIe* controller expects each device should drive the SRCCLKREQ#. If the GPIO is set to native mode for a device, which does not support SRCCLKREQ#, then during RTD3 exit link would not be established. Because controller samples the SRCCLKREQ# before detecting the device and break L1 as the system might enter L1SS as controller detects SRCCLKREQ# as de-asserted. As a workaround the Pins must not be configured in Native Mode (CLKREQ native function). Therefore here they are not configured at all. source: 689882 (intel document ID) So apparently hardware doesn't sample SRCCLKREQ Pin if it's not configured as such. That workaround suggestion however also brought a patch to FSP, which in turn causes the same bug (even if SRCLKREQ are not configured). Usually in order to make use of root port power saving features (e.g. clock gating), the Root port must either be disabled or a CLKREQ Pin must be configured. The patch however removed that check before enabling power management for the rootport. Workaround (until FSP is fixed): pretend to FSP that the rootports have a CLKREQ Pin attached, by supplying them in the FSP UPDs. That will cause FSP to configure the CLKREQ Pin and enable power management for said rootport, but it will not crash on L1 entry/exit. That has been done on the Atlas board (as workaround) for a short period of time (before applying FSP Fix) like this: // RP 5 (the rootport you want to fix) - memupd->FspmConfig.PcieClkSrcUsage[2] = 4; // e.g. choose a clkreq pin that is not routed out - memupd->FspmConfig.PcieClkSrcClkReq[2] = 0; Furthermore disable CpuPcieRpClockReqMsgEnable FSP-M options to prevent the same issue, but for CPU root ports. If not done the following will happen in coreboot: [DEBUG] PCI: 00:06.2 scanning... [SPEW ] do_pci_scan_bridge for PCI: 00:06.2 [DEBUG] PCI: pci_scan_bus for bus 02 [DEBUG] PCI: 02:00.0 [1344/5410] enabled [INFO ] PCIe: Common Clock Configuration already enabled [INFO ] PCIE CLK PM is not supported by endpoint [INFO ] ASPM: Enabled L1 [EMERG] CPU Index 9 - APIC 32 Unexpected Exception:18 @ 10:76aeb93f - Halting [EMERG] Code: 0 eflags: 00000046 cr2: 00000000 [EMERG] eax: 00000000 ebx: 00000009 ecx: 00000000 edx: 00000000 [EMERG] edi: 00000009 esi: 76b218c4 ebp: 00000000 esp: 76b29100 [EMERG] 0x76aeb8f8: c4 2c 5b 5e 5f 5d c3 56 [EMERG] 0x76aeb900: 53 83 ec 14 65 a1 00 00 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: If2acdc16f37cdae0292f55d210b058f82179bfb4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-02-20soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORTSean Rhodes
Select NO_S0IX_SUPPORT for `starlabs/starbook` and `atlas/prodrive` so their configurations are unchanged. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I718952165daa6471f11e8025e745fe7c249d3b46 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72800 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-07tree: Drop repeated wordsAlexander Goncharov
Found-by: linter Change-Id: I7c6d0887a45fdb4b6de294770a7fdd5545a9479b Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72795 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-01mb/prodrive/atlas/data.vbt: Fix VBT lane countMaximilian Brune
Currently there is a problem, where two Displayports are not working. To be precise: TCP0 and TCP1 (Type-C Port 0/1) are not working. Setting the lane count of the TCP0 and TCP1 to x1 works fine. Setting the lane count of the TCP0 and TCP1 to x2 does not work. Setting the lane count of the TCP0 and TCP1 to x4 does not work. The reason for that is currently unknown. This change sets the lane count of the TCP0 and TCP1 Port to x1 length in the VBT binary. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I182b528275152bf5adcb01a56816afd65674aed3 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72610 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-26src/mb/prodrive/atlas: Add GPIOs for configurationMaximilian Brune
CLKREQ Pins are intentionally not configured, because there seems to be a current Issue with FSP, that causes pci devices to not work if CLKREQ Pins are configured by coreboot. The msi/ms7d25 mainboard seems to have a similar issue and the cause is also documented in it's gpio.c file. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Iba35076af194de0e85de60ebc93d62fda24e9c24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-01-25mb/prodrive/atlas: Enable audio outputLean Sheng Tan
Before, the Intel HDA PCIe device was showing up in the lspci tool, but Audio wasn't working. This patch enables the corresponding FSP-M settings to make it work. Tested on Prodrive Atlas with Themis carrier board on Windows 10 and Linux 6.1.0-rc3. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I144618c453c1e6a3e759afc7532a4ac4a71814c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-25mb/prodrive/atlas: Disable SaGv by defaultLean Sheng Tan
Customer needs SaGv to be disabled by default. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I8454c267dcc12d2ef7de7bd23296a17294f058a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2022-12-02mb/prodrive/atlas: Enable GPP_B14 buzzer supportLean Sheng Tan
Per Intel doc 621483, 26.1.1 - NMI_STS_CNT, 8254 timer is required for Speaker Data output (buzzer) at GPP_B14 NF1, as it is using 8254 timer counter 2 output. However when 8254 timer is used, S0ix will not work as 8254 has to be gated instead. For further info on s0ix requirements, refer to Intel doc 610002 (Modern Standby Unified Checklist). This CL also disables s0ix because it is not required by the platform. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Ib5e7787a47509ed09818d8515d21a80196fb1ec6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67553 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02mb/prodrive/atlas: Add DP++ supportLean Sheng Tan
Update VBT configurations for DP++ and DP dongles support. Tested working on customer's side. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I7aa34297a10bf16b9043140bff91fd3a8c4009d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70154 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17mb/prodrive/atlas: add unique DIMM locators in smbios type17David Milosevic
This patch adds unique device-locators, bank-locators and asset-tags to the smbios type17 tables by making use of a DIMMs controller-ID. This way we avoid name clashes when, for example, two DIMMs share the same channel-ID and DIMM-ID but have a distinct controller-ID. Signed-off-by: David Milosevic <David.Milosevic@9elements.com> Change-Id: I8aef79faa43f2475485f581c675ee152e580f678 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-11-04mb/prodrive/atlas: Add IBECC Kconfig optionMaximilian Brune
Add an option on Atlas to enable IBECC (In Band Error Correction Code), which is currently needed for endurance testing. Test: start atlas mainboard with Linux. See in dmesg that IBECC (EDAC igen6) driver is loaded. Inject a fake error via debugfs and see in dmesg that Linux handles it. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I71ee2401136e2dc70b3164db6c99af03a3e1f346 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-26mb/prodrive/atlas: Disable S3Maximilian Brune
The Atlas board has currently the problem that suspending the System causes the System to freeze. Therefore disable S3, until the cause is figured out and fixed. Change-Id: I5b28787df9b01683fcd4a1de8267840a80bb4fe6 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68591 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-17mb/*/*/gpio.h: Remove unused <soc/gpe.h>Elyes Haouas
Change-Id: I9b03ccc1100307e3c24393903600d18f6cc9abdc Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68378 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
2022-10-14mb/prodrive/atlas: Print HSIDMaximilian Brune
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ibb7aac1204bc297d16797cac5b32b119d0a9204b Reviewed-on: https://review.coreboot.org/c/coreboot/+/68224 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-30mb/prodrive/atlas: Add Kconfig option to enable SaGvLean Sheng Tan
It turns out that one can use Kconfig options to specify values for devicetree options, as long as the resulting expression is a compile time constant. Use this to configure SaGv for Atlas: enable it by default, but allow SaGv to be disabled manually for convenience when testing. Enabling SaGv makes MRC train the RAM multiple times, which takes a significant amount of time. For further info on SAGV on ADL, please refer to Intel Doc 655258 (Alder Lake Datasheet) section 5.1.3.2. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Change-Id: I3c6ac25d414122c408f2348d12dba8dce909e567 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-13mb/prodrive/atlas: Enable legacy S3 supportLean Sheng Tan
Enable S3 support as Prodrive doesn't need s0ix for now. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I7625c8ac860e1afc60c94b3c51e996531a1f2b15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67414 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-09-09mb/prodrive/atlas: Set i225 PCIe RP as built inLean Sheng Tan
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I4436a9d75cb06f2f51979f2bc57d48fa3dbb9e00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67411 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-09mb/prodrive/atlas: Enable resizable BAR supportLean Sheng Tan
Allow up to 4GiB resizable BAR support. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I097483ba8b4479211f67f29a42754d1a51379771 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-09mb/prodrive/atlas: Configure Acoustic noise mitigationLean Sheng Tan
- Enable Acoustic noise mitigation - Set slow slew rate to fast/4 for VCCIA and VCCGT - Disable fast slew rate for deep package C states for VCCIA and VCCGT Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Ia344d9d939c3323bac82afdf25d5fff81081f9c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67380 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2022-09-08mb/prodrive/atlas: Disable POST codes by defaultLean Sheng Tan
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Ib1dd9826cedfd0a3f1ed719cf2e2927f09f783fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/67427 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-08mb/prodrive/atlas: Update VBT data binaryLean Sheng Tan
The previous VBT binary was not properly configured, there were DP display issues on some of the ports and resulted in hangs when FSP debug was used. The updated VBT fixes all the issues. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I788240e36a9a90a5342ee9761f2c61ebf4caa9a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67426 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-29mb/prodrive/atlas: Fix SMBUS/SPD addressesMaximilian Brune
Commit 0e7cf3d81d121181a94b6a594b944628c2e5a939 (soc/intel/alderlake: Fix DDR5 channel mapping) fixed a bug in SoC code that messed up DDR5 SPD address mapping. Atlas uses the 0x50/0x52 addresses. However, the SoC code bug required commit 044883615d4471b7a0b883eb8b8224d95faf52af (mb/prodrive/atlas: Update correct SPD address) so that at least some RAM would work. Now that the SoC code bug is fixed, the workaround is no longer needed, so use the correct SPD address mapping. TEST=Boot Atlas and verify that both memory channels work Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I352d8f36eec63cffd3f63ab6e7421db16ca30163 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-29soc/intel/alderlake: Rename pcie5 aliasBora Guvendik
Rename pcie5 alias as pcie5_0 since raptorlake is adding a new pcie5 RC. BRANCH=firmware-brya-14505.B TEST=none Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Iee669e68e3607b7ffec9f0800e9f0a916defd498 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-16mb/**/dsdt.asl: Drop misleading "OEM revision" commentAngel Pons
It is highly unlikely that the "OEM revision" of the DSDT is 0x20110725 on mainboards with a chipset not yet released on 2011-07-25. Since this comment is most likely to have been copy-pasted from other boards, drop it from boards which use a chipset newer than Sandy/Ivy Bridge. Change-Id: If2f61d09082806b461878a76b286204ae56bf0eb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2022-08-16mb/**/dsdt.asl: Drop superfluous commentsAngel Pons
These comments don't add much value, so remove them. Change-Id: I7e9692e3fe82345cb7ddcb11c32841c69768cd36 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66713 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2022-08-03mb/prodrive/atlas: Select FSP_TYPE_IOTLean Sheng Tan
Atlas uses IoT FSP. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I4c20600e0b62367e6e58908cf9cf916f309e6362 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2022-07-20mb/prodrive/atlas: Swtich from EC UART to LPSS UARTLean Sheng Tan
Switch x86 uart output from EC to LPSS. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I2756d139a72185ba6a5c6d1079d770ce33afdf71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65985 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-05mb/prodrive/atlas: Increase CBFS size to 8MBLean Sheng Tan
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I7c50f770c3a7ab261d6ea41f945e2239ba53fd09 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-05mb/prodrive/atlas: Add data.vbt for 4 DPs supportLean Sheng Tan
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Ia5b6c5c72a1eafe1118e92e4579decb4f4abc9e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-05mb/prodrive/atlas: Update pcie config for i225Lean Sheng Tan
Enable clk 1, LTR & AER for PCIe-to-i225 bridge. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I9593f5d0b70f3d231fd1a8f4758b924645392d63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64902 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-05mb/prodrive/atlas: Fix FSP debug boot hangLean Sheng Tan
When device tcss_xhci is disabled, boot hang occurs at FSP-S TcssInit(): "IomReadyCheck Failed!" Enabling this device fixes the issue. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Ie001bd56b403d511c397737fbc214ed64956910d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64901 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-05mb/prodrive/atlas: Add display configs for 4 DisplayPortsLean Sheng Tan
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Iea5312055305bc3354755607a7bfafa7980c6d21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-04-22mb/prodrive/atlas: Fix build errorEric Lai
commit c6b041a12e refactor the TPM Kconfig. MAINBOARD_HAS_LPC_TPM has changed to MEMORY_MAPPED_TPM. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Iff7e20ac271eb5b2afc9061819e2cc0cf2264cbf Reviewed-on: https://review.coreboot.org/c/coreboot/+/63773 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-20mb/prodrive/atlas: Enable SPI TPM 2.0Lean Sheng Tan
Enable SPI dTPM using eSPI bus. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I18ca41c143ade024ee2840b619ba777b22a2a86a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-20mb/prodrive/atlas: Enable UFS and ISHLean Sheng Tan
The PCI Local Bus Specification Revision 3.0 requires that multi-function devices always implement function 0. Because of this, enabling UFS (PCI device 12.7) requires ISH (PCI device 12.0) to be enabled as well. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Ia8b9561973640edc5f7d0f579dd640e805c0af17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-20mb/prodrive/atlas: Enable PCH PCIe RP7Lean Sheng Tan
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I3f438a7b1dff1a44a81edc8adc983d08708fdd57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-14mb/prodrive/atlas: Update KconfigLean Sheng Tan
Update Kconfig per Atlas usages: 1. Set EC I/O mapped UART as default UART output 2. Add EC IFD region & ACPI support Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I970de724237bcb08899aed7a4b87a23c5cdb0b48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2022-04-11mb/prodrive/atlas: Configure eSPI IO decode ranges for ECLean Sheng Tan
This implementation adds eSPI IO decode range for EC. 1. 0x800-0x8FF / 0x200-020F: EC host command range. 2. 0x900-0x9ff: EC memory map range. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I787561287025e33a8622eb9b3565fa14d0416c46 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-11mb/prodrive/atlas: Disable ASPM for i225 portLean Sheng Tan
I225 doesn’t support ASPM, so disable it at the root port. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I61fe3760c1cde60795c9b52c703e521ba4df504a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-11mb/prodrive/atlas: Update GPIOsLean Sheng Tan
Update Atlas GPIOs for GPD11 & E7. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I92a0d0797206cdba96d7c6efe264b0356b5157ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/63411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-11mb/prodrive/atlas: Update correct SPD addressLean Sheng Tan
Update the SPD address as Atlas is using DIMM 0 & 1 in memory controller 1 channel 1. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Icefcd23b57a7f97e1ee25fed20b35d0e2cb51145 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-15soc/intel/adl/chip.h: Convert all camel case variables to snake caseMAULIK V VAGHELA
coreboot chip.h files mainly contains variable which allows board to fill platform configuration through devicetree. Since many of this configuration involves FSP UPDs, variable names were in camel case which aligned with UPD naming convention. By default coreboot follow snake case variable naming, so cleaning up file to align all variable names as per coreboot convention. During renaming process, this patch also removes unused variables listed below: -> SataEnable // Checked in SoC code based on PCI dev enabled status -> ITbtConnectTopologyTimeoutInMs // SoC always passes 0, so not used Note: Since separating out changes into smaller CL might break the compilation for the patch set, this is being pushed as a single big CL. BUG=None BRANCH=firmware-brya-14505.B TEST=All boards using ADL SoC compiles with the CL. Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-03-15{mb, soc}: Move mrc_cache invalidating logic into `memory` common codeSubrata Banik
Commit hash b8b40964 ( mb, soc: Add the SPD_CACHE_ENABLE) introduced per mainboard logic to invalidate the mrc_cache. This patch moves mrc_cache invalidating logic into IA common code and cleans up the code to remove unused argument `dimms_changed` from SoC and mainboard directory. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=Able to build and boot redrix without any visible failure/errors. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6f18e18adc6572571871dd6da1698186e4e3d671 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-15{mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototypeSubrata Banik
This patch modifies `memcfg_init` and `variant_memory_init`functions argument from FSP_M_CONFIG to FSPM_UPD. This change in `memcfg_init()` argument will help to update the architectural FSP-M UPDs from common code blocks rather than going into SoC and/or mainboard implementation. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=Able to build and boot redrix without any visible failure/errors. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3002dd5c2f3703de41f38512976296f63e54d0c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-02mb, soc: Add the SPD_CACHE_ENABLEZhuohao Lee
In order to cache the spd data which reads from the memory module, we add SPD_CACHE_ENABLE option to enable the cache for the spd data. If this option is enabled, the RW_SPD_CACHE region needs to be added to the flash layout for caching the data. Since the user may remove the memory module after the bios caching the data, we need to add the invalidate flag to invalidate the mrc cache. Otherwise, the bios will use the mrc cache and can make the device malfunction. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=build pass and enable this feature to the brask the device could speed up around 150ms with this feature. Change-Id: If7625a00c865dc268e2a22efd71b34b40c40877b Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62294 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25mb, soc: change mainboard_memory_init_params prototypeZhuohao Lee
The mainboard_memory_init_params takes the struct FSP_M_CONFIG as the input which make the board has no chance to modify data in the FSPM_UPD, for example, set FspmArchUpd.NvsBufferPtr = 0. After changing the FSP_M_CONFIG to FSPM_UPD, the board can modify the value based on its requirement. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=build pass Change-Id: Id552b1f4662f5300f19a3fa2c1f43084ba846706 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-03mb/prodrive/atlas: Configure PCIe device tree settingsLean Sheng Tan
Add CPU & PCH PCIe configs and remove the unused devices. Configures per Atlas schematics v6. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Id3145156c4ab3ec1c2d3eb6c433108a1b1cab9e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-02-03mb/prodrive/atlas: Configure SATA, USB & HSIO device tree settingsLean Sheng Tan
Configure SATA, USB & HSIO settings per Atlas schematics v6. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I88c898d4b0c3bfeefbca71e13dad55e2c5fc846f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-25soc/intel/adl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik
Since Tiger Lake platform, the HECI1 device can be disabled on Alder Lake platform using two different mechanism: A. Using PMC IPC command 0xA9. B. Sending SBI message under SMM. In current scope of Alder Lake the default implementation is using (B) sending sbi message under SMM. A follow up patch to add the possible options and let platform to choose the applicable one. List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. 3. Default enable HECI1 device in `chipset.cb` to ensure the HECI1 device can undergo the PCI enumeration and later based on the mainboard policy the HECI1 device can be disabled. Mainboards that choose to make HECI1 enable during boot don't override `DISABLE_HECI1_AT_PRE_BOOT` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie673e634fbc0bdece419c379d417b08dfb4819e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-21mb/prodrive/atlas: Configure GPIO as per Atlas boardLean Sheng Tan
Update GPIO settings as per schematics v3. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I685d0b7274e3a6e707fec37d051f4818860169ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/61116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-12mb/prodrive/atlas: Add new mainboard based on adlrvpLean Sheng Tan
This is a initial mainboard code cloned from adlrvp aimed to serve as base for further mainboard check-ins. This commit copies the mainboard directory and adjusts the naming to match the new board's name. Besides, This commit also trims down major parts of adlrvp code except some of ADL-P DDR5 RVP as Atlas is using it as main reference. Follow-up commits will introduce the needed changes for the new mainboard. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Ia3129f68c73969604edcd290c3e50ad219cf88d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60899 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-15 14:29:46 +0000