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2022-09-13mb/prodrive/atlas: Enable legacy S3 supportLean Sheng Tan
Enable S3 support as Prodrive doesn't need s0ix for now. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I7625c8ac860e1afc60c94b3c51e996531a1f2b15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67414 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-09-09mb/prodrive/atlas: Set i225 PCIe RP as built inLean Sheng Tan
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I4436a9d75cb06f2f51979f2bc57d48fa3dbb9e00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67411 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-09mb/prodrive/atlas: Enable resizable BAR supportLean Sheng Tan
Allow up to 4GiB resizable BAR support. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I097483ba8b4479211f67f29a42754d1a51379771 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-09mb/prodrive/atlas: Configure Acoustic noise mitigationLean Sheng Tan
- Enable Acoustic noise mitigation - Set slow slew rate to fast/4 for VCCIA and VCCGT - Disable fast slew rate for deep package C states for VCCIA and VCCGT Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Ia344d9d939c3323bac82afdf25d5fff81081f9c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67380 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2022-09-08mb/prodrive/atlas: Disable POST codes by defaultLean Sheng Tan
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Ib1dd9826cedfd0a3f1ed719cf2e2927f09f783fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/67427 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-08mb/prodrive/atlas: Update VBT data binaryLean Sheng Tan
The previous VBT binary was not properly configured, there were DP display issues on some of the ports and resulted in hangs when FSP debug was used. The updated VBT fixes all the issues. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I788240e36a9a90a5342ee9761f2c61ebf4caa9a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67426 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-29mb/prodrive/atlas: Fix SMBUS/SPD addressesMaximilian Brune
Commit 0e7cf3d81d121181a94b6a594b944628c2e5a939 (soc/intel/alderlake: Fix DDR5 channel mapping) fixed a bug in SoC code that messed up DDR5 SPD address mapping. Atlas uses the 0x50/0x52 addresses. However, the SoC code bug required commit 044883615d4471b7a0b883eb8b8224d95faf52af (mb/prodrive/atlas: Update correct SPD address) so that at least some RAM would work. Now that the SoC code bug is fixed, the workaround is no longer needed, so use the correct SPD address mapping. TEST=Boot Atlas and verify that both memory channels work Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I352d8f36eec63cffd3f63ab6e7421db16ca30163 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-29soc/intel/alderlake: Rename pcie5 aliasBora Guvendik
Rename pcie5 alias as pcie5_0 since raptorlake is adding a new pcie5 RC. BRANCH=firmware-brya-14505.B TEST=none Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Iee669e68e3607b7ffec9f0800e9f0a916defd498 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-16mb/**/dsdt.asl: Drop misleading "OEM revision" commentAngel Pons
It is highly unlikely that the "OEM revision" of the DSDT is 0x20110725 on mainboards with a chipset not yet released on 2011-07-25. Since this comment is most likely to have been copy-pasted from other boards, drop it from boards which use a chipset newer than Sandy/Ivy Bridge. Change-Id: If2f61d09082806b461878a76b286204ae56bf0eb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2022-08-16mb/**/dsdt.asl: Drop superfluous commentsAngel Pons
These comments don't add much value, so remove them. Change-Id: I7e9692e3fe82345cb7ddcb11c32841c69768cd36 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66713 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2022-08-03mb/prodrive/atlas: Select FSP_TYPE_IOTLean Sheng Tan
Atlas uses IoT FSP. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I4c20600e0b62367e6e58908cf9cf916f309e6362 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2022-07-20mb/prodrive/atlas: Swtich from EC UART to LPSS UARTLean Sheng Tan
Switch x86 uart output from EC to LPSS. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I2756d139a72185ba6a5c6d1079d770ce33afdf71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65985 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-05mb/prodrive/atlas: Increase CBFS size to 8MBLean Sheng Tan
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I7c50f770c3a7ab261d6ea41f945e2239ba53fd09 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-05mb/prodrive/atlas: Add data.vbt for 4 DPs supportLean Sheng Tan
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Ia5b6c5c72a1eafe1118e92e4579decb4f4abc9e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-05mb/prodrive/atlas: Update pcie config for i225Lean Sheng Tan
Enable clk 1, LTR & AER for PCIe-to-i225 bridge. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I9593f5d0b70f3d231fd1a8f4758b924645392d63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64902 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-05mb/prodrive/atlas: Fix FSP debug boot hangLean Sheng Tan
When device tcss_xhci is disabled, boot hang occurs at FSP-S TcssInit(): "IomReadyCheck Failed!" Enabling this device fixes the issue. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Ie001bd56b403d511c397737fbc214ed64956910d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64901 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-05mb/prodrive/atlas: Add display configs for 4 DisplayPortsLean Sheng Tan
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Iea5312055305bc3354755607a7bfafa7980c6d21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-04-22mb/prodrive/atlas: Fix build errorEric Lai
commit c6b041a12e refactor the TPM Kconfig. MAINBOARD_HAS_LPC_TPM has changed to MEMORY_MAPPED_TPM. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Iff7e20ac271eb5b2afc9061819e2cc0cf2264cbf Reviewed-on: https://review.coreboot.org/c/coreboot/+/63773 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-20mb/prodrive/atlas: Enable SPI TPM 2.0Lean Sheng Tan
Enable SPI dTPM using eSPI bus. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I18ca41c143ade024ee2840b619ba777b22a2a86a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-20mb/prodrive/atlas: Enable UFS and ISHLean Sheng Tan
The PCI Local Bus Specification Revision 3.0 requires that multi-function devices always implement function 0. Because of this, enabling UFS (PCI device 12.7) requires ISH (PCI device 12.0) to be enabled as well. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Ia8b9561973640edc5f7d0f579dd640e805c0af17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-20mb/prodrive/atlas: Enable PCH PCIe RP7Lean Sheng Tan
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I3f438a7b1dff1a44a81edc8adc983d08708fdd57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-14mb/prodrive/atlas: Update KconfigLean Sheng Tan
Update Kconfig per Atlas usages: 1. Set EC I/O mapped UART as default UART output 2. Add EC IFD region & ACPI support Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I970de724237bcb08899aed7a4b87a23c5cdb0b48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2022-04-11mb/prodrive/atlas: Configure eSPI IO decode ranges for ECLean Sheng Tan
This implementation adds eSPI IO decode range for EC. 1. 0x800-0x8FF / 0x200-020F: EC host command range. 2. 0x900-0x9ff: EC memory map range. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I787561287025e33a8622eb9b3565fa14d0416c46 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-11mb/prodrive/atlas: Disable ASPM for i225 portLean Sheng Tan
I225 doesn’t support ASPM, so disable it at the root port. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I61fe3760c1cde60795c9b52c703e521ba4df504a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-11mb/prodrive/atlas: Update GPIOsLean Sheng Tan
Update Atlas GPIOs for GPD11 & E7. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I92a0d0797206cdba96d7c6efe264b0356b5157ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/63411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-11mb/prodrive/atlas: Update correct SPD addressLean Sheng Tan
Update the SPD address as Atlas is using DIMM 0 & 1 in memory controller 1 channel 1. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Icefcd23b57a7f97e1ee25fed20b35d0e2cb51145 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-15soc/intel/adl/chip.h: Convert all camel case variables to snake caseMAULIK V VAGHELA
coreboot chip.h files mainly contains variable which allows board to fill platform configuration through devicetree. Since many of this configuration involves FSP UPDs, variable names were in camel case which aligned with UPD naming convention. By default coreboot follow snake case variable naming, so cleaning up file to align all variable names as per coreboot convention. During renaming process, this patch also removes unused variables listed below: -> SataEnable // Checked in SoC code based on PCI dev enabled status -> ITbtConnectTopologyTimeoutInMs // SoC always passes 0, so not used Note: Since separating out changes into smaller CL might break the compilation for the patch set, this is being pushed as a single big CL. BUG=None BRANCH=firmware-brya-14505.B TEST=All boards using ADL SoC compiles with the CL. Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-03-15{mb, soc}: Move mrc_cache invalidating logic into `memory` common codeSubrata Banik
Commit hash b8b40964 ( mb, soc: Add the SPD_CACHE_ENABLE) introduced per mainboard logic to invalidate the mrc_cache. This patch moves mrc_cache invalidating logic into IA common code and cleans up the code to remove unused argument `dimms_changed` from SoC and mainboard directory. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=Able to build and boot redrix without any visible failure/errors. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6f18e18adc6572571871dd6da1698186e4e3d671 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-15{mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototypeSubrata Banik
This patch modifies `memcfg_init` and `variant_memory_init`functions argument from FSP_M_CONFIG to FSPM_UPD. This change in `memcfg_init()` argument will help to update the architectural FSP-M UPDs from common code blocks rather than going into SoC and/or mainboard implementation. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=Able to build and boot redrix without any visible failure/errors. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3002dd5c2f3703de41f38512976296f63e54d0c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-02mb, soc: Add the SPD_CACHE_ENABLEZhuohao Lee
In order to cache the spd data which reads from the memory module, we add SPD_CACHE_ENABLE option to enable the cache for the spd data. If this option is enabled, the RW_SPD_CACHE region needs to be added to the flash layout for caching the data. Since the user may remove the memory module after the bios caching the data, we need to add the invalidate flag to invalidate the mrc cache. Otherwise, the bios will use the mrc cache and can make the device malfunction. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=build pass and enable this feature to the brask the device could speed up around 150ms with this feature. Change-Id: If7625a00c865dc268e2a22efd71b34b40c40877b Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62294 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25mb, soc: change mainboard_memory_init_params prototypeZhuohao Lee
The mainboard_memory_init_params takes the struct FSP_M_CONFIG as the input which make the board has no chance to modify data in the FSPM_UPD, for example, set FspmArchUpd.NvsBufferPtr = 0. After changing the FSP_M_CONFIG to FSPM_UPD, the board can modify the value based on its requirement. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=build pass Change-Id: Id552b1f4662f5300f19a3fa2c1f43084ba846706 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-03mb/prodrive/atlas: Configure PCIe device tree settingsLean Sheng Tan
Add CPU & PCH PCIe configs and remove the unused devices. Configures per Atlas schematics v6. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Id3145156c4ab3ec1c2d3eb6c433108a1b1cab9e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-02-03mb/prodrive/atlas: Configure SATA, USB & HSIO device tree settingsLean Sheng Tan
Configure SATA, USB & HSIO settings per Atlas schematics v6. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I88c898d4b0c3bfeefbca71e13dad55e2c5fc846f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-25soc/intel/adl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik
Since Tiger Lake platform, the HECI1 device can be disabled on Alder Lake platform using two different mechanism: A. Using PMC IPC command 0xA9. B. Sending SBI message under SMM. In current scope of Alder Lake the default implementation is using (B) sending sbi message under SMM. A follow up patch to add the possible options and let platform to choose the applicable one. List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. 3. Default enable HECI1 device in `chipset.cb` to ensure the HECI1 device can undergo the PCI enumeration and later based on the mainboard policy the HECI1 device can be disabled. Mainboards that choose to make HECI1 enable during boot don't override `DISABLE_HECI1_AT_PRE_BOOT` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie673e634fbc0bdece419c379d417b08dfb4819e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-21mb/prodrive/atlas: Configure GPIO as per Atlas boardLean Sheng Tan
Update GPIO settings as per schematics v3. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I685d0b7274e3a6e707fec37d051f4818860169ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/61116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-12mb/prodrive/atlas: Add new mainboard based on adlrvpLean Sheng Tan
This is a initial mainboard code cloned from adlrvp aimed to serve as base for further mainboard check-ins. This commit copies the mainboard directory and adjusts the naming to match the new board's name. Besides, This commit also trims down major parts of adlrvp code except some of ADL-P DDR5 RVP as Atlas is using it as main reference. Follow-up commits will introduce the needed changes for the new mainboard. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Ia3129f68c73969604edcd290c3e50ad219cf88d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60899 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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