coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2024-05-06	soc/intel/xeon_sp/acpi: Refactor Xeon-SP ASL file location	Shuo Liu
2022-08-16	mb/**/dsdt.asl: Drop misleading "OEM revision" comment	Angel Pons
2021-01-27	ACPI: Add top-level ASL	Kyösti Mälkki
2020-12-10	soc/intel/xeon_sp/nvs: Use common global NVS	Marc Jones
2020-11-07	mainboard/ocp/tiogapass: Add xeon_sp pch.asl	Marc Jones
2020-10-28	mb/ocp/tiogapass/dsdt: Remove unnecessary comments	Maxim Polyakov
2020-10-28	mb/ocp/tiogapass/acpi: Exclude uncore.asl from _SB scope	Maxim Polyakov
2020-10-13	{src/mb,util/autoport}: Use macro for DSDT revision	Elyes HAOUAS
2020-10-03	soc/intel/xeon_sp: Use common ASL code for xeon_sp	Marc Jones
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-06	treewide: replace GPLv2 long form headers with SPDX header	Patrick Georgi
2020-05-06	treewide: Move "is part of the coreboot project" line in its own comment	Patrick Georgi
2020-05-02	acpi: Move ACPI table support out of arch/x86 (3/5)	Furquan Shaikh
2020-03-26	soc/intel/xeon_sp: Refactor code to allow for additional CPUs types	Andrey Petrov
2020-03-18	mainboard/[g-p]*: Remove copyright notices	Patrick Georgi
2020-03-06	mainboard/ocp: Add support for OCP platform TiogaPass	Jonathan Zhang