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2013-12-26AMD boards (non-AGESA): Cleanup post_cache_as_ram.c includesKyösti Mälkki
Change-Id: Ib3a69e3364418426438f88ba14e5cf744e2414fa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4524 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-26AMD boards (non-AGESA): Cleanup earlymtrr.c includesKyösti Mälkki
Change-Id: I5f4bf9dbaf3470dc83d3e980bb6cab10801e15c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4523 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-12-24Remove PCI_ROM_RUN optionVladimir Serbinenko
The main purpose of option rom is to supply int* handlers. But supplying those is outside of coreboot scope and if someone needs those they should run SeaBIOS anyway which runs the option roms wonderfully. Running VGA oprom is kept because they're needed to init graphics. This patch still keeps the options to include the option roms to make them available to SeaBIOS. Change-Id: I646334cf88094d3bf8f527779a68a07e0b4b93ec Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4545 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Kevin O'Connor <kevin@koconnor.net>
2013-12-09AMD boards: Fix includes for microcode updatesKyösti Mälkki
No ROMCC involved, no need to include .c files in romstage.c. Change-Id: I8a2aaf84276f2931d0a0557ba29e359fa06e2fba Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4501 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-10-18get_bus_conf.c: reindent with indentPaul Menzel
Change-Id: Ia0c37339aa69b92a1b518fa5e49adc4a7628ae5d Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3979 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-10-14ck804: obtain I/O APIC base address for ACPI MADT from allocatorJonathan A. Kollasch
Change-Id: I67192c8ae99e396ea4b17e03c658f31dbb5c1800 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/3960 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-10-12Nvidia boards: acpi_tables.c: Remove intermediate variable in ACPI interrupt ↵Jonathan A. Kollasch
routing initialization Change-Id: I6cb4ad5ea5ad40284f8e88ff440f2605d3b83359 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/3959 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2013-08-15Include boot_cpu.c for romstage buildsKyösti Mälkki
ROMCC boards were left unmodified. Change-Id: I3d842196b3f5b6999b6891b914036e9ffcc3cef0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3853 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-06-24AMD: Drop empty root_complexKyösti Mälkki
There are no files to build left under AMD nortbridge/x/root_complex directories. For some cases, even the Kconfig file was no longer sourced. Remove all such references and empty files. For devicetree.cb treat component paths with "/root_complex" in them valid even when the directory does not exists. This is because AMD boards us this dummy chip component as the root node in their devicetree.cb. The generated devicetree file static.c remains unchanged. Change-Id: I9278ebb50a83cebbf149b06afb5669899a8e4d0b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3434 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-05-10Get rid of MAXIMUM_CONSOLE_LOGLEVEL; compile all messages into the coreboot ↵Ronald G. Minnich
binary This option has never had much if any use. It solved a problem over 10 years ago that resulted from an argument over the value or lack thereof of including all the debug strings in a coreboot image. The answer is in: it's a good idea to maintain the capability to print all messages, for many reasons. This option is also misleading people, as in a recent discussion, to believe that log messges are controlled at build time in a way they are not. For the record, from this day forward, we can print messages at all log levels and the default log level is set at boot time, as directed by DEFAULT_CONSOLE_LOGLEVEL. You can set the default to 0 at build time and if you are having trouble override it in CMOS and get more messages. Besides, a quick glance shows it's always set to max (9 in this case) in the very few cases (1) in which it is set. Change-Id: I60c4cdaf4dcd318b841a6d6c70546417c5626f21 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3188 Tested-by: build bot (Jenkins)
2013-05-09AMD: Reduce stack size from 64 KB to the default of 4 KBPaul Menzel
Apply the following commit to all AMD boards. commit 935850e08293cec1cb27d12358b27285e780566a Author: Stefan Reinauer <reinauer@chromium.org> Date: Mon May 6 16:16:03 2013 -0700 asrock/e350m1: reduce default stack size The stack used on the ASRock E350M1 is significantly less than what we currently set (64k per core). In fact, we use about half of the default stack size (4k) on core 0 and even less on non BSP cores [1]: $ grep stack coreboot_without_patch_but_monotonic_timer.log CPU1: stack_base 002a0000, stack_end 002afff8 CPU1: stack: 002a0000 - 002b0000, lowest used address 002afda8, stack used: 600 bytes CPU0: stack: 002b0000 - 002c0000, lowest used address 002bf75c, stack used: 2212 bytes […] Reviewed-on: http://review.coreboot.org/3209 Please note that AGESA seems to define bigger stack sizes. But these seem to be too much too. $ git grep STACK_SIZE src/vendorcode/amd […] src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c:#define BSP_STACK_SIZE 16384 src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c:#define CORE0_STACK_SIZE 16384 src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c:#define CORE1_STACK_SIZE 4096 src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c: BSP_STACK_SIZE, src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c: CORE0_STACK_SIZE, src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c: CORE1_STACK_SIZE, […] The following command was used to create the patch. $ git grep -l STACK_SIZE src/mainboard/ | xargs sed -i '/STACK_SIZE/,+3d' Change-Id: I36b95b7a6f190b64d0639fc036ce2fb0253f3fa1 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3217 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-08Drop CONFIG_AP_CODE_IN_CARStefan Reinauer
This option has not been enabled on any board and was considered obsolete last time it was touched. If we need the functionality, let's fix this in a generic way instead of a K8 specific way. This was mostly a speedup hack back in the day. Change-Id: Ib1ca248c56a7f6e9d0c986c35d131d5f444de0d8 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3211 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-03-22x86: Unify arch/io.h and arch/romcc_io.hStefan Reinauer
Here's the great news: From now on you don't have to worry about hitting the right io.h include anymore. Just forget about romcc_io.h and use io.h instead. This cleanup has a number of advantages, like you don't have to guard device/ includes for SMM and pre RAM anymore. This allows to get rid of a number of ifdefs and will generally make the code more readable and understandable. Potentially in the future some of the code in the io.h __PRE_RAM__ path should move to device.h or other device/ includes instead, but that's another incremental change. Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2872 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
In the file `COPYING` in the coreboot repository and upstream [1] just one space is used. The following command was used to convert all files. $ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/' [1] http://www.gnu.org/licenses/gpl-2.0.txt Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2490 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-14sconfig: rename lapic_cluster -> cpu_clusterStefan Reinauer
The name lapic_cluster is a bit misleading, since the construct is not local APIC specific by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-x86 systems without adding new keywords. Change-Id: Icd7f5fcf6f54d242eabb5e14ee151eec8d6cceb1 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2377 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14sconfig: rename pci_domain -> domainStefan Reinauer
The name pci_domain was a bit misleading, since the construct is only PCI specific in a particular (northbridge/cpu) implementation, but not by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-PCI systems without adding new keywords. Change-Id: Ide885a1d5e15d37560c79b936a39252150560e85 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2376 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-29Drop empty mainboard.cKyösti Mälkki
Change-Id: Idcf9349d96297b8cb0ea1e68769e02659ac16ab8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1933 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-29Drop empty mainboard_opsKyösti Mälkki
Change-Id: I24866142eebcb8fdbc7e21f5b2f364a8d1b264b3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1932 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-28amdk8/amdfam10: Use CAR_GLOBAL for sysinfoPatrick Georgi
This gets rid of the somewhat unstructured placement of AMD's sysinfo structure in CAR. We used to carve out some CAR space using a Kconfig variable, and then put sysinfo there manually (by "virtue" of pointer magic). Now it's a variable with the CAR_GLOBAL qualifier, and build system magic. For this, the following steps were done (but must happen together since the intermediates won't build): - Add new CAR_GLOBAL sysinfo_car - point all sysinfo pointers to sysinfo_car instead of GLOBAL_VAR - remove DCACHE_RAM_GLOBAL_VAR_SIZE - from CAR setup (no need to reserve the space) - commented out code (that was commented out for years) - only copy sizeof(sysinfo) into RAM after ram init, where before it copied the whole GLOBAL_VAR area. - from Kconfig Change-Id: I3cbcccd883ca6751326c8e32afde2eb0c91229ed Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1887 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-27Remove AMD special case for LAPIC based udelay()Patrick Georgi
- Optionally override FSB clock detection in generic LAPIC code with constant value. - Override on AMD Model fxx, 10xxx, agesa CPUs with 200MHz - compile LAPIC code for romstage, too - Remove #include ".../apic_timer.c" in AMD based mainboards - Remove custom udelay implementation from intel northbridges' romstages Future work: - remove the compile time special case (requires some cpuid based switching) - drop northbridge udelay implementations (i945, i5000) if not required anymore (eg. can SMM use the LAPIC timer?) Change-Id: I25bacaa2163f5e96ab7f3eaf1994ab6899eff054 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1618 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-16Fix PIRQ routing abstractionStefan Reinauer
intel_irq_routing_table is a local structure that should not be used globally, because it might not be there on all mainboards. Instead, the API has to be corrected to allow passing a PIRQ table in where needed. Change-Id: Icf08928b67727a366639b648bf6aac8e1a87e765 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1862 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-16Fix Kconfig GENERATE_*_TABLE usageStefan Reinauer
Some boards selected GENERATE_ instead of HAVE_ Change-Id: I450c22d7b044f0c88c21692246d452d516a68a83 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1841 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-16Drop CONFIG_HAVE_BUS_CONFIG, clean up KconfigStefan Reinauer
This patch is the beginning of a Kconfig cleanup series - drop CONFIG_HAVE_BUS_CONFIG and add get_bus_conf.c if it exists in the mainboard directory - drop duplicate ACPI_SSDTX_NUM from mainboard Kconfig if it only defines the defaul value of 0 - Add mptable.c, fadt.c, reset.c and ssdtX.asl when they exist, not based on some Kconfig magic Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Ia14a7116dad6a724af7e531920fee9a51fd0b200 Reviewed-on: http://review.coreboot.org/1832 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-14ms9652: fix misuse of LIFT_BSP_APIC_IDStefan Reinauer
It's a bool, not a number Change-Id: I70d52c6af6703101dbd534970ec65275902a283d Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1842 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-06Drop redundant CHIP_NAME in mainboard.cKyösti Mälkki
Compose the name from Kconfig strings instead. As the field is for debug print use only, a minor change in the output should do no harm. The strings no longer include word "Mainboard". Change-Id: Ifd24f408271eb5a5d1a08a317512ef00cb537ee2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1635 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-10-08hpet: common ACPI generationPatrick Georgi
HPET's min ticks (minimum time between events to avoid losing interrupts) is chipset specific, so move it to Kconfig. Via also has a special base address, so move it as well. Apart from these (and the base address was already #defined), the table is very uniform. Change-Id: I848a2e2b0b16021c7ee5ba99097fa6a5886c3286 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1562 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2012-08-08Cleanup coreboot memory table includesKyösti Mälkki
The includes removed here were previously required for struct lb_memory and lb_add_memory_range(). Change-Id: Ie6c0d4ef55c2225aa709cf3fbad30ff1080e3610 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1391 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2012-08-08Drop HAVE_MAINBOARD_RESOURCESKyösti Mälkki
These existed to provide a hook to add reserved memory regions in the coreboot memory table. Reserved memory are now added as resources. Change-Id: I9f83df33845cfa6973b018a51cf9444dbf0f8667 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1414 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-08-07Move cpus_ready_for_init() to AMD K8Kyösti Mälkki
The function is a noop for all but amd/serengeti_cheetah. Change-Id: I09e2e710aa964c2f31e35fcea4f14856cc1e1dca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1184 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-01Intel and GFXUMA: drop redundant use of lb_add_memory_range()Kyösti Mälkki
Use of uma_resource() in northbridge code created a memory resource marked as reserved. Such resources are removed from system memory in write_coreboot_table(). Change-Id: I14bfd560140d8d30ec156562f23072bfae747bde Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1238 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-07-31Revert "remove CONFIG_SERIAL_CPU_INIT"Sven Schnelle
This reverts commit 78efc4c36c68b51b3e73acdb721a12ec23ed0369. The broadcast patch was reverted, so this commit should also be reverted. The reason for reverting the broadcast patch: It turned out that sending IPIs via broadcast doesn't work on Sandybridge. We tried to come up with a solution, but didn't found any so far. So revert the code for now until we have a working solution. Change-Id: I05c27dec55fa681f455215be56dcbc5f22808193 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1380 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-26Drop mainboard chip.hStefan Reinauer
mainboard_config never worked right, at least not since we've had sconfig. Hence, drop mainboard/<vendor>/<device>/chip.h and fix up the mainboards that tried to use it anyways. Change-Id: I7cd403ea188d8a9fd4c1ad15479fa88e02ab8e83 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1359 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-12Drop Kconfig VAR_MTRR_HOLE optionKyösti Mälkki
All but one board use the default value of enabled. Disabling this can only increase the number of MTRR registers used. Change-Id: I7d28adc31b9fae2301e4ff78fcb96486f81d5ec2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1213 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-02remove CONFIG_SERIAL_CPU_INITSven Schnelle
The new broadcast code doesn't support serial init - if a CPU needs serial init, this should be handled in the model specific CPU init code. Change-Id: I7cafb0af10d712366819ad0849f9b93558e9d46a Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1140 Tested-by: build bot (Jenkins)
2012-05-08Clean up #ifsPatrick Georgi
Replace #if CONFIG_FOO==1 with #if CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} + Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} + Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} + Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} + (and some manual changes to fix false positives) Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1004 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Martin Roth <martin@se-eng.com>
2012-04-27Move top level pc80 directory to drivers/Stefan Reinauer
There is no reason for this to be a top level directory. Some stuff from lib/ should also be moved to drivers/ Change-Id: I3c2d2e127f7215eadead029cfc7442c22b26814a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/939 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-20Refactor some alignment handlingPatrick Georgi
Made using coccinelle: @@ expression E; @@ -(E + 7) & -8 +ALIGN(E, 8) @@ expression E; @@ -(E + 15) & -16 +ALIGN(E, 16) Change-Id: I071d2c98cd95580d7de21d256c31b6368a3dc70b Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/910 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-08Unify Local APIC address definitionsPatrick Georgi
We used several names for that same value, and hardcoded the value at some more places. They're all LOCAL_APIC_ADDR now (except for lapic specific code that still uses LAPIC_DEFAULT_BASE). Change-Id: I1d4be73b1984f22b7e84681edfadf0588a7589b6 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/676 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-22ACPI: More ../../.. removalPatrick Georgi
CPP is ran with src/ as part of its search path, so using <northbridge/...> and the like is safe. Change-Id: I644d60190ac92ef284d5f0b4acf44f7db3c788ee Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/649 Tested-by: build bot (Jenkins)
2012-02-22Remove old AMD fam10 fixme commentMarc Jones
The family10 code had a very slow decompress before the cache settings were fixed. This has been fixed for some time. Remove all the old messages from the serial stream. Change-Id: I476efe1a430f702af394734f354ff69bd053f1d2 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/672 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-02-17nvidia/mcp55: Move HAVE_HARD_RESET to southbridgePatrick Georgi
No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: Ibfb7b294aa5007ac2f767d85e090572f85148bad Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/659 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-02-17broadcom/bcm5785: Move HAVE_HARD_RESET to southbridgePatrick Georgi
No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: Id95660f088c8240606d45abf326cd5eefca30da3 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/658 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-02-17nvidia/ck804: Move HAVE_HARD_RESET to southbridgePatrick Georgi
No in-tree ck804-using board has it not selected, so move selection from boards to southbridge. Change-Id: I3064b406cfd5ad18067c597bd5b5866a720f7e87 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/657 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-17Remove whitespace.Patrick Georgi
Fix issues reported by new lint test. Change-Id: I077a829cb4a855cbb3b71b6eb5c66b2068be6def Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/646 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-09Remove no-op Makefiles under mainboard directoryKyösti Mälkki
Patch removes following files: src/mainboard/amd/serengeti_cheetah/Makefile.inc src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc src/mainboard/broadcom/blast/Makefile.inc src/mainboard/hp/dl145_g1/Makefile.inc src/mainboard/msi/ms9282/Makefile.inc src/mainboard/supermicro/h8dme/Makefile.inc src/mainboard/tyan/s2881/Makefile.inc src/mainboard/tyan/s2892/Makefile.inc src/mainboard/via/epia-m700/Makefile.inc Change-Id: I020776313abff1772be38afc896af51ca5ab6453 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/612 Tested-by: build bot (Jenkins) Reviewed-by: Kerry Sheh <shekairui@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-07Delete hard-coded driver includesKyösti Mälkki
Driver components are conditionally included in the build using the Kconfig options. Change-Id: I05417ee263a5b82e947600482dfb68f7a3f52d58 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/610 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-01-18Unify ID_SECTION_OFFSET and mark it deprecatedPatrick Georgi
We used to put the id section at -0x10, with some boards overriding this to avoid collisions with romstraps. Hardcode the location at -0x80, at the possible expense of some space (0x70 bytes). This also makes the section easier to find in a binary image. At some point, CONFIG_ID_SECTION_OFFSET can be removed, so this option is moved to src/Kconfig.deprecated_options. Change-Id: I6ce2d6e94e57717939bda070bfe0c9df80ca2a89 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/549 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-11-01remove trailing whitespaceStefan Reinauer
Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/364 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-30remove usbdebug.h include from mainboard/romstage codeSven Schnelle
No romstage is supposed to use usbdebug functions/defines directly, so remove all those includes. The usb code is now called and setup from console code. Change-Id: I9b1120d96f5993303d6b302accc86e14a91f7a9f Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/354 Tested-by: build bot (Jenkins)
2011-10-28Get rid of the old romstage-as-bootblock ROM layoutPatrick Georgi
This change removes CONFIG_TINY_BOOTBLOCK, CONFIG_BIG_BOOTBLOCK, and all their uses, assuming TINY_BOOTBLOCK=y, BIG_BOOTBLOCK=n. This might break a couple of boards on runtime, but so far, fixes were quite simple. There's a flag day: Code that relies on CONFIG_TINY_BOOTBLOCK must be adapted. Change-Id: I1e17a4a1b9c9adb8b43ca4db8aed5a6d44d645f5 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/320 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-13Use default table creator macro for all SSDTsStefan Reinauer
Change-Id: I0c138ebfdc6d4d5ae7d3512b0dd68df20485690e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/262 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13mptable: Refactor mptable generation some morePatrick Georgi
The last couple of lines of every mptable function were mostly identical. Refactor into common code, a new function mptable_finalize. Coccinelle script: @@ identifier mc; @@ ( -mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); -mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); -printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); -return smp_next_mpe_entry(mc); +return mptable_finalize(mc); | -mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); -mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); -return smp_next_mpe_entry(mc); +return mptable_finalize(mc); ) Change-Id: Ib2270d800bdd486c5eb49b328544d36bd2298c9e Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/246 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13mptable: Get rid of fixup_virtual_wirePatrick Georgi
As stated in some code files, fixup_virtual_wire was established to avoid touching 200 invocations of the mptable code. Let Coccinelle do it: @@ type T; identifier v; @@ -void fixup_virtual_wire(T v) -{ ... } @@ expression A; identifier v; @@ -v = smp_write_floating_table(A); +v = smp_write_floating_table(A, 0); @@ expression A; identifier v; @@ -v = smp_write_floating_table(A, 0); -fixup_virtual_wire(v); +v = smp_write_floating_table(A, 1); Change-Id: Icad8a063380bf4726be7cebb414d13b574112b14 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/245 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13mptable: Refactor lintsrc generationPatrick Georgi
We copied pretty much the same code for generating mptable entries for local interrupts (with some notable exceptions). This change moves these lines into a generic function "mptable_lintsrc" and makes use of it in many places. The remaining uses of smp_write_lintsrc should be reviewed and replaced by mptable_lintsrc calls where possible, and smp_write_lintsrc made static. This patch was generated using Coccinelle: @@ expression mc; expression isa_bus; @@ -smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); -smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); +mptable_lintsrc(mc, isa_bus); @@ expression mc; expression isa_bus; @@ -smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x0); -smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x1); +mptable_lintsrc(mc, isa_bus); @m@ identifier mc; expression BUS; @@ -#define IO_LOCAL_INT(type, intr, apicid, pin) smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, BUS, (intr), (apicid), (pin)); ... -IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); -IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); +mptable_lintsrc(mc, BUS); Change-Id: I97421f820cd039f5fd753cb0da5c1cca68819bb4 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/244 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-21Use ACPI text fields consistently with all other boardsStefan Reinauer
LXBIOS and LXB-DSDT are not used in other parts of the tree. Make names consistent across the tree. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: I91caeac09fd2401a36e53bd061d249b236a48e43 Reviewed-on: http://review.coreboot.org/224 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-08-06ms7135: add ACPI supportJonathan A. Kollasch
Change-Id: I64a74d3dc0ea2d006ed4b25657d531fb243c2993 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/140 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-04Add voltage control of southbridge and RAM on ms7135Jonathan A. Kollasch
Change-Id: I5d79b4838f69cad56d58363608b801f8b1d3ab43 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/126 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-08-03Remove debugging code, or convert it to be selected by kconfigJonathan A. Kollasch
Change-Id: Ib6cd82badeb6401e065ee14c2a04c78f61a87dd4 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/130 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-03Use preferred style of fixed-width integer typesJonathan A. Kollasch
Change-Id: I1abaaa2af4de940584039f9b8c348bb57fb611e0 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/125 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Peter Stuge <peter@stuge.se>
2011-04-20run uart_init() from console_init, just like the other console ↵Stefan Reinauer
initialization functions. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-18* Set USBDEBUG_DEFAULT_PORT in all southbridges and use that valueStefan Reinauer
to unify calls to *_enable_usbdebug() * rename *_enable_usbdebug() to enable_usbdebug() * move enable_usbdebug() to generic romstage console init code and drop it from the individual romstage.c files. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6513 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-10In 2007 Adrian Reber suggested that we drop ASSEMBLY in favor of __ASSEMBLER__.Stefan Reinauer
http://www.coreboot.org/pipermail/coreboot/2007-September/024665.html It's about time we follow this advice. Also move some manually set __PRE_RAM__ defines (ap_romstage.c) to the Makefile and drop unused CPP define Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6482 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-08Enable mahogany_fam10 and Kino family 10h to run the SB HT link at the ↵Scott Duplichan
expected HT3 frequency and width by matching the BUID swap list to the production BIOS. In addition, the BUID swap list has been moved into the project-specific file romstage.c for the other 13 AMD family 10h projects as well. For projects using a desktop AMD family 10h processor, pasting in the mahogany_fam10 swap list will likely allow HT3 operation. This should be confirmed on real hardware before commiting any swap list change. A different swap list will be needed for server projects. For serengeti_cheetah_fam10, a reference BIOS swap list to try is: 0x00, 0x0A, 0x00, 0x06, 0xFF, 0x0A, 0x06, 0xFF. The patch makes these changes: 1) Remove the BUID swap list from ht_wrapper.c and put it in each of 15 romstage.c files where it is used (AMD family 10h projects). 2) Add a prototype to amdfam10.h. 3) Modify the swap list and test in real hardware for mahogany_fam10 and kino family 10h and confirm HT3 operation for the SB link. Abuild tested. Signed-off-by: Scott Duplichan <sc...@notabs.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6439 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-03Configure PCIe lanes on ms7135 as original BIOS does.jakllsch
Signed-off-by: <jakllsch@kollasch.net> Acked-by: <jakllsch@kollasch.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6428 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-01Use subsystem id from devicetree.cb instead of Kconfig and moveSven Schnelle
all boards to the new config scheme. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6421 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-26Make AMD Fam10h CPU microcode updates optional in Expert modeXavi Drudis Ferran
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6385 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-19The same mechanisms are used for normal and fallback images. Stefan Reinauer
Hence drop the FALLBACK_ prefix Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6204 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-17Remove some more unused/incorrect hda_verb.h files.Uwe Hermann
As discussed on the mailing list at http://www.coreboot.org/pipermail/coreboot/2010-December/062393.html http://www.coreboot.org/pipermail/coreboot/2010-December/062510.html Someone who owns these boards should create correct files at some point. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6196 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-17drop one more version of doing serial uart output differently.Stefan Reinauer
coreboot made it kind of complicated to print a character on serial. Not quite as complicated as UEFI, but too much for a good design. Fix it. Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6191 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-16Get mptable OEM/product ID from kconfig variables.Uwe Hermann
We currently use "COREBOOT" unconditionally as the "OEM ID" in our mptable.c files, and hardcode the mainboard name in mptable.c like this: mptable_init(mc, "DK8-HTX ", LAPIC_ADDR); However, the spec says "OEM ID: A string that identifies the manufacturer of the system hardware." (Table 4-2, page 42) so "COREBOOT" doesn't match the spec, we should use the hardware vendor name. Thus, use CONFIG_MAINBOARD_VENDOR which we have already as the "OEM ID" (truncate/fill it to 8 characters as per spec). Also, use CONFIG_MAINBOARD_PART_NUMBER (the board name) as "product ID", and truncate/fill it to 12 characters as per spec, if needed. Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6183 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-15Build fix.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6181 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-15Cleanup up HD audio codec / hda_verb.h files.Uwe Hermann
Most of the current hda_verb.h files are identical (same MD5 sum) and are intended for a specific MCP55 board with the Realtek ALC880 audio codec, which has the vendor/device ID of 0x10ec0880. They were splitted out from the MCP55 southbridge code and put into board dirs a long time ago (which is correct, as those settings are indeed board-specific), but they were never adapted to those boards. Here's the table of which codec is soldered onto which board, based on checking the vendor website board spec pages, and the board manuals: - GIGABYTE GA-M57SLI-S4: Realtek ALC883 - MSI MS-7260: Realtek ALC883 - MSI MS-9652: Realtek ALC888 - MSI MS-9282: Server board, doesn't have audio at all - Tyan S2912: Server board, doesn't have audio at all - All Supermicro boards: Server boards, don't have audio at all - NVIDIA l1_2pvv: No public info to be found, but I assume this was the original MCP55 eval board for the port and it's probably has the Realtek ALC880 codec used in the original hda_verb.h. These are the codec vendor device/IDs involved: Realtek ALC880: 0x10ec0880 Realtek ALC883: 0x10ec0883 Realtek ALC888: 0x10ec0888 The following files are marked as incorrect / TODO, as the ID of the codec doesn't match and thus will never get actually used (you'll see "HDA: no verb!" or similar in the coreboot logs). Even if the ID matched, the rest of the table would be incorrect anyway because the values are highly board-specific. ./src/mainboard/gigabyte/m57sli/hda_verb.h ./src/mainboard/msi/ms9652_fam10/hda_verb.h ./src/mainboard/msi/ms9282/hda_verb.h The following files can be safely dropped as these are server boards and don't have HD audio (or other audio) at all: ./src/mainboard/supermicro/h8dmr/hda_verb.h ./src/mainboard/supermicro/h8qme_fam10/hda_verb.h ./src/mainboard/supermicro/h8dme/hda_verb.h ./src/mainboard/supermicro/h8dmr_fam10/hda_verb.h ./src/mainboard/tyan/s2912/hda_verb.h ./src/mainboard/tyan/s2912_fam10/hda_verb.h The following two are correct and can stay: ./src/mainboard/nvidia/l1_2pvv/hda_verb.h ./src/mainboard/getac/p470/hda_verb.h Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6180 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-13no leading zeroes.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6177 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-08Move "select CACHE_AS_RAM" lines from boards into CPU socket.Uwe Hermann
All K8/Fam10h boards use CAR, so move the "select CACHE_AS_RAM" into the socket directories, and remove it from the individual boards. Do the same for Intel CPUs/sockets where all boards use CAR. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6151 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-08second round name simplification. drop the <component>_ prefix.stepan
the prefix was introduced in the early v2 tree many years ago because our old build system "newconfig" could not handle two files with the same name in different paths like /path/to/usb.c and /another/path/to/usb.c correctly. Only one of the files would end up being compiled into the final image. Since Kconfig (actually since shortly before we switched to Kconfig) we don't suffer from that problem anymore. So we could drop the sb700_ prefix from all those filenames (or, the <componentname>_ prefix in general) - makes it easier to fork off a new chipset - makes it easier to diff against other chipsets - storing redundant information in filenames seems wrong Signed-off-by: <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6150 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-08first round name simplification. drop the <component>_ prefix.stepan
the prefix was introduced in the early v2 tree many years ago because our old build system "newconfig" could not handle two files with the same name in different paths like /path/to/usb.c and /another/path/to/usb.c correctly. Only one of the files would end up being compiled into the final image. Since Kconfig (actually since shortly before we switched to Kconfig) we don't suffer from that problem anymore. So we could drop the sb700_ prefix from all those filenames (or, the <componentname>_ prefix in general) - makes it easier to fork off a new chipset - makes it easier to diff against other chipsets - storing redundant information in filenames seems wrong Signed-off-by: <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-07Get rid of some unneeded function prototypes in romstage.c files.Uwe Hermann
Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6147 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-06Winbond W83627HF: Use existing functions instead of open-coding.Uwe Hermann
Use w83627hf_set_clksel_48() where needed instead or open-coding the same functionality, and also use w83627hf_enable_serial() instead of w83627hf_enable_dev() (which does exactly the same, but isn't wrapped in the enter/exit config mode functions). Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6143 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-05W83627DHG/W83627EHG fixups for virtual LDNs.Uwe Hermann
W83627DHG: - Add proper "virtual LDN" handling for the LDNs that need it (i.e., those that don't have their "enable" bit in bit 0 of the 0x30 register). - Fix various I/O masks in the pnp_dev_info[] array as per datasheet. Add missing PNP_IRQ0 to the W83627DHG_ACPI LDN. W83627EHG: - Similar to W83627DHG, improve the "virtual LDN" setup a bit (it was mostly implemented already, though). - Add missing PNP_IRQ0 to the W83627EHG_ACPI LDN. Also: Fix up devicetree.cb of all boards using W83627DHG/W83627EHG to adapt for the virtual LDNs. include/device/pnp.h: Add comment that 'function' (which refers to the LDN and should probably be renamed later) has to be at least 16 bits wide. In theory LDNs could use u8, but due to the virtual LDN info being encoded in the "high byte" of 'function' it must be at least u16. asrock/939a785gmh/romstage.c: Drop unused GPIO6_DEV. ibase/mb899/romstage.c: Use DUMMY_DEV instead of a specific LDN (serial port 1 in this case) to avoid confusion. The global registers manipulated there are accessible from any LDN. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6140 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-28devicetree.cb: Only add as many entries as there are DIMM slots.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6129 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-26Broadcom BCM5785: Add TINY_BOOTBLOCK support.Uwe Hermann
In bcm5785_enable_rom(): Use PCI IDs from pci_ids.h instead of hardcoding, and use 'dev' instead of 'addr' as device_t variable name. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6126 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-25MCP55: Add TINY_BOOTBLOCK support.Uwe Hermann
Also, move CONFIG_HT_CHAIN_END_UNITID_BASE #ifdef block to mcp55.h to make the build work (but this is a good idea anyway, as it's used in multiple files). Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6123 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-22Printing coreboot debug messages on VGA console is pretty much useless, sinceStefan Reinauer
initializing VGA happens pretty much as the last thing before starting the payload. Hence, drop VGA console support, as we did in coreboot v3. - Drop VGA and BTEXT console support. Console is meant to be debugging only, and by the time graphics comes up 99% of the risky stuff has already happened. Note: This patch does not remove hardware init but only the actual output functionality. The ragexl driver needs some extra love, but that's for another day - factor out die() and post() - drop some leftover RAMBASE < 0x100000 checks. Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: QingPei Wang<wangqingpei@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6111 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-21Simplify a few code chunks, fix whitespace and indentation.Uwe Hermann
Also, remove some less useful comments, some dead code / unused functions. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6108 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-21Drop excessive whitespace randomly sprinkled in romstage.c files.Uwe Hermann
Also drop some dead or useless code snippets. Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6107 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-21Convert more boards to use mptable_write_buses.Patrick Georgi
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6106 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-21Move MCP55_PCI_E_X_* to Kconfig. Any useless values in romstage.cs werePatrick Georgi
not brought over to Kconfig (this applies to all #defines to 4, as that's the default anyway) Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6104 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-21Use DIMM0 et al in lots more places instead of hardocding values.Uwe Hermann
The (0xa << 3) expression equals 0x50, i.e. DIMM0. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6103 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-20Merge all spd_addr.h into the resp. romstage.c files.Uwe Hermann
Except for one instance the spd_addr.h were now very tiny, there's not much point in keeping that stuff in an extra file. The only user of those files is the romstage.c file anyway. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6101 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-20Some more DIMM0 related cleanups and deduplication.Uwe Hermann
- VIA VT8235: Do the shift in smbus_read_byte() as all other chipsets do. - spd.h: Move RC00-RC63 #defines here, they were duplicated in lots of romstage.c files and lots of spd_addr.h files. Don't even bother for those spd_addr.h which aren't even actually used, drop them right away. - Replace various 0x50 hardcoded numbers with DIMM0, 0x51 with DIMM1, and 0xa0 with (DIMM0 << 1) where appropriate. - Various debug.c files: Replace SMBUS_MEM_DEVICE_START with DIMM0, SMBUS_MEM_DEVICE_END with DIMM7, and drop useless SMBUS_MEM_DEVICE_INC. - VIA VX800: Drop unused SMBUS_ADDR_CH* #defines. - VIA VT8623: Do the shift in smbus_read_byte() as all other chipsets do. Then, replace 0xa0 (which now becomes 0x50) with DIMM0. - alix1c/romstage.c, alix2d/romstage.c: Adapt to recent bit shift changes. - Various files: Drop DIMM_SPD_BASE and/or replace it with DIMM0. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-20Unify DIMM SPD addressing. For Geode, change thePatrick Georgi
addressing scheme to match the rest of the tree (0x50 instead of 0xa0). abuild tested. Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-18Drop unused and incorrect RTC_DEV for Winbond W83627EHG.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6094 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-18Eliminate SET_NB_CFG_54 option. There was no board thatPatrick Georgi
deselected it, and very likely there won't ever be any hardware that requires it deselected. Keep the "selected" code path around, leading to no functional change. Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Scott Duplichan <scott@notabs.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6086 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-16Drop W83627THF, it's the same device as W83627THG.Uwe Hermann
The only difference is that the "G" version is in a Pb-free package, which is not relevant from a programmer's view. We keep W83627THG (and drop W83627THF) because: - The W83627THF had a CIR device / LDN which doesn't actually exist. - The W83627THF had no GPIO2, GPIO3 LDNs (were commented out). - The W83627THF didn't use the PNP_MSC0/1 which is needed/used by boards. This also fixes an issue on MSI MS7135's devicetree.cb: device pnp 4e.6 off end # XXX keep allocator happy The line above can be (and is) removed, as it was only needed due to the incorrect CIR LDN in the W83627THF. In the iwill/dk8x target: Drop incorrect LDNs 4 and 6, add 0xb. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6080 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-16Drop commented out debug definesPatrick Georgi
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6079 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-16Move the SET_FIDVID* family of configuration options to Kconfig andPatrick Georgi
make their defaults more obvious. Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6077 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-14CK804/MCP55 devicetree.cb cosmetic and indentation fixes.Uwe Hermann
Add a few more comments for the entries, and also change the devicetree.cb files to the more compact and better readable variant with indentation level of 2 spaces (instead of random mix of tabs and spaces). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6071 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07Move K8_ALLOCATE_IO_RANGE to Kconfig.Patrick Georgi
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6036 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-06Remove comments that are obsolete since r6028.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6029 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-05Move QRANK_DIMM_SUPPORT to Kconfig, removing it from romstage.cPatrick Georgi
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6028 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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