ms7135: add ACPI support

Change-Id: I64a74d3dc0ea2d006ed4b25657d531fb243c2993
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/140
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

3 files changed, 548 insertions, 0 deletions

diff --git a/src/mainboard/msi/ms7135/Kconfig b/src/mainboard/msi/ms7135/Kconfig
index 586d403c25..c08a16939f 100644
--- a/src/mainboard/msi/ms7135/Kconfig
+++ b/src/mainboard/msi/ms7135/Kconfig
@@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select CK804_USE_NIC
 	select CK804_USE_ACI
 	select QRANK_DIMM_SUPPORT
+	select HAVE_ACPI_TABLES
 
 config MAINBOARD_DIR
 	string
diff --git a/src/mainboard/msi/ms7135/acpi_tables.c b/src/mainboard/msi/ms7135/acpi_tables.c
new file mode 100644
index 0000000000..5d5b288b6d
--- /dev/null
+++ b/src/mainboard/msi/ms7135/acpi_tables.c
@@ -0,0 +1,278 @@
+/*
+ * ACPI support
+ * written by Stefan Reinauer <stepan@openbios.org>
+ *  (C) 2005 Stefan Reinauer
+ *
+ *
+ *  Copyright 2005 AMD
+ *  2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <cpu/amd/amdk8_sysconf.h>
+#include "../../../northbridge/amd/amdk8/acpi.h"
+//#include <cpu/amd/model_fxx_powernow.h>
+
+extern const unsigned char AmlCode[];
+
+static void acpi_create_hpet_new(acpi_hpet_t *);
+static int acpi_create_hpet_new_fill(acpi_hpet_t *, u32, u16, u8);
+static unsigned long acpi_fill_hpet_new(unsigned long);
+
+void acpi_create_hpet_new(acpi_hpet_t *hpet)
+{
+	acpi_header_t *header=&(hpet->header);
+	unsigned long current=(unsigned long)hpet;
+
+	memset((void *)hpet, 0, sizeof(acpi_hpet_t));
+
+	/* fill out header fields */
+	memcpy(header->signature, "HPET", 4);
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+	memcpy(header->asl_compiler_id, ASLC, 4);
+
+	header->length = sizeof(acpi_hpet_t);
+	header->revision = 1;
+
+	current = acpi_fill_hpet_new(current);
+
+	/* recalculate length */
+	header->length = current - (unsigned long)hpet;
+
+	header->checksum	= acpi_checksum((void *)hpet, header->length);
+}
+
+
+int acpi_create_hpet_new_fill(acpi_hpet_t *hpet, u32 base, u16 min, u8 attr)
+{
+	static u8 num = 0;
+	acpi_addr_t *addr = &(hpet->addr);
+
+	hpet->id = read32(base + 0x000);
+
+	/* fill out HPET address */
+	addr->space_id		= 0; /* Memory */
+	addr->bit_width		= 0;
+	addr->bit_offset	= 0;
+	addr->addrl		= base;
+	addr->addrh		= 0;
+
+	hpet->number	= num++;
+	hpet->min_tick  = min;
+	hpet->attributes = attr;
+
+	return (sizeof(acpi_hpet_t));
+}
+
+static unsigned long acpi_fill_hpet_new(unsigned long current)
+{
+#if 1
+	device_t dev;
+	unsigned long hpet_base;
+
+	dev = dev_find_slot(0x0, PCI_DEVFN(0x1,0));
+	if (!dev)
+		return current;
+
+	hpet_base = pci_read_config32(dev, 0x44) & ~0xf;
+
+	printk(BIOS_INFO, "hpet_base %lx.\n", hpet_base);
+
+	current += acpi_create_hpet_new_fill((acpi_hpet_t *)current, hpet_base, 250, 1);
+#endif
+
+	return current;
+}
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+	device_t dev;
+	unsigned long mcfg_base;
+
+	dev = dev_find_slot(0x0, PCI_DEVFN(0x0,0));
+	if (!dev)
+		return current;
+
+	mcfg_base = pci_read_config16(dev, 0x90);
+	if ((mcfg_base & 0x1000) == 0)
+		return current;
+
+	mcfg_base = (mcfg_base & 0xf) << 28;
+
+	printk(BIOS_INFO, "mcfg_base %lx.\n", mcfg_base);
+
+	current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)
+			current, mcfg_base, 0x0, 0x0, 0xff);
+	return current;
+}
+
+/* APIC */
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	unsigned long apic_addr;
+	device_t dev;
+
+	/* create all subtables for processors */
+	current = acpi_create_madt_lapics(current);
+
+	/* Write NVIDIA CK804 IOAPIC. */
+	dev = dev_find_slot(0x0, PCI_DEVFN(0x1,0));
+	if (dev) {
+		apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1) & ~0xf;
+		current += acpi_create_madt_ioapic(
+			(acpi_madt_ioapic_t *)current,
+			CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS,
+			apic_addr, 0);
+		/* Initialize interrupt mapping if mptable.c didn't. */
+#if (!CONFIG_GENERATE_MP_TABLE)
+#error untested config
+		{
+			u32 dword;
+			dword = 0x0120d218;
+			pci_write_config32(dev, 0x7c, dword);
+
+			dword = 0x12008a00;
+			pci_write_config32(dev, 0x80, dword);
+
+			dword = 0x0000007d;
+			pci_write_config32(dev, 0x84, dword);
+		}
+#endif
+	}
+
+	/* IRQ of timer */
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+		current, 0, 0, 2, 0);
+	/* IRQ9 */
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+		current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
+
+	/* create all subtables for processors */
+	/* acpi_create_madt_lapic_nmis returns current, not size. */
+	current = acpi_create_madt_lapic_nmis(current,
+			MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
+
+	return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) {
+	k8acpi_write_vars();
+	//amd_model_fxx_generate_powernow(0, 0, 0);
+	return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+	unsigned long current;
+	acpi_rsdp_t *rsdp;
+	acpi_srat_t *srat;
+	acpi_rsdt_t *rsdt;
+	acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_mcfg_t *mcfg;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+	acpi_slit_t *slit;
+	acpi_header_t *ssdt;
+	acpi_header_t *dsdt;
+
+	/* Align ACPI tables to 16 byte. */
+	start = (start + 0x0f) & -0x10;
+	current = start;
+
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
+
+	/* We need at least an RSDP and an RSDT Table */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+
+	current = ALIGN(current, 16);
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+
+	/* Clear all table memory. */
+	memset((void *) start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt, NULL);
+	acpi_write_rsdt(rsdt);
+
+	current = ALIGN(current, 64);
+	facs = (acpi_facs_t *) current;
+	printk(BIOS_DEBUG, "ACPI:    * FACS %p\n", facs);
+	current += sizeof(acpi_facs_t);
+	acpi_create_facs(facs);
+
+	/* DSDT */
+	current = ALIGN(current, 16);
+	dsdt = (acpi_header_t *) current;
+	printk(BIOS_DEBUG, "ACPI:    * DSDT %p\n", dsdt);
+	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+	current += dsdt->length;
+	memcpy(dsdt, &AmlCode, dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n",dsdt,dsdt->length);
+
+	current = ALIGN(current, 16);
+	fadt = (acpi_fadt_t *) current;
+	printk(BIOS_DEBUG, "ACPI:    * FACP (FADT) @ %p\n", fadt);
+	current += sizeof(acpi_fadt_t);
+
+	/* Add FADT now that we have facs and dsdt. */
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdp, fadt);
+
+	current = ALIGN(current, 16);
+	mcfg = (acpi_mcfg_t *) current;
+	printk(BIOS_DEBUG, "ACPI:    * MCFG @ %p\n", mcfg);
+	acpi_create_mcfg(mcfg);
+	current += mcfg->header.length;
+	acpi_add_table(rsdp, mcfg);
+
+	current = ALIGN(current, 16);
+	hpet = (acpi_hpet_t *) current;
+	printk(BIOS_DEBUG, "ACPI:    * HPET @ %p\n", hpet);
+	acpi_create_hpet_new(hpet);
+	acpi_add_table(rsdp, hpet);
+	current += hpet->header.length;
+
+	current = ALIGN(current, 16);
+	madt = (acpi_madt_t *) current;
+	printk(BIOS_DEBUG, "ACPI:    * APIC/MADT @ %p\n", madt);
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	acpi_add_table(rsdp, madt);
+
+	current = ALIGN(current, 16);
+	srat = (acpi_srat_t *) current;
+	printk(BIOS_DEBUG, "ACPI:    * SRAT @ %p\n", srat);
+	acpi_create_srat(srat);
+	current += srat->header.length;
+	acpi_add_table(rsdp, srat);
+
+	/* SLIT */
+	current = ALIGN(current, 16);
+	slit = (acpi_slit_t *) current;
+	printk(BIOS_DEBUG, "ACPI:    * SLIT @ %p\n", slit);
+	acpi_create_slit(slit);
+	current+=slit->header.length;
+	acpi_add_table(rsdp,slit);
+
+	/* SSDT */
+	current = ALIGN(current, 16);
+	ssdt = (acpi_header_t *)current;
+	printk(BIOS_DEBUG, "ACPI:    * SSDT @ %p\n", ssdt);
+	acpi_create_ssdt_generator(ssdt, "DYNADATA");
+	current += ssdt->length;
+	acpi_add_table(rsdp, ssdt);
+
+	printk(BIOS_INFO, "ACPI: done %p.\n", (void *)current);
+	return current;
+}
diff --git a/src/mainboard/msi/ms7135/dsdt.asl b/src/mainboard/msi/ms7135/dsdt.asl
new file mode 100644
index 0000000000..090a3b2860
--- /dev/null
+++ b/src/mainboard/msi/ms7135/dsdt.asl
@@ -0,0 +1,269 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
+ * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+ * ISA portions taken from QEMU acpi-dsdt.dsl.
+ */
+
+DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE  ", "CB-DSDT ", 1)
+{
+	#include "northbridge/amd/amdk8/util.asl"
+
+	/* For now only define 2 power states:
+	 *  - S0 which is fully on
+	 *  - S5 which is soft off
+	 * Any others would involve declaring the wake up methods.
+	 */
+	Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
+	Name (\_S5, Package () { 0x07, 0x00, 0x00, 0x00 })
+
+	Name (PICM, 0x00)
+	Method (_PIC, 1, Serialized) {
+		Store (Arg0, PICM)
+	}
+
+	/* Root of the bus hierarchy */
+	Scope (\_SB)
+	{
+		/* Top PCI device (CK804) */
+		Device (PCI0)
+		{
+			Name (_HID, EisaId ("PNP0A03"))
+			Name (_ADR, 0x00)
+			Name (_UID, 0x00)
+			Name (_BBN, 0x00)
+
+			External (BUSN)
+			External (MMIO)
+			External (PCIO)
+			External (SBLK)
+			External (TOM1)
+			External (HCLK)
+			External (SBDN)
+			External (HCDN)
+
+			Method (_CRS, 0, NotSerialized)
+			{
+				Name (BUF0, ResourceTemplate ()
+				{
+					IO (Decode16,
+					0x0CF8,	// Address Range Minimum
+					0x0CF8,	// Address Range Maximum
+					0x01,	// Address Alignment
+					0x08,	// Address Length
+					)
+					WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+					0x0000,	// Address Space Granularity
+					0x0000,	// Address Range Minimum
+					0x0CF7,	// Address Range Maximum
+					0x0000,	// Address Translation Offset
+					0x0CF8,	// Address Length
+					,, , TypeStatic)
+				})
+				/* Methods bellow use SSDT to get actual MMIO regs
+				   The IO ports are from 0xd00, optionally an VGA,
+				   otherwise the info from MMIO is used.
+				   \_SB.GXXX(node, link)
+				 */
+				Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
+				Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
+				Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
+				Return (Local3)
+			}
+
+#include "southbridge/nvidia/ck804/acpi/ck804.asl"
+
+			/* PCI Routing Table */
+			Name (_PRT, Package () {
+				Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LLAS, 0x00 },
+				Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LLAS, 0x00 },
+				Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LUOH, 0x00 },
+				Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LUEH, 0x00 },
+				Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LAUD, 0x00 },
+				Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LMOD, 0x00 },
+				Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LPA0, 0x00 },
+				Package (0x04) { 0x0007FFFF, 0x00, \_SB.PCI0.LSA0, 0x00 },
+				Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LSA1, 0x00 },
+
+				Package (0x04) { 0x0009FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
+				Package (0x04) { 0x0009FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+				Package (0x04) { 0x0009FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+				Package (0x04) { 0x0009FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
+
+				Package (0x04) { 0x000AFFFF, 0x00, \_SB.PCI0.LEMA, 0x00 },
+
+				Package (0x04) { 0x000BFFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
+				Package (0x04) { 0x000BFFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+				Package (0x04) { 0x000BFFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+				Package (0x04) { 0x000BFFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
+
+				Package (0x04) { 0x000CFFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
+				Package (0x04) { 0x000CFFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+				Package (0x04) { 0x000CFFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+				Package (0x04) { 0x000CFFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
+
+				Package (0x04) { 0x000DFFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },
+				Package (0x04) { 0x000DFFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
+				Package (0x04) { 0x000DFFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },
+				Package (0x04) { 0x000DFFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },
+
+				Package (0x04) { 0x000EFFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },
+				Package (0x04) { 0x000EFFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
+				Package (0x04) { 0x000EFFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
+				Package (0x04) { 0x000EFFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
+			})
+
+			Device (PCIC)
+			{
+				Name (_ADR, 0x00090000)
+				Name (_UID, 0x00)
+				Name (_PRT, Package () {
+					/* AGR slot */
+					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 },
+					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x10 },
+					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 },
+					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 },
+				})
+			}
+
+			/* 2:00 PCIe x1 */
+			Device (PEX1)
+			{
+				Name (_ADR, 0x000d0000)
+				Name (_UID, 0x00)
+			}
+
+			/* 3:00 PCIe x16 */
+			Device (PEX0)
+			{
+				Name (_ADR, 0x000e0000)
+				Name (_UID, 0x00)
+			}
+
+			Device (LPC) {
+				Name (_HID, EisaId ("PNP0A05"))
+				Name (_ADR, 0x00010000)
+
+				OperationRegion (CF44, PCI_Config, 0x44, 0x04)
+				Field (CF44, ByteAcc, NoLock, Preserve)
+				{
+					ETBA, 32,
+				}
+
+				/* PS/2 keyboard (seems to be important for WinXP install) */
+				Device (KBD)
+				{
+					Name (_HID, EisaId ("PNP0303"))
+					Method (_STA, 0, NotSerialized)
+					{
+						Return (0x0f)
+					}
+					Method (_CRS, 0, NotSerialized)
+					{
+						Name (TMP, ResourceTemplate () {
+							IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
+							IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
+							IRQNoFlags () {1}
+						})
+						Return (TMP)
+					}
+				}
+
+				/* PS/2 mouse */
+				Device (MOU)
+				{
+					Name (_HID, EisaId ("PNP0F13"))
+					Method (_STA, 0, NotSerialized)
+					{
+						Return (0x0f)
+					}
+					Method (_CRS, 0, NotSerialized)
+					{
+						Name (TMP, ResourceTemplate () {
+							IRQNoFlags () {12}
+						})
+						Return (TMP)
+					}
+				}
+
+				/* Parallel port */
+				Device (LP0)
+				{
+					Name (_HID, EisaId ("PNP0400")) // "PNP0401" for ECP
+					Method (_STA, 0, NotSerialized)
+					{
+						Return (0x0f)
+					}
+					Method (_CRS, 0, NotSerialized)
+					{
+						Name (TMP, ResourceTemplate () {
+							FixedIO (0x0378, 0x10)
+							IRQNoFlags () {7}
+						})
+						Return (TMP)
+					}
+				}
+
+				/* Floppy controller */
+				Device (FDC0)
+				{
+					Name (_HID, EisaId ("PNP0700"))
+					Method (_STA, 0, NotSerialized)
+					{
+						Return (0x0f)
+					}
+					Method (_CRS, 0, NotSerialized)
+					{
+						Name (BUF0, ResourceTemplate () {
+							FixedIO (0x03F0, 0x08)
+							IRQNoFlags () {6}
+							DMA (Compatibility, NotBusMaster, Transfer8) {2}
+						})
+						Return (BUF0)
+					}
+				}
+#if 0
+				Device (HPET)
+				{
+					Name (_HID, EisaId ("PNP0103"))
+					Name (CRS, ResourceTemplate ()
+					{
+						Memory32Fixed (ReadOnly,
+						0x00000000,
+						0x00001000,
+						_Y02)
+					})
+					Method (_STA, 0, NotSerialized)
+					{
+						Return (0x0F)
+					}
+					Method (_CRS, 0, NotSerialized)
+					{
+						CreateDWordField (CRS, \_SB.PCI0.LPC.HPET._Y02._BAS, HPT)
+						Store (ETBA, HPT)
+						Return (CRS)
+					}
+						
+				}
+#endif
+			}
+		}
+	}
+}